SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 FEATURES • • • • • • • • • • • • • • Member of the Texas Instruments Widebus™ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Outputs (100 mA) LVTTL Outputs (–24 mA/24 mA) Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DGG PACKAGE (TOP VIEW) OEAB LEAB A1 A2 GND A3 VCC A4 A5 GND A6 A7 A8 GND A9 VCC A10 GND A11 A12 GND A13 A14 GND A15 VCC A16 ERC A17 A18 OEBA LEBA 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 CEAB CLKAB B1 B2 GND B3 BIAS VCC B4 B5 GND B6 B7 B8 GND B9 VCC B10 GND B11 B12 GND B13 B14 GND B15 VREF B16 GND B17 B18 CLKBA CEBA DESCRIPTION The SN74GTLPH1612 is a high-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 Ω. GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH1612 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT, TI-OPC, OEC, TI are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2005, Texas Instruments Incorporated SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 DESCRIPTION (CONTINUED) Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. Active bus-hold circuitry is provided to hold unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) 2 TSSOP – DGG Tape and reel ORDERABLE PART NUMBER SN74GTLPH1612DGGR TOP-SIDE MARKING GTLPH1612 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 FUNCTIONAL DESCRIPTION The SN74GTLPH1612 is a high-drive (100 mA), 18-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of the functions shown in Table 1. Data polarity is noninverting. Table 1. SN74GTLPH1612 UBT Transceiver Replacement Functions 8 BIT 9 BIT 10 BIT 16 BIT 18 BIT Transceiver FUNCTION '245, '623, '645 '863 '861 '16245, '16623 '16863 Buffer/driver '241, '244, '541 '827 '16241, '16244, '16541 '16825 '16543 '16472 '16373 '16843 '16646, '16652 '16474 Latched transceiver '543 Latch '373, '573 Registered transceiver '646, '652 Flip-flop '374, '574 '843 '841 '821 '16374 Standard UBT '16500, '16501 Universal bus driver '16835 Registered transceiver with clock enable '2952 Flip-flop with clock enable '377 '16470, '16952 '823 '16823 Standard UBT with clock enable '16600, '16601 SN74GTLPH1612 UBT transceiver replaces all above functions xxx Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA), and output enables (OEAB and OEBA). CEAB and CEBA and OEAB and OEBA control the 18 bits of data for the A-to-B and B-to-A directions, respectively. For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data is latched, regardless of the state of CLKAB (high or low) and if LEAB is high, the device is in transparent mode. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. The data flow for B to A is similar to that of A to B, except that CEBA, OEBA, LEBA, and CLKBA are used. FUNCTION TABLES SPACE HOLDER OUTPUT ENABLE (1) INPUTS CEAB OEAB LEAB CLKAB A OUTPUT B MODE X H X X X Z Isolation (1) (2) (3) (2) L L L H X B0 L L L L X B0 (3) X L H X L L X L H X H H L L L ↑ L L L L L ↑ H H H L L X X B0 (3) Latched storage of A data True transparent Clocked storage of A data Clock inhibit A-to-B data flow is shown: B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and CLKBA. The condition when OEAB and OEBA are both low at the same time is not recommended. Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low Output level before the indicated steady-state input conditions were established 3 SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 B-PORT EDGE-RATE CONTROL (ERC) INPUT ERC LOGIC LEVEL NOMINAL VOLTAGE OUTPUT B-PORT EDGE RATE L GND Slow H VCC Fast LOGIC DIAGRAM (POSITIVE LOGIC) 39 VREF 28 ERC 1 OEAB CEAB 64 63 CLKAB 2 LEAB 32 LEBA 34 CLKBA CEBA 33 31 OEBA CE 1D 3 A1 C1 CLK CE 1D C1 CLK To 17 Other Channels 4 62 B1 SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC BIAS VCC Supply voltage range VI Input voltage range (2) VO Voltage range applied to any output in the high-impedance or power-off state (2) IO Current into any output in the low state IO Current into any A-port output in the high state (3) MIN MAX –0.5 4.6 A-port, ERC, and control inputs –0.5 7 B port and VREF –0.5 4.6 A port –0.5 7 B port –0.5 4.6 A port 48 B port 200 UNIT V V V mA 48 mA ±100 mA IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA 55 °C/W 150 °C Continuous current through each VCC or GND θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) impedance (4) –65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. 5 SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 Recommended Operating Conditions (1) (2) (3) (4) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 B port VTT Except B port B port ERC Except B port and ERC VCC 5.5 VCC 5.5 Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC Power-up ramp rate TA Operating free-air temperature VCC – 0.6 (2) (3) (4) 6 V V 2 VREF – 0.05 ERC GND Except B port and ERC (1) V VREF + 0.05 B port VIL V 0.6 V 0.8 A port –18 mA –24 mA A port 24 B port 100 Outputs enabled 10 ns/V µs/V 20 –40 mA 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but generally, GND is connected first. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 Electrical Characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port VCC = 3.15 V, II = –18 mA VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC – 0.2 IOH = –12 mA 2.4 IOH = –24 mA 2 VCC = 3.15 V VCC = 3.15 V to 3.45 V, A port VCC = 3.15 V VOL B port II Control inputs IOZH (2) A port B port MIN TYP (1) TEST CONDITIONS VCC = 3.15 V VCC = 3.45 V, VCC = 3.45 V MAX UNIT –1.2 V V IOL = 100 µA 0.2 IOL = 12 mA 0.4 IOL = 24 mA 0.5 IOL = 10 mA 0.2 IOL = 64 mA 0.4 IOL = 100 mA 0.55 VI = 0 or 5.5 V ±10 VO = VCC 10 VO = 1.5 V 10 IOZL (2) A and B ports VCC = 3.45 V, VO = GND IBHL (3) A port VCC = 3.15 V, VI = 0.8 V (4) –10 V µA µA µA 75 µA A port VCC = 3.15 V, VI = 2 V –75 µA IBHLO (5) A port VCC = 3.45 V, VI = 0 to VCC 500 µA IBHHO (6) A port VCC = 3.45 V, VI = 0 to VCC –500 µA ICC A or B port VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND, VI (B port) = VTT or GND IBHH Cio (1) (2) (3) (4) (5) (6) (7) 45 Outputs low 45 Outputs disabled 45 VCC = 3.45 V, One A-port or control input at VCC – 0.6 V, Other A-port or control inputs at VCC or GND ∆ICC (7) Ci Outputs high mA 1.5 mA pF Control inputs VI = 3.15 V or 0 4 5.5 A port VO = 3.15 V or 0 6.5 8 B port VO = 1.5 V or 0 9.5 11.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameters IOZH and IOZL include the input leakage current. The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Hot-Insertion Specifications for A Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS MIN MAX UNIT 10 µA OE = 0 ±30 µA OE = 0 ±30 µA VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, 7 SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 Live-Insertion Specifications for B Port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN µA ±30 µA VO = 0.5 V to 1.5 V, OE = 0 ±30 µA 5 mA 10 µA BIAS VCC = 0, VI or VO = 0 to 1.5 V IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, ICC (BIAS VCC) VCC = 3.15 V to 3.45 V UNIT VO = 0.5 V to 1.5 V, OE = 0 VCC = 0, VCC = 0 to 3.15 V MAX 10 Ioff BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0 to 1.5 V VO VCC = 0, BIAS VCC = 3.3 V, IO VCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V IO = 0 0.95 1.05 V µA –1 Timing Requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (normal mode) (unless otherwise noted) MIN fclock tw tsu th 8 Clock frequency Pulse duration Setup time Hold time LEAB or LEBA high 3 CLKAB or CLKBA high or low 3 A before CLKAB↑ 2.2 B before CLKBA↑ 2.4 A before LEAB↓, CLK = Don't care 1.8 B before LEBA↓, CLK = Don't care 2.1 CEAB before CLKAB↑ 1.5 CEBA before CLKBA↑ 1.5 A after CLKAB↑ 0.7 B after CLKBA↑ 0.5 A after LEAB↓, CLK = Don't care 1.2 B after LEBA↓, CLK = Don't care 0.9 CEAB after CLKAB↑ 1.5 CEBA after CLKBA↑ 1.5 MAX UNIT 175 MHz ns ns ns SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (normal mode) (see Figure 1) PARAMETER TO (OUTPUT) EDGE RATE (1) MIN TYP (2) MAX fmax 175 tPLH 4.2 5.6 7.1 3 4.4 6.3 tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis ten tdis A B Slow A B Fast LEAB B Slow LEAB B Fast CLKAB B Slow CLKAB B Fast OEAB B Slow OEAB B Fast tr Rise time, B outputs (20% to 80%) tf Fall time, B outputs (80% to 20%) tPLH tPHL tPLH tPHL tPLH tPHL ten tdis (1) (2) FROM (INPUT) B A LEBA A CLKBA A OEBA A UNIT MHz 3 4.3 5.7 2.6 3.8 5.3 4.6 6.1 7.7 3.3 4.7 6.5 3.4 4.8 6.2 3 4.2 5.7 4.7 6.2 7.7 3.2 4.7 6.4 3.5 4.9 6.2 2.9 4.2 5.6 3 4.6 6.5 4.6 6 7.5 2.7 4.1 5.6 3.4 4.8 6.2 Slow 2.5 Fast 1.3 Slow 3.3 Fast 2.5 ns ns ns ns ns ns ns ns ns ns 1.3 2.9 4.6 1.6 3 4.2 1.5 3.2 4.6 1.5 3 3.9 1.5 3.3 4.8 1.5 3 4.2 1.2 2.5 5 2.3 3.8 5.5 ns ns ns ns Slow (ERC = GND) and Fast (ERC = VCC) All typical values are at VCC = 3.3 V, TA = 25°C. 9 SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test 1.5 V 6V Open S1 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR A OUTPUTS LOAD CIRCUIT FOR B OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION tsu th VOH Data Input VM VM 0V 3V Input 1.5 V 1.5 V 0V tPLH tPHL VOLTAGE WAVEFORMS SETUP AND HOLD TIMES (VM = 1.5 V for A port and 1 V for B port) (VOH = 3 V for A port and 1.5 V for B port) VOH Output 1V 1V 3V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1V 1V 0V tPLH 1.5 V tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL VOH Output 1.5 V tPZL 1.5 V Input Output Control Output Waveform 2 S1 at GND (see Note B) tPHZ VOH 1.5 V VOH − 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 10 SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 22 Ω 0.25” ZO = 50 Ω 1” Conn. 1” Conn. 1” Conn. Conn. 1” 1” 0.25 ” 22 Ω 1.5 V 1.5 V 1” Rcvr Rcvr Rcvr Slot 2 Slot 19 Slot 20 Drvr Slot 1 Figure 2. High-Drive Test Backplane 1.5 V 11 Ω From Output Under Test LL = 14 nH Test Point CL = 18 pF Figure 3. High-Drive RLC Network 11 SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis ten tdis (1) (2) 12 FROM (INPUT) TO (OUTPUT) EDGE RATE (1) A B Slow A B Fast LEAB B Slow LEAB B Fast CLK B Slow CLK B Fast OEAB B Slow OEAB B Fast tr Rise time, B outputs (20% to 80%) tf Fall time, B outputs (80% to 20%) Slow (ERC = GND) and Fast (ERC = VCC) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. TYP (2) 5.3 5.3 4 4 5.2 5.2 3.9 3.9 5.5 5.5 4.3 4.3 5.7 4.3 4.3 3.8 Slow 2 Fast 1.2 Slow 2.5 Fast 1.8 UNIT ns ns ns ns ns ns ns ns ns ns PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74GTLPH1612DGGRE4 ACTIVE TSSOP DGG 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH1612DGGR ACTIVE TSSOP DGG 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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