ELPIDA HB52R1289E2U-B6B

HB52R1289E2U-A6B/B6B
Description
L
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1 GB Registered SDRAM DIMM
128-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module
(36 pcs of 64 M × 4 Components)
PC100 SDRAM
E0016H10 (1st edition)
(Previous ADE-203-1194A (Z))
Preliminary
Jan. 30, 2001
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The HB52R1289E2U belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been
developed as an optimized main memory solution for 8-byte processor applications. The HB52R1289E2U is
a 64M × 72 × 2-bank Synchronous Dynamic RAM Module, mounted 36 pieces of 256-Mbit SDRAM
(HM5225405BTB) sealed in TCP package, 1 piece of PLL clock driver, 3 pieces register driver and 1 piece of
serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52R1289E2U is 168-pin socket type
package (dual lead out). Therefore, the HB52R1289E2U makes high density mounting possible without
surface mount technology. The HB52R1289E2U provides common data inputs and outputs. Decoupling
capacitors are mounted beside TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would
be electrical defects.
Features
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• Fully compatible with : JEDEC standard outline 8-byte DIMM
: Intel PCB Reference design (Rev. 1.2)
• 168-pin socket type package (dual lead out)
 Outline: 133.35 mm (Length) × 30.48 mm (Height) × 4.80 mm (Thickness)
 Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed RAS
Preliminary: The Specifications of this device are subject to change without notice. Please contact to your
nearest Elpida Memory, Inc.regarding specifications.
This product became EOL in September, 2002.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52R1289E2U-A6B/B6B
4 Banks can operates simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8
2 variations of burst sequence
 Sequential
 Interleave
Programmable CE latency : 3/4 (HB52R1289E2U-A6B)
: 4 (HB52R1289E2U-B6B)
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64 ms
2 variations of refresh
 Auto refresh
 Self refresh
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•
•
•
•
•
•
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Ordering Information
Type No.
Frequency
CE latency
Package
HB52R1289E2U-A6B
100 MHz
3/4
168-pin dual lead out socket type Gold
HB52R1289E2U-B6B
100 MHz
4
1 pin 10 pin 11 pin
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Pin Arrangement
Contact pad
40 pin 41 pin
85 pin 94 pin 95 pin 124 pin 125 pin
84 pin
168 pin
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Preliminary Data Sheet E0016H10
2
HB52R1289E2U-A6B/B6B
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VSS
43
VSS
85
VSS
127
VSS
2
DQ0
44
NC
86
DQ32
128
CKE0
3
DQ1
45
S2
87
DQ33
129
S3
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VCC
48
NC
90
VCC
132
NC
7
DQ4
49
VCC
91
DQ36
133
VCC
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VCC
101
DQ45
143
VCC
18
VCC
60
DQ20
102
VCC
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
105
CB4
147
REGE
22
CB1
64
VSS
23
VSS
65
DQ21
24
NC
66
DQ22
25
NC
67
DQ23
26
VCC
68
VSS
27
W
69
DQ24
28
DQMB0
70
DQ25
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29
DQMB1
71
30
S0
31
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Pin No.
Pr
CB5
148
VSS
107
VSS
149
DQ53
108
NC
150
DQ54
109
NC
151
DQ55
110
VCC
152
VSS
111
CE
153
DQ56
112
DQMB4
154
DQ57
DQ26
113
DQMB5
155
DQ58
72
DQ27
114
S1
156
DQ59
NC
73
VCC
115
RE
157
VCC
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
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106
Preliminary Data Sheet E0016H10
3
HB52R1289E2U-A6B/B6B
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CK2
121
A9
163
CK3
38
A10 (AP)
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
VCC
82
SDA
124
VCC
166
SA1
41
VCC
83
SCL
125
CK1
167
SA2
42
CK0
84
VCC
126
A12
168
VCC
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Pin No.
Pin Description
A0 to A12
L
Pin name
BA0/BA1
CB0 to CB7
S0 to S3
RE
Address input
Row address
A0 to A12
Column address
A0 to A9, A11
Bank select address
BA0/BA1
Pr
DQ0 to DQ63
Function
Data input/output
Check bit (Data input/output)
Chip select input
Row enable (RAS) input
CE
Column enable (CAS) input
W
Write enable input
od
DQMB0 to DQMB7
Byte data mask
CK0 to CK3
Clock input
CKE0
Clock enable input
WP
Write protect for serial PD
1
Register enable
SDA
Data input/output for serial PD
SCL
Clock input for serial PD
SA0 to SA2
Serial address input
VCC
Primary positive power supply
VSS
Ground
NC
No connection
Note:
1. REGE is the Register Enable pin which permits the DIMM to operate in “buffered” mode and
“registered” mode. To conform to this specification, mother boards must pull this pin to high state
(“registerd” mode).
Preliminary Data Sheet E0016H10
4
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REGE*
HB52R1289E2U-A6B/B6B
Serial PD Matrix*1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
Total SPD memory size
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
0
0
04
SDRAM
3
Number of row addresses bits
0
0
0
0
1
1
0
1
0D
13
4
Number of column addresses
bits
0
0
0
0
1
0
1
1
0B
11
5
Number of banks
0
0
0
0
0
0
1
0
02
2
6
Module data width
0
1
0
0
1
0
0
0
48
72 bit
7
Module data width (continued)
0
0
0
0
0
0
0
00
0 (+)
8
Module interface signal levels
0
0
0
0
0
0
0
1
01
LVTTL
9
L
0
SDRAM cycle time
(highest CE latency)
10 ns
1
0
1
0
0
0
0
0
A0
CL = 3
10
SDRAM access from Clock
(highest CE latency)
6 ns
0
1
1
0
0
0
0
0
60
*3
11
Module configuration type
0
0
0
0
0
0
1
0
02
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82
Normal
(7.8125 µs)
Self refresh
13
SDRAM width
0
0
0
0
0
1
0
0
04
64M × 4
14
Error checking SDRAM width
0
0
0
0
0
1
0
0
04
×4
15
SDRAM device attributes:
0
minimum clock delay for back-toback random column addresses
0
0
0
0
0
0
1
01
1 CLK
16
SDRAM device attributes:
Burst lengths supported
0
0
0
0
1
1
1
1
0F
1, 2, 4, 8
17
SDRAM device attributes:
number of banks on SDRAM
device
0
0
0
0
0
1
0
0
04
4
18
SDRAM device attributes:
CE latency
(-A6B)
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
EO
Byte No. Function described
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SDRAM device attributes:
S latency
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19
Pr
(-B6B)
0
06
2/3
0
04
3
1
01
0
Preliminary Data Sheet E0016H10
5
HB52R1289E2U-A6B/B6B
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
W latency
0
0
0
0
0
0
0
1
01
0
21
SDRAM device attributes
0
0
0
1
0
1
1
0
16
Registered
EO
22
SDRAM device attributes:
General
0
0
0
0
1
1
1
0
0E
VCC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
(-A6B) 10 ns
1
0
1
0
0
0
0
0
A0
CL = 2
0
0
0
0
0
0
0
0
00
0
1
1
0
0
0
0
0
60
0
0
0
0
0
0
0
0
00
(-B6B) Undefined
24
SDRAM access from Clock
(2nd highest CE latency)
(-A6B) 6 ns
L
(-B6B) Undefined
SDRAM cycle time
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
26
SDRAM access from Clock
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time
0
0
0
1
0
1
0
0
14
20 ns
28
Row active to row active min
0
0
0
1
0
1
0
0
14
20 ns
29
RE to CE delay min
0
0
0
1
0
1
0
0
14
20 ns
30
Minimum RE pulse width
0
0
1
1
0
0
1
0
32
50 ns
31
Density of each bank on module 1
0
0
0
0
0
0
0
80
2 bank
512M byte
32
Address and command signal
input setup time
0
0
1
33
Address and command signal
input hold time
0
0
0
34
Data signal input setup time
0
0
1
35
Data signal input hold time
0
0
0
36 to 61 Superset information
0
0
0
62
SPD data revision code
0
0
63
Checksum for bytes 0 to 62
(-A6B)
0
od
Pr
25
0
0
0
0
20
2 ns* 3
1
0
0
0
0
10
1 ns* 3
0
0
0
0
0
20
2 ns* 3
1
0
0
0
0
10
1 ns* 3
0
0
0
0
0
00
Future use
0
1
0
0
1
0
12
Rev. 1.2A
0
0
1
1
0
1
1
1B
27
0
0
0
1
1
0
0
1
19
25
Manufacturer’s JEDEC ID code
0
0
0
0
0
1
1
1
07
HITACHI
65 to 71 Manufacturer’s JEDEC ID code
0
0
0
0
0
0
0
0
00
72
×
×
×
×
×
×
×
×
××
(-B6B)
64
Manufacturing location
Preliminary Data Sheet E0016H10
6
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0
* 4 (ASCII8bit code)
HB52R1289E2U-A6B/B6B
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
73
Manufacturer’s part number
0
1
0
0
1
0
0
0
48
H
74
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
75
Manufacturer’s part number
0
0
1
1
0
1
0
1
35
5
76
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
77
Manufacturer’s part number
0
1
0
1
0
0
1
0
52
R
78
Manufacturer’s part number
0
0
1
1
0
0
0
1
31
1
79
Manufacturer’s part
0
0
1
1
0
0
1
0
32
2
80
Manufacturer’s part number
0
0
1
1
1
0
0
0
38
8
81
Manufacturer’s part number
0
0
1
1
1
0
0
1
39
9
82
Manufacturer’s part number
0
1
0
0
0
1
0
1
45
E
83
Manufacturer’s part number
0
1
1
0
0
1
0
32
2
84
Manufacturer’s part number
0
1
0
1
0
1
0
1
55
U
85
Manufacture’s part number
0
0
1
0
1
1
0
1
2D
—
86
L
0
Manufacturer’s part number
(-A6B)
0
1
0
0
0
0
0
1
41
A
0
1
0
0
0
0
1
0
42
B
EO
Byte No. Function described
Pr
(-B6B)
Manufacturer’s part number
0
0
1
1
0
1
1
0
36
6
88
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
89
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
90
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
91
Revision code
0
0
1
1
0
0
0
0
30
Initial
92
Revision code
0
0
1
0
0
0
0
0
20
(Space)
93
Manufacturing date
×
×
×
×
×
×
×
×
××
Year code
(BCD)*5
94
Manufacturing date
×
×
×
×
×
×
×
×
××
Week code
(BCD) *5
od
87
*7
99 to 125 Manufacturer specific data
—
—
—
—
—
—
—
—
—
*6
126
Intel specification frequency
0
1
1
0
0
1
0
0
64
100 MHz
127
Intel specification CE#
latency support
(-A6B)
1
0
0
0
0
1
1
1
87
CL = 2/3
1
0
0
0
0
1
0
1
85
CL = 3
(-B6B)
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95 to 98 Assembly serial number
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”
These SPD are based on Intel specification (Rev.1.2A).
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte10, 23, 24, 32 through 35 are component spec.
4. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
Preliminary Data Sheet E0016H10
7
HB52R1289E2U-A6B/B6B
5. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary
Coded Decimal”.
6. All bits of 99 through 125 are not defined (“1” or “0”).
7. Bytes 95 through 98 are assembly serial number.
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Preliminary Data Sheet E0016H10
8
HB52R1289E2U-A6B/B6B
Block Diagram
RS0
EO
RS1
RDQMB0
4
DQ0 to DQ3
4
DQ4 to DQ7
10 Ω
10 Ω
RDQMB4
DQMB CS
I/O0
to I/O3
D0
DQMB CS
I/O0
to I/O3
D1
DQMB CS
DQMB CS
D18
I/O0
to I/O3
10 Ω
DQ8 to DQ11
10 Ω
DQ12 to DQ15
CB0 to CB3
10 Ω
RS2
RS3
RDQMB2
I/O0
to I/O3
D2
DQMB CS
I/O0
to I/O3
D3
I/O0
to I/O3
D4
4
10 Ω
4
10 Ω
4
10 Ω
DQ36 to DQ39
I/O0
to I/O3
DQMB CS
D10
I/O0
to I/O3
D28
I/O0
to I/O3
DQ40 to DQ43
DQMB CS
DQ44 to DQ47
DQMB CS
I/O0
to I/O3
I/O0
to I/O3
CB4 to CB7
I/O0
to I/O3
D29
DQMB CS
D12
I/O0
to I/O3
D30
DQMB CS
DQMB CS
D22
I/O0
to I/O3
I/O0
to I/O3
D11
DQMB CS
D21
I/O0
to I/O3
DQMB CS
DQMB CS
D20
Pr
4
10 Ω
DQ16 to DQ19
I/O0
to I/O3
D5
DQMB CS
4
10 Ω
RDQMB3
I/O0
to I/O3
D6
D13
I/O0
to I/O3
D31
DQMB CS
I/O0
to I/O3
D23
4
10 Ω
4
10 Ω
DQ48 to DQ51
DQMB CS
I/O0
to I/O3
D24
DQ52 to DQ55
DQMB CS
I/O0
to I/O3
DQMB CS
D14
I/O0
to I/O3
DQMB CS
DQMB CS
I/O0
to I/O3
D32
D15
I/O0
to I/O3
D33
RDQMB7
4
10 Ω
DQ24 to DQ27
I/O0
to I/O3
D7
DQMB CS
4
10 Ω
DQ28 to DQ31
I/O0
to I/O3
D8
DQMB CS
I/O0
to I/O3
D25
I/O0
to I/O3
4
10 Ω
4
10 Ω
DQ56 to DQ59
DQMB CS
D26
DQMB CS
I/O0
to I/O3
D16
DQ60 to DQ63
10k
RS0, RS1, RS2, RS3
RDQMB0 to RDQMB7
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35 CK1
RA0 to RA12 -> A0 to A12: SDRAMs D0 to D35
to CK3
RRAS -> RAS: SDRAMs D0 to D35
RCAS -> CAS: SDRAMs D0 to D35
VCC
RCKE0 -> CKE: SDRAMs D0 to D35
0.0022 µF × 26 pcs
RW -> WE: SDRAMs D0 to D35
VSS
Serial PD
SCL
SCL
SDA
U0
A0
A1
SDA
WP
A2
47 kΩ
SA0 SA1 SA2 VSS
Notes:
1. The SDA pull-up resistor is required due to the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
D34
DQMB CS
D17
I/O0
to I/O3
R1
I/O0
to I/O3
D35
PLL
12 pF
CK : SDRAMs
(D0 to D35)
Register
R2 to R4
VSS
12 pF
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R
E
G
I
S
T
E
R
I/O0
to I/O3
DQMB CS
CK0
S0, S1, S2, S3
DQMB0 to DQMB7
BA0 to BA1
A0 to A12
RE
CE
CKE0
W
DQMB CS
od
DQMB CS
VCC
REGE
PLL CK
D27
DQMB CS
DQMB CS
D19
I/O0
to I/O3
I/O0
to I/O3
RDQMB6
DQMB CS
DQ20 to DQ23
10 Ω
I/O0
to I/O3
DQMB CS
D9
RDQMB5
DQMB CS
DQMB CS
4
4
DQMB CS
L
4
10 Ω
DQ32 to DQ35
RDQMB1
4
4
VCC (D0 to D35, U0)
0.22 µF × 19 pcs
VSS (D0 to D35, U0)
* D0 to D35: HM5225405
PLL: 2510
Register: 16834
U0: 2-kbit EEPROM
Preliminary Data Sheet E0016H10
9
HB52R1289E2U-A6B/B6B
Absolute Maximum Ratings
Symbol
Value
Unit
Note
Voltage on any pin relative to V SS
VT
–0.5 to VCC + 0.5
(≤ 4.6 (max))
V
1
Supply voltage relative to VSS
VCC
–0.5 to +4.6
V
1
Short circuit output current
Iout
50
mA
Power dissipation
PT
18.0
W
Operating temperature
Topr
0 to +55
°C
Storage temperature
Tstg
–50 to +100
°C
EO
Parameter
Note:
1. Respect to V SS
L
DC Operating Conditions (Ta = 0 to +55°C)
Parameter
Supply voltage
Input low voltage
Ambient illuminance
Max
Unit
Notes
VCC
3.0
3.6
V
1, 2
VSS
0
0
V
3
VIH
2.0
VCC
V
1, 4
VIL
0
0.8
V
1, 5
—
—
100
lx
All voltage referred to VSS
The supply voltage with all VCC and V CCQ pins must be on the same level.
The supply voltage with all VSS and VSS Q pins must be on the same level.
VIH (max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.
VIL (min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS .
t
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Notes: 1.
2.
3.
4.
5.
Min
Pr
Input high voltage
Symbol
Preliminary Data Sheet E0016H10
10
HB52R1289E2U-A6B/B6B
VIL/VIH Clamp (Component characteristics)
This SDRAM component has VIL and V IH clamp for CK, CKE, S, DQMB and DQ pins.
EO
Minimum VIL Clamp Current
VIL (V)
I (mA)
–2
–32
–1.8
–25
–1.6
–19
–1.4
–13
–1.2
–8
L
–1
–0.9
–0.8
–0.6
–0.4
–4
–2
–0.6
0
0
Pr
–0.2
0
0
0
0
–2
–5
I (mA)
–15
–20
–25
–30
–35
–1
–0.5
0
od
–10
–1.5
VIL (V)
t
uc
Preliminary Data Sheet E0016H10
11
HB52R1289E2U-A6B/B6B
Minimum VIH Clamp Current (referred to VIH)
VIH (V)
I (mA)
VCC + 2
10
EO
VCC + 1.8
8
VCC + 1.6
5.5
VCC + 1.4
3.5
VCC + 1.2
1.5
VCC + 1
0.3
VCC + 0.8
0
VCC + 0.6
0
VCC + 0.4
0
VCC + 0
L
VCC + 0.2
0
0
10
I (mA)
6
4
2
VCC + 0.5
od
0
VCC + 0
Pr
8
VCC + 1
VCC + 1.5
VCC + 2
VIH (V)
t
uc
Preliminary Data Sheet E0016H10
12
HB52R1289E2U-A6B/B6B
IOL/IOH Characteristics (Component characteristics)
Output Low Current (IOL)
EO
I OL
Vout (V)
Min (mA)
Max (mA)
0
0
0
0.4
27
71
0.65
41
108
0.85
51
134
1
58
151
1.4
70
188
72
194
75
203
77
209
1.95
77
212
3
80
220
81
223
L
I OL
1.5
1.65
1.8
Pr
3.45
250
IOL (mA)
150
100
50
0
0
0.5
1
1.5
2
Vout (V)
2.5
3
min
max
t
uc
od
200
3.5
Preliminary Data Sheet E0016H10
13
HB52R1289E2U-A6B/B6B
Output High Current (I OH ) (Ta = 0 to 55˚C, V CC = 3.0 V to 3.45 V, VSS = 0 V)
I OH
I OH
Min (mA)
Max (mA)
3.45
—
–3
3.3
—
–28
3
0
–75
2.6
–21
–130
2.4
–34
–154
2
–59
–197
1.8
–67
–227
1.65
–73
–248
Vout (V)
L
EO
1.5
1.4
1
0
–200
–300
–400
–500
0.5
–81
–285
–89
–345
–93
–503
1
1.5
2
2.5
3.5
Vout (V)
Preliminary Data Sheet E0016H10
min
max
t
uc
–600
14
3
od
IOH (mA)
–100
0
–270
Pr
0
–78
HB52R1289E2U-A6B/B6B
DC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52R1289E2U
EO
-A6B
-B6B
Symbol
Min
Max
Min
Max
Unit
Test conditions
Notes
Operating current
(CE latency = 3)
—
2945
—
—
mA
Burst length = 1
t RC = min
1, 2, 3
I CC1
(CE latency = 4)
I CC1
—
2945
—
2945
mA
Standby current in power I CC2P
down
—
803
—
803
mA
CKE = VIL, t CK = 12
ns
6
Standby current in power I CC2PS
down (input signal stable)
—
767
—
767
mA
CKE = VIL, t CK = ∞
7
Standby current in non
power down
I CC2N
—
1415
—
1415
mA
CKE, S = VIH,
t CK = 12 ns
4
Active standby current in
power down
I CC3P
—
839
—
839
mA
CKE = VIL, t CK = 12
ns
1, 2, 6
Active standby current in
non power down
I CC3N
—
1775
—
1775
mA
CKE, S = VIH,
t CK = 12 ns
1, 2, 4
t CK = min, BL = 4
1, 2, 5
t RC = min
3
8
L
Parameter
I CC4
Pr
Burst operating current
(CE latency = 3)
—
2945
—
—
mA
—
2945
—
2945
mA
—
5195
—
—
mA
—
5195
—
5195
mA
—
803
—
803
mA
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
I CC4
Refresh current
(CE latency = 3)
I CC5
(CE latency = 4)
I CC5
Self refresh current
I CC6
Input leakage current
I LI
–10
10
–10
10
µA
0 ≤ Vin ≤ VCC
Output leakage current
I LO
–10
10
–10
10
µA
0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage
VOH
2.4
—
2.4
—
V
I OH = –4 mA
Output low voltage
VOL
—
0.4
—
0.4
V
I OL = 4 mA
od
(CE latency = 4)
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Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
Preliminary Data Sheet E0016H10
15
HB52R1289E2U-A6B/B6B
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Symbol
Max
Unit
Notes
Input capacitance (Address)
CI1
25
pF
1, 2, 4
Input capacitance (RE, CE, W)
CI2
25
pF
1, 2, 4
Input capacitance (CKE)
CI3
45
pF
1, 2, 4
Input capacitance (S)
CI4
20
pF
1, 2, 4
Input capacitance (CK)
CI5
45
pF
1, 2, 4
Input capacitance (DQMB)
CI6
20
pF
1, 2, 4
Input/Output capacitance (DQ)
CI/O1
25
pF
1, 2, 3, 4
EO
Parameter
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
DQMB = VIH to disable Data-out.
This parameter is sampled and not 100% tested.
L
Notes: 1.
2.
3.
4.
AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Pr
HB52R1289E2U
-A6B/B6B
PC100
Symbol
Min
Max
Unit
Notes
t CK
Tclk
10
—
ns
1
t CK
Tclk
10
—
ns
CK high pulse width
t CKH
Tch
4
—
ns
1
CK low pulse width
t CKL
Tcl
4
—
ns
1
Access time from CK
(CE latency = 3)
t AC
Tac
—
7.5
ns
1, 2
(CE latency = 4)
t AC
Tac
—
7.5
ns
Data-out hold time
t OH
Toh
2.1
—
ns
1, 2
CK to Data-out low impedance
t LZ
1.1
—
ns
1, 2, 3
CK to Data-out high impedance
t HZ
—
7.5
ns
1, 4
Data-in setup time
t DS
Tsi
2.9
—
ns
1
Data in hold time
t DH
Thi
3.4
—
ns
1
Address setup time
t AS
Tsi
2.6
—
ns
1
Address hold time
t AH
Thi
3.0
—
ns
1, 5
CKE setup time
t CES
Tsi
2.6
—
ns
1, 5
CKE setup time for power down exit
t CESP
Tpde
2.6
—
ns
1
System clock cycle time
(CE latency = 3)
(CE latency = 4)
Preliminary Data Sheet E0016H10
16
t
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od
Symbol
Parameter
HB52R1289E2U-A6B/B6B
AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (cont)
HB52R1289E2U
-A6B/B6B
EO
Symbol
PC100
Symbol
Min
Max
Unit
Notes
CKE hold time
t CEH
Thi
3.0
—
ns
1
Command setup time
t CS
Tsi
2.6
—
ns
1
Command hold time
t CH
Thi
3.0
—
ns
1
Ref/Active to Ref/Active command period t RC
Trc
70
—
ns
1
Active to precharge command period
t RAS
Tras
50
120000
ns
1
Active command to column command
(same bank)
t RCD
Trcd
20
—
ns
1
Precharge to active command period
t RP
Trp
20
—
ns
1
Write recovery or data-in to precharge
lead time
t DPL
Tdpl
20
—
ns
1
Active (a) to Active (b) command period
t RRD
Trrd
20
—
ns
1
Transition time (rise to fall)
tT
1
5
ns
t REF
—
64
ms
L
Parameter
Pr
Refresh period
Notes: 1.
2.
3.
4.
5.
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V.
Access time is measured at 1.5 V. Load condition is C L = 50 pF.
t LZ (max) defines the time at which the outputs achieves the low impedance state.
t HZ (max) defines the time at which the outputs achieves the high impedance state.
t CES defines CKE setup time to CK rising edge except power down exit command.
od
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
• Ambient illuminance: Under 100 lx
0.4 V
t
uc
2.4 V
input
DQ
2.0 V
0.8 V
CL
t
T
tT
Preliminary Data Sheet E0016H10
17
HB52R1289E2U-A6B/B6B
Relationship Between Frequency and Minimum Latency
HB52R1289E2U
Frequency (MHz)
-A6B/B6B
EO
Parameter
PC100
Symbol Symbol 10
Notes
Active command to column command (same bank)
I RCD
2
1
Active command to active command (same bank)
I RC
7
= [IRAS + IRP]
1
Active command to precharge command (same bank)
I RAS
5
1
Precharge command to active command (same bank)
I RP
2
1
Write recovery or data-in to precharge command
(same bank)
I DPL
2
1
Active command to active command (different bank)
I RRD
2
1
Self refresh exit time
I SREX
Tsrx
2
2
Last data in to active command
(Auto precharge, same bank)
I APW
Tdal
4
= [IDPL + IRP]
Self refresh exit to command input
I SEC
7
= [IRC]
3
L
tCK (ns)
Pr
Precharge command to high impedance
(CE latency = 3)
(CE latency = 4)
Tdpl
I HZP
Troh
3
I HZP
Troh
4
I APR
Last data out to precharge (early precharge)
(CE latency = 3)
od
(CE latency = 4)
Column command to column command
Write command to data in latency
0
I EP
–2
I EP
–3
I CCD
Tccd
1
I WCD
Tdwd
1
I DID
Tdqm
1
I DOD
Tdqz
3
CKE to CK disable
I CLE
Tcke
2
Register set to active command
I RSA
Tmrd
1
S to command disable
I CDD
0
Power down exit to command input
I PEC
1
Burst stop to output valid data hold
(CE latency = 3)
I BSR
2
I BSR
3
DQMB to data in
DQMB to data out
(CE latency = 4)
Preliminary Data Sheet E0016H10
18
t
uc
Last data out to active command (auto precharge)
(same bank)
HB52R1289E2U-A6B/B6B
Parameter
HB52R1289E2U
Frequency (MHz)
-A6B/B6B
PC100
Symbol Symbol 10
tCK (ns)
EO
Burst stop to output high impedance
(CE latency = 3)
(CE latency = 4)
Burst stop to write data ignore
I BSH
3
I BSH
4
I BSW
1
Notes
Notes: 1. I RCD to IRRD are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP]
L
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Pr
Preliminary Data Sheet E0016H10
19
HB52R1289E2U-A6B/B6B
Pin Functions
EO
CK0 to CK3 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK
rising edge.
S0 to S3 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operation section.
L
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY9, AY11) is determined by A0 to A9, A11 level
at the read or write command cycle CK rising edge. And this column address becomes burst access start
address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are
precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by
BA0/BA1 (BA) is precharged.
Pr
BA0/BA1 (input pin): BA0/BA1 are bank select signal (BA). The memory array is divided into bank 0,
bank 1, bank 2 and bank 3. If BA0 is Low and BA1 is Low, bank 0 is selected. If BA0 is High and BA1 is
Low, bank 1 is selected. If BA0 is Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is
High, bank 3 is selected.
CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK
rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and
clock suspend modes.
od
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If
the DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,
the data is written.
DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins.
VSS (power supply pins): Ground is connected.
t
uc
VCC (power supply pins): 3.3 V is applied.
REGE (input pins): If REGE is High, the register is ″registered″ mode. If REGE is Low, the register is
″buffered″ mode.
Detailed Operaion Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet.
Preliminary Data Sheet E0016H10
20
HB52R1289E2U-A6B/B6B
Physical Outline
Unit: mm
inch
EO
Front side
133.35
5.25
3.00
0.118
(DATUM -A-)
4.80 max
0.189 max
3.00
0.118
Component area
(Front)
84
L
B
C
Back side
85
Component area
(Back)
3.125 ± 0.125
6.35
0.250
2.00 ± 0.10
0.079 ± 0.004
1.00
0.039
Note: Tolerance on all dimensions ± 0.15/0.006 unless otherwise specified.
0.123 ± 0.005
0.123 ± 0.005
0.20 ± 0.15
0.010 ± 0.0004
Detail C
(DATUM -A-)
R FULL
6.35
0.250
4.175
0.164
2.00 ± 0.10
0.079 ± 0.004
t
uc
1.00 ± 0.05
0.039 ± 0.002
1.27
0.050
Detail B
R FULL
3.125 ± 0.125
Detail A
od
(DATUM -A-)
2.50 ± 0.20
0.098 ± 0.008
4.00
0.157
127.35
5.014
Pr
2 – φ 3.00
2 – φ 0.118
1.27
0.050
54.61
2.150
30.48
1.20
0.450
A
36.83
1.450
17.80
0.70
11.43
168
1
4.00 min
0.157 min
(63.67)
(2.51)
ED480120W
Preliminary Data Sheet E0016H10
21
HB52R1289E2U-A6B/B6B
Cautions
L
EO
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any
third party’s patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information contained in this
document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause
risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage
when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally
foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as
fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury,
fire or other consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
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Pr
Preliminary Data Sheet E0016H10
22