STMICROELECTRONICS HCF4094B

HCF4094B
8 STAGE SHIFT AND STORE BUS REGISTER
WITH 3-STATE OUTPUTS
■
■
■
■
■
■
■
■
3-STATE PARALLEL OUTPUTS FOR
CONNECTION TO COMMON BUS
SEPARATE SERIAL OUTPUTS
SYNCHRONOUS TO BOTH POSITIVE AND
NEGATIVE CLOCK EDGES FOR
CASCADING
MEDIUM SPEED OPERATION 5MHz at 10V
QUIESCENT CURRENT SPECIFIED UP TO
20V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
DESCRIPTION
The HCF4094B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4094B is an 8 stages serial shift register
having a storage latch associated with each stage
for strobing data from the serial input to parallel
buffered 3-state outputs. The parallel outputs may
be connected directly to common bus lines. Data
is shifted on positive clock transition. The data in
each shift register stage is transferred to the
DIP
SOP
ORDER CODES
PACKAGE
TUBE
T&R
DIP
SOP
HCF4094BEY
HCF4094BM1
HCF4094M013TR
storage register when the STROBE input is high.
Data in the storage register appears at the outputs
whenever the OUTPUT-ENABLE signal is high.
Two serial outputs are available for cascading a
number of HCF4094B devices. Data is available
at the QS serial output terminal on positive clock
edges to allow for high speed operation in
cascaded system in which the clock rise time is
fast. The same serial information, available at the
Q’S terminal on the next negative clock edge,
provides a means for cascading HCF4094B
devices when the clock rise time is slow.
PIN CONNECTION
March 2004
1/13
HCF4094B
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN N°
SYMBOL
2
1
3
DATA
STROBE
CLOCK
QS, Q’S
Data Input
Strobe Input
Clock Input
Q1 to Q8
Parallel Outputs
9, 10
4, 5, 6, 7, 14,
13, 12, 11
NAME AND FUNCTION
Serial Outputs
8
OUTPUT
ENABLE
VSS
Negative Supply Voltage
16
VDD
Positive Supply Voltage
15
Output Enable Input
FUNCTIONAL DIAGRAM
TRUTH TABLE
CLOCK
PARALLEL OUTPUTS
OUTPUTS
ENABLE
STROBE
L
X
L
SERIAL OUTPUTS
DATA
Q1
Qn
Q*S
Q’S
X
OC
OC
Q7
No Change
X
X
OC
OC
No Change
Q7
H
L
X
No Change
No Change
Q7
No Change
H
H
L
L
Qn - 1
Q7
No Change
H
H
H
H
Qn - 1
Q7
No Change
H
H
H
No Change
No Change
No Change
Q7
X : Don’t Care
OC : Open Circuit
* At the positive clock edge information on the 7th shift register stage is transferred to the 8th register stage and the QS output.
2/13
HCF4094B
LOGIC DIAGRAM
TIMING CHART
3/13
HCF4094B
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Supply Voltage
VI
DC Input Voltage
II
DC Input Current
PD
Value
Unit
-0.5 to +22
V
-0.5 to VDD + 0.5
± 10
V
mA
500 (*)
100
mW
mW
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
-55 to +125
°C
Tstg
Storage Temperature
-65 to +150
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
4/13
Parameter
Supply Voltage
VI
Input Voltage
Top
Operating Temperature
Value
Unit
3 to 20
V
0 to VDD
V
-55 to 125
°C
HCF4094B
DC SPECIFICATIONS
Test Condition
Symbol
IL
VOH
VOL
VIH
VIL
IOH
IOL
II
Parameter
Quiescent Current
High Level Output
Voltage
Low Level Output
Voltage
VI
(V)
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
High Level Input
Voltage
Low Level Input
Voltage
Output Drive
Current
Output Sink
Current
Input Leakage
Current
IOH, IOL 3-State Output
Leakage Current
Input Capacitance
CI
VO
(V)
0/5
0/5
0/10
0/15
0/5
0/10
0/15
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
Value
|IO| VDD
(µA) (V)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
TA = 25°C
Min.
Typ.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
4.95
9.95
14.95
-40 to 85°C
-55 to 125°C
Min.
Min.
150
300
600
3000
4.95
9.95
14.95
0.05
0.05
0.05
4.95
9.95
14.95
3.5
7
11
1.5
3
4
-3.2
-1
-2.6
-6.8
1
2.6
6.8
Max.
150
300
600
3000
0.05
0.05
0.05
3.5
7
11
-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0
Max.
3.5
7
11
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
µA
V
0.05
0.05
0.05
1.5
3
4
Unit
V
V
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
V
mA
mA
0/18
Any Input
18
±10-5 ± 0.1
±1
±1
µA
0/18
0/18
18
±10-4 ± 0.4
± 12
± 12
µA
Any Input
5
7.5
pF
The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
5/13
HCF4094B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
VDD (V)
tPLH tPHL Propagation Delay Time
(Clock to serial Output QS)
tPLH tPHL Propagation Delay Time
(Clock to serial Output Q’S)
tPLH tPHL Propagation Delay Time
(Clock to Parallel Output)
tPLH tPHL Propagation Delay Time
(Strobe to Parallel Output)
tPZL, tPZH Propagation Delay Time
Output Enable to Parallel Out:
Output High to High Impedance
tPHZ tPLZ Propagation Delay Time
Output Enable to Parallel Out:
Output Low to High Impedance
tW
tW
tsetup
thold
Strobe Pulse Width
Clock Pulse Width
Data Setup Time
Minimum Hold Time
tTLH tTHL Transition Time
tr, tf
fmax
Unit
Clock input Rise or Fall Time
Maximum Clock Input
Frequency
Typ.
Max.
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
300
125
95
230
110
75
420
195
135
290
145
100
140
75
55
600
250
190
460
220
150
840
390
270
580
290
200
280
150
110
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
225
95
70
100
40
35
100
50
40
60
30
20
0
0
0
100
50
40
450
190
140
(*) Typical temperature coefficient for all VDD value is 0.3%/°C.
6/13
Value (*)
Parameter
Min.
200
80
70
200
100
83
125
55
35
0
0
0
15
5
5
1.25
2.5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
200
100
80
ns
ns
µs
2.5
5
6
MHz
HCF4094B
TYPICAL APPLICATION (REMOTE CONTROL HOLDING REGISTER)
TEST CIRCUIT
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VCC
tPZH, tPHZ
GND
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
7/13
HCF4094B
WAVEFORM 1: PROPAGATION DELAY TIMES, PULSE WIDTH (CLOCK), SETUP AND HOLD TIME
(DATA IN TO CLOCK) (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAY TIME, PULSE WIDTH (STROBE), SETUP AND HOLD TIME
(STROBE TO CLOCK) (f=1MHz; 50% duty cycle)
8/13
HCF4094B
WAVEFORM 3: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
9/13
HCF4094B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
10/13
HCF4094B
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.004
0.008
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45˚ (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
8
0.024
˚ (max.)
PO13H
11/13
HCF4094B
Tape & Reel SO-16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
MAX.
MIN.
330
13.2
TYP.
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
12/13
TYP
0.504
22.4
0.519
0.882
Ao
6.45
6.65
0.254
0.262
Bo
10.3
10.5
0.406
0.414
Ko
2.1
2.3
0.082
0.090
Po
3.9
4.1
0.153
0.161
P
7.9
8.1
0.311
0.319
HCF4094B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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