INTERSIL HIP2100IR

HIP2100
®
Data Sheet
October 21, 2004
100V/2A Peak, Low Cost, High Frequency
Half Bridge Driver
The HIP2100 is a high frequency, 100V Half Bridge
N-Channel power MOSFET driver IC. The low-side and
high-side gate drivers are independently controlled and
matched to 8ns. This gives the user maximum flexibility in
dead-time selection and driver protocol. Undervoltage
protection on both the low-side and high-side supplies force
the outputs low. An on-chip diode eliminates the discrete
diode required with other driver ICs. A new level-shifter
topology yields the low-power benefits of pulsed operation
with the safety of DC operation. Unlike some competitors,
the high-side output returns to its correct state after a
momentary undervoltage of the high-side supply.
TEMP.
RANGE (°C)
Features
• Drives N-Channel MOSFET Half Bridge
• SOIC, EPSOIC, QFN and DFN Package Options
• SOIC, EPSOIC and DFN Packages Compliant with 100V
Conductor Spacing Guidelines of IPC-2221
• Pb-Free Product Available (RoHS Compliant)
• Bootstrap Supply Max Voltage to 114VDC
• On-Chip 1Ω Bootstrap Diode
• Fast Propagation Times for Multi-MHz Circuits
• Drives 1000pF Load with Rise and Fall Times Typ. 10ns
• CMOS Input Thresholds for Improved Noise Immunity
• Independent Inputs for Non-Half Bridge Topologies
Ordering Information
PART #
FN4022.13
PACKAGE
PKG.
DWG. #
M8.15
• No Start-Up Problems
• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground, or HS Slewing at High dv/dt
HIP2100IB
-40 to 125
8 Ld SOIC
HIP2100IBZ (Note 1)
-40 to 125
8 Ld SOIC (Pb-free) M8.15
• Low Power Consumption
HIP2100EIB
-40 to 125
8 Ld EPSOIC
M8.15C
• Wide Supply Range
HIP2100EIBZ
(Note 1)
-40 to 125
8 Ld EPSOIC
(Pb-free)
M8.15C
• Supply Undervoltage Protection
HIP2100IR
-40 to 125
16 Ld 5x5 QFN
L16.5x5
HIP2100IRZ (Note 1)
-40 to 125
16 Ld 5x5 QFN
(Pb-free)
L16.5x5
HIP2100IR4
-40 to 125
12 Ld 4x4 DFN
L12.4x4A
HIP2100IR4Z
(Note 1)
-40 to 125
12 Ld 4x4 DFN
(Pb-free)
L12.4x4A
• 3Ω Driver Output Resistance
• QFN/DFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
NOTES:
1. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020C.
• Telecom Half Bridge Power Supplies
• Avionics DC-DC Converters
• Two-Switch Forward Converters
• Active Clamp Forward Converters
2. Add “T” suffix for Tape and Reel packing option.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
HIP2100
Pinouts
6
LI
4
5
HI
12 LO
2
11 VSS
NC
3
HB
4
HO
HS
16
15
14
13
NC 1
10 NC
EPAD
NC
3
HS
1
NC
12 NC
HB 2
11 VSS
9
NC
5
8
LI
HO 3
10 LI
6
7
HI
NC 4
9
EPAD
NOTE: EPAD = Exposed PAD.
5
6
7
8
NC
HO
VDD
LO
VSS
EPAD
HI
LO
7
VDD
8
2
HS
1
HB
HIP2100 (QFN)
TOP VIEW
NC
VDD
HIP2100IR4 (DFN)
TOP VIEW
NC
HIP2100 (SOIC, EPSOIC)
TOP VIEW
NC
Application Block Diagram
+12V
+100V
SECONDARY
CIRCUIT
VDD
HB
DRIVE
HI
PWM
CONTROLLER
LI
CONTROL
HI
HS
DRIVE
LO
HIP2100
VSS
2
HO
LO
REFERENCE
AND
ISOLATION
FN4022.13
HIP2100
Functional Block Diagram
HB
VDD
UNDER
VOLTAGE
HO
LEVEL SHIFT
DRIVER
HS
HI
UNDER
VOLTAGE
LO
DRIVER
LI
VSS
EPAD (EPSOIC, QFN and DFN PACKAGES ONLY)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For
best thermal performance connect the EPAD to the PCB power ground plane.
+48V
+12V
PWM
HIP2100
SECONDARY
CIRCUIT
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
PWM
HIP2100
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP
3
FN4022.13
HIP2100
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD, VHB-VHS (Notes 3, 4) . . . . . . . . -0.3V to 18V
LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on HO (Note 4) . . . . . . . . . . . . . . . VHS -0.3V to VHB +0.3V
Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V
Average Current in VDD to HB diode . . . . . . . . . . . . . . . . . . . 100mA
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV)
Thermal Resistance (Typical)
Maximum Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . +9V to 14.0VDC
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS. . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . VHS +8V to VHS +14.0V and VDD -1V to VDD +100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
θJA (°C/W)
θJC (°C/W)
SOIC (Note 5) . . . . . . . . . . . . . . . . . . .
95
N/A
EPSOIC (Note 6) . . . . . . . . . . . . . . . . .
40
3.0
QFN (Note 6) . . . . . . . . . . . . . . . . . . . .
37
6.5
DFN (Note 6) . . . . . . . . . . . . . . . . . . . .
40
3.0
Max Power Dissipation at 25°C in Free Air (SOIC, Note 5). . . . . . 1.3W
Max Power Dissipation at 25°C in Free Air (EPSOIC, Note 6) . . . 3.1W
Max Power Dissipation at 25°C in Free Air (QFN, Note 6) . . . . . . 3.3W
Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . -55°C to 150°C
Lead Temperature (Soldering 10s - SOIC Lead Tips Only) . . 300°C
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
3. The HIP2100 is capable of derated operation at supply voltages exceeding 14V. Figure 16 shows the high-side voltage derating curve for this
mode of operation.
4. All voltages referenced to VSS unless otherwise specified.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
TJ = -40°C TO
125°C
TJ = 25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
SUPPLY CURRENTS
VDD Quiescent Current
IDD
LI = HI = 0V
-
0.1
0.15
-
0.2
mA
VDD Operating Current
IDDO
f = 500kHz
-
1.5
2.5
-
3
mA
Total HB Quiescent Current
IHB
LI = HI = 0V
-
0.1
0.15
-
0.2
mA
Total HB Operating Current
IHBO
f = 500kHz
-
1.5
2.5
-
3
mA
HB to VSS Current, Quiescent
IHBS
VHS = VHB = 114V
-
0.05
1
-
10
µA
HB to VSS Current, Operating
IHBSO
f = 500kHz
-
0.7
-
-
-
mA
INPUT PINS
Low Level Input Voltage Threshold
VIL
4
5.4
-
3
-
V
High Level Input Voltage Threshold
VIH
-
5.8
7
-
8
V
VIHYS
-
0.4
-
-
-
V
RI
-
200
-
100
500
kΩ
VDD Rising Threshold
VDDR
7
7.3
7.8
6.5
8
V
VDD Threshold Hysteresis
VDDH
-
0.5
-
-
-
V
HB Rising Threshold
VHBR
6.5
6.9
7.5
6
8
V
HB Threshold Hysteresis
VHBH
-
0.4
-
-
-
V
Input Voltage Hysteresis
Input Pulldown Resistance
UNDERVOLTAGE PROTECTION
4
FN4022.13
HIP2100
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
TJ = -40°C TO
125°C
TJ = 25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
BOOT STRAP DIODE
Low-Current Forward Voltage
VDL
IVDD-HB = 100µA
-
0.45
0.55
-
0.7
V
High-Current Forward Voltage
VDH
IVDD-HB = 100mA
-
0.7
0.8
-
1
V
Dynamic Resistance
RD
IVDD-HB = 100mA
-
0.8
1
-
1.5
Ω
LO GATE DRIVER
Low Level Output Voltage
VOLL
ILO = 100mA
-
0.25
0.3
-
0.4
V
High Level Output Voltage
VOHL
ILO = -100mA, VOHL = VDD-VLO
-
0.25
0.3
-
0.4
V
Peak Pullup Current
IOHL
VLO = 0V
-
2
-
-
-
A
Peak Pulldown Current
IOLL
VLO = 12V
-
2
-
-
-
A
Low Level Output Voltage
VOLH
IHO = 100mA
-
0.25
0.3
-
0.4
V
High Level Output Voltage
VOHH
IHO = -100mA, VOHH = VHB-VHO
-
0.25
0.3
-
0.4
V
Peak Pullup Current
IOHH
VHO = 0V
-
2
-
-
-
A
Peak Pulldown Current
IOLH
VHO = 12V
-
2
-
-
-
A
HO GATE DRIVER
Switching Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST
CONDITIONS
TJ = -40°C
TO 125°C
TJ = 25°C
MIN
TYP
MAX
MIN
MAX
UNITS
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
tLPHL
-
20
35
-
45
ns
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
tHPHL
-
20
35
-
45
ns
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
tLPLH
-
20
35
-
45
ns
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
tHPLH
-
20
35
-
45
ns
Delay Matching: Lower Turn-On and Upper Turn-Off
tMON
-
2
8
-
10
ns
Delay Matching: Lower Turn-Off and Upper Turn-On
tMOFF
-
2
8
-
10
ns
CL = 1000pF
-
10
-
-
-
ns
CL = 0.1µF
-
0.5
0.6
-
0.8
us
tRC, tFC
Either Output Rise/Fall Time
Either Output Rise/Fall Time (3V to 9V)
tR, tF
Either Output Rise Time Driving DMOS
tRD
CL = IRFR120
-
20
-
-
-
ns
Either Output Fall Time Driving DMOS
tFD
CL = IRFR120
-
10
-
-
-
ns
Minimum Input Pulse Width that Changes the Output
tPW
-
-
-
-
50
ns
Bootstrap Diode Turn-On or Turn-Off Time
tBS
-
10
-
-
-
ns
5
FN4022.13
HIP2100
Pin Descriptions
SYMBOL
DESCRIPTION
VDD
Positive Supply to lower gate drivers. De-couple this pin to VSS. Bootstrap diode connected to HB.
HB
High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
HO
High-Side Output. Connect to gate of High-Side power MOSFET.
HS
High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to
this pin.
HI
High-Side input.
LI
Low-Side input.
VSS
Chip negative supply, generally will be ground.
LO
Low-Side Output. Connect to gate of Low-Side power MOSFET.
EPAD
Exposed Pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Timing Diagrams
LI
HI
HI,
LI
tHPLH ,
tLPLH
tHPHL,
tLPHL
LO
tMOFF
tMON
HO,
LO
HO
FIGURE 3.
FIGURE 4.
10
10
1
1
0.1
0.01
10
IHBSO (mA)
IDDO, IHBO (mA)
Typical Performance Curves
T = 150°C
T = 125°C
T = 25°C
T = -40°C
100
FREQUENCY (kHz)
FIGURE 5. OPERATING CURRENT vs FREQUENCY
6
T = 150°C
T = -40°C
T = 125°C
T = 25°C
0.1
1000
0.01
10
100
FREQUENCY (kHz)
1000
FIGURE 6. HB TO VSS OPERATING CURRENT vs
FREQUENCY
FN4022.13
HIP2100
Typical Performance Curves
(Continued)
500
500
VHB = VDD = 9V
VHB = VDD = 9V
VHB = VDD = 12V
400
VHB = VDD = 14V
VOLL, VOLH (mV)
VOHL, VOHH (mV)
400
300
200
100
-50
VHB = VDD = 12V
VHB = VDD = 14V
300
200
0
50
100
100
-50
150
0
50
TEMPERATURE (°C)
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
0.54
0.5
VDDR
VHBH, VDDH (mV)
VHBR, VDDR (V)
7.4
7.2
7.0
VHBR
VDDH
0.46
0.42
0.38
VHBH
6.8
0.34
0
50
TEMPERATURE (°C)
100
0.3
-50
150
0
50
TEMPERATURE (°C)
100
150
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
2.5
30
tHPHL
2.0
tHPLH
tLPHL
25
tLPLH
IHO , ILO (A)
tLPLH, tLPHL, tHPLH, tHPHL (ns)
150
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
7.6
6.6
-50
100
TEMPERATURE (°C)
1.5
1.0
20
0.5
15
-50
0
0
50
TEMPERATURE (°C)
100
FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE
7
150
0
2
4
6
VHO , VLO (V)
8
10
12
FIGURE 12. PEAK PULLUP CURRENT vs OUTPUT VOLTAGE
FN4022.13
HIP2100
Typical Performance Curves
(Continued)
2.5
1
0.1
FORWARD CURRENT (A)
ILO, IHO (A)
2.0
1.5
1.0
0.5
0
0
2
4
6
VLO, VHO (V)
8
10
0.001
1•10-4
1•10-5
1•10-6
0.3
12
50
100
VHS TO VSS VOLTAGE (V)
120
IHB vs VHB
40
IDD vs VDD
30
20
10
0
5
10
VDD , VHB (V)
15
FIGURE 15. QUIESCENT CURRENT vs VOLTAGE
8
0.5
0.6
0.7
0.8
FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS
60
0
0.4
FORWARD VOLTAGE (V)
FIGURE 13. PEAK PULLDOWN CURRENT vs OUTPUT
VOLTAGE
IDD , IHB (µA)
0.01
80
60
40
20
0
12
14
15
VDD TO VSS VOLTAGE (V)
16
FIGURE 16. VHS VOLTAGE vs VDD VOLTAGE
FN4022.13
HIP2100
Dual Flat No-Lead Plastic Package (DFN)
Micro Lead Frame Plastic Package (MLFP)
L12.4x4A
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
2X
0.15
C
A
D
A
D/2
D1
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
-
0.85
0.90
-
A1
0.00
0.01
0.05
-
A2
-
0.65
0.70
-
0.30
5, 8
A3
0.20 REF
-
D1/2
b
2X
0.15
N
E1/2
E/2
C
B
D
4.00 BSC
-
3.75 BSC
-
2.65
E
0.15
9
C
B
1 2
E2
B
TOP VIEW
0.15
C
2X
A2
A
//
C
A1
A3
C
0.10
0.08
SEATING
PLANE
7, 8
SIDE VIEW
C
-
3.75 BSC
1.43
e
A
4X 0
2.95
4.00 BSC
E1
3
2X
2.80
E
6
INDEX
AREA
0.23
D1
D2
E1
0.18
1.58
1.73
7, 8
0.50 BSC
-
k
0.635
-
-
-
L
0.30
0.40
0.50
8
N
12
Nd
2
6
3
P
0.24
0.42
0.60
θ
-
-
12
Rev. 0 8/03
7
8
NOTES:
D2
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
(Nd-1)Xe
REF.
2. N is the number of terminals.
D2/2
1
3. Nd refer to the number of terminals on D.
2 3
4. All dimensions are in millimeters. Angles are in degrees.
6
INDEX
AREA
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX k
E2
7
8
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
E2/2
4X P
N N-1
NX b
0.10
e
5
M
C A B
BOTTOM VIEW
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for
the L dimension.
CL
NX b
A1
L
5
5
C C
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
9
FN4022.13
HIP2100
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.28
D
0.33
9
0.40
5, 8
5.00 BSC
D1
D2
9
0.20 REF
-
4.75 BSC
2.55
2.70
9
2.85
7, 8
E
5.00 BSC
-
E1
4.75 BSC
9
E2
2.55
e
2.70
2.85
7, 8
0.80 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
16
Nd
2
4
3
Ne
4
4
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 2 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
10
FN4022.13
HIP2100
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
µα
A1
B
0.25(0.010) M
C
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MAX
A1
e
0.10(0.004)
MIN
α
8
0o
8
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
11
FN4022.13
HIP2100
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15C
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
TOP VIEW
L
SEATING PLANE
-A-
-C-
µα
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
SIDE VIEW
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.056
0.066
1.43
1.68
-
A1
0.001
0.005
0.03
0.13
-
B
0.0138
0.0192
0.35
0.49
9
C
0.0075
0.0098
0.19
0.25
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.811
3.99
4
e
h x 45o
A
D
MIN
0.050 BSC
1.27 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
8o
0o
8o
-
N
α
8
0o
8
7
P
-
0.126
-
3.200
11
P1
-
0.099
-
2.514
11
Rev. 0 11/03
NOTES:
1
2
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
3
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
N
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN4022.13