IDT ICSSSTUAF32868AHLFT

DATASHEET
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Description
ICSSSTUAF32868A
QERR pin (active low). The convention is even parity, i.e.,
valid parity is defined as an even number of ones across the
DIMM-independent data inputs combined with the parity
input bit. To calculate parity, all DIMM-independent D-inputs
must be tied to a known logic state. If an error occurs and
the QERR output is driven low, it stays latched low for a
minimum of two clock cycles or until RESET is driven low. If
two or more consecutive parity errors occur, the QERR
output is driven low and latched low for a clock duration
equal to the parity error duration or until RESET is driven
low. If a parity error occurs on the clock cycle before the
device enters the low-power (LPM) and the QERR output is
driven low, then it stays lateched low for the LPM duration
plus two clock cycles or until RESET is driven low. The
DIMM-dependent signals (DCKE0, DCKE1, DODT0,
DODT1, DCS0 and DCS1) are not included in the parity
check computation.
This 28-bit 1:2 configurable registered buffer is designed for
1.7V to 1.9V VDD operation. All inputs are compatible with
the JEDEC standard for SSTL_18, except the chip-select
gate-enable (CSGEN), control (C), and reset (RESET)
inputs, which are LVCMOS. All outputs are edge-controlled
circuits optimized for unterminated DIMM loads, and meet
SSTL_18 specifications, except the open-drain error
(QERR) output.
The ICSSSTUAF32868A operates from a differential clock
(CLK and CLK). Data are registered at the crossing of CLK
going high and CLK going low. The device supports
low-power standby operation. When RESET is low, the
differential input receivers are disabled, and undriven
(floating) data, clock, and reference voltage (Vref) inputs
are allowed. In addition, when RESET is low, all registers
are reset and all outputs are forced low except QERR. The
LVCMOS RESET and C inputs must always be held at a
valid logic high or low level. To ensure defined outputs from
the register before a stable clock has been supplied,
RESET must be held in the low state during power up. In
the DDR2 RDIMM application, RESET is specified to be
completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be ensured between
the two. When entering reset, the register will be cleared
and the data outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. As long as the data inputs are low, and the clock
is stable during the time from the low-to-high transition of
RESET until the input receivers are fully enabled, the
design of the ICSSSTUAF32868A must ensure that the
outputs will remain low, thus ensuring no glitches on the
output.
The C input controls the pinout configuration from
register-A configuration (when low) to register-B
configuration (when high). The C input should not be
switched during normal operation. It should be hardwired to
a valid low or high level to configure the register in the
desired mode. The device also supports low-power active
operation by monitoring both system chip select (DCS0 and
DCS1) and CSGEN inputs and will gate the Qn outputs
from changing states when CSGEN, DCS0, and DCS1
inputs are high. If CSGEN, DCS0 orDCS1 input is low, the
Qn outputs will function normally. Also, if both DCS0 and
DCS1 inputs are high, the device will gate the QERR output
from changing states. If either DCS0 orDCS1 is low, the
QERR output will function normally. The RESET input has
priority over the DCS0 and DCS1 control and when driven
low will force the Qn outputs low, and the QERR output
high. If the chip-select control functionality is not desired,
then the CSGEN input can be hard-wired to ground, in
which case, the setup-time requirement for DCS0 and
DCS1 would be the same as for the other D data inputs. To
control the low-power mode with DCS0 and DCS1 only,
then the CSGEN input should be pulled up to Vdd through a
pullup resistor. The two VREF pins (A1 and V1) are
connected together internally by approximately 150.
However, it is necessary to connect only one of the two
VREF pins to the external VREF power supply. An unused
VREF pin should be terminated with a VREF coupling
capacitor.
The ICSSSTUAF32868A includes a parity checking
function. Parity, which arrives one cycle after the data input
to which it applies, is checked on the PAR_IN input of the
device. The corresponding QERR output signal for the data
inputs is generated two clock cycles after the data, to which
the QERR signal applies, is registered. The
ICSSSTUAF32868A accepts a parity bit from the memory
controller on the parity bit (PAR_IN) input, compares it with
the data received on the DIMM-independent D-inputs
(D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12,
D17-D20, D22, D24-D28 when C = 1) and indicates
whether a parity error has occurred on the open-drain
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
CONFIDENTIAL
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COMMERCIAL TEMPERATURE GRADE
Features
Applications
• 28-bit 1:2 registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
and outputs
ICS98ULPA877A or IDTCSPUA877A
• Supports LVCMOS switching levels on CSGEN and
• Ideal for DDR2 400, 533, and 667
RESET inputs
• Low voltage operation: VDD = 1.7V to 1.9V
• Available in 176-ball LFBGA package
Block Diagram
M2
RESET
CLK
CLK
L1
M1
VREF
A5, AB5
DCKE0,
DCKE1
D1, C1
2
F2, E2
QCKE0A,
QCKE1A
H8, F8
QCKE0B,
QCKE1B
D
2
2
CK
Q
R
DODT0,
DODT1
N1, P1
2
CK
Q
K1
D
CK
L2
DCS1
J1
M7, M8
QODT0B,
QODT1B
D
CK
K2
QCS0A
L7
QCS0B
J2
QCS1A
L8
QCS1B
Q
R
CSGEN
QODT0A,
QODT1A
2
R
DCS0
N2, P2
D
2
Q
R
One of 22 Channels
D1
A2
A7
CE
D
CK
R
Q1A
Q
A8
Q1B
TO 21 OTHER CHANNELS
(D2-D5, D7, D9-D12, D17-D28)
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Parity Logic Diagram
M2
RESET
CLK
CLK
L1
M1
D1-D5, D7,
D9-D12,
D17-D28
VREF
22
D1-D5, D7,
D9-D12,
D17-D28
D1-D5, D7,
D9-D12,
D17-D28
22
A5, AB5
D
22
CK
R
PAR_IN
Q1A-Q5A, Q7A,
Q9A-Q12A,
Q17A-Q28A
22
Q
CE
22
Q1B-Q5B, Q7B,
Q9B-Q12B,
Q17B-Q28B
22
D1-D5, D7,
D9-D12,
D17-D28
L3
D
CK
R
DCS0
Parity Generator
and
Error Check
Q
M3
CE
K1
K2
D
CK
L2
DCS1
J1
R
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
L7
D
CK
3
QCS0A
Q
R
CSGEN
QERR
QCS0B
J2
QCS1A
L8
QCS1B
Q
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28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Block Diagram
M2
RESET
CLK
CLK
L1
M1
VREF
A5, AB5
DCKE0,
DCKE1
W1, Y1
2
U2, V2
QCKE0A,
QCKE1A
R8, U8
QCKE0B,
QCKE1B
D
2
2
CK
Q
R
DODT0,
DODT1
K1, J1
2
CK
Q
R
DCS0
N1
D
CK
L2
DCS1
P1
QODT0A,
QODT1A
L7, L8
QODT0B,
QODT1B
D
CK
2
N2
QCS0A
M7
QCS0B
P2
QCS1A
M8
QCS1B
Q
R
CSGEN
K2, J2
D
2
Q
R
One of 22 Channels
D1
A2
A7
D CE
CK
R
Q1A
Q
A8
Q1B
TO 21 OTHER CHANNELS
(D2-D12, D17-D20, D22, D24-D28)
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Parity Logic Diagram
M2
RESET
CLK
CLK
L1
M1
D1-D12,
D17-D20,
D22,
D24-D28
VREF
22
D1-D12,
D17-D20, D22,
D24-D28
D1-D12,
D17-D20, D22,
D24-D28
22
A5, AB5
D
22
CK
R
PAR_IN
Q1A-Q12A,
Q17A-Q20A,
Q22A,
Q24A-Q28A
22
Q
Q1B-Q12B,
Q17B-Q20B,
Q22B,
Q24B-Q28B
22
CE
22
D1-D12,
D17-D20, D22,
D24-D28
L3
D
CK
R
DCS0
Parity Generator
and
Error Check
Q
M3
CE
N1
N2
D
CK
L2
DCS1
P1
R
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
M7
D
CK
5
QCS0A
Q
R
CSGEN
QERR
QCS0B
P2
QCS1A
M8
QCS1B
Q
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Pin Configuration
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
176 BALL BGA
TOP VIEW
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28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Pin Configuration
A
D2
D1
C
GND
VREF
GND
Q1A
Q1B
A
D2
D1
C
GND
VREF
GND
Q1A
Q1B
B
D4
D3
VDD
VDD
VDD
VDD
Q2A
Q2B
B
D4
D3
VDD
VDD
VDD
VDD
Q2A
Q2B
C
D6
(DCKE1)
D5
GND
GND
GND
GND
Q3A
Q3B
D
D8
(DCKE0)
D7
D7
VDD
VDD
VDD
VDD
Q4A
Q4B
D9
Q6A
(QCKE1A)
GND
GND
GND
GND
Q5A
Q5B
F
D10
Q8A
(QCKE0A)
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Q7A
Q6B
G
D11
Q10A
GND
GND
H
D12
Q12A
VDD
J
DCS1
QCS1
GND
E
K
D5
DCS0
QCS0
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
Q3A
Q4A
VDD
C
Q3B
D
Q4B
E
D6
D8
D9
Q6A
Q5A
Q5B
VDD
Q7A
Q6B
(QCKE0B)
F
D10
GND
GND
Q9A
Q7B
G
D11
Q10A
GND
GND
GND
GND
Q9A
Q7B
VDD
VDD
VDD
Q11A
Q8B
(QCKE0B)
H
D12
Q12A
VDD
VDD
VDD
VDD
Q11A
Q8B
GND
GND
GND
Q10B
Q9B
J
D13
(DODT1)
Q13A
(QODT1A)
GND
GND
GND
GND
Q10B
Q9B
K
D14
(DODT0)
Q14A
(QODT0A)
VDD
VDD
VDD
VDD
Q12B
Q11B
Q13B
(QODT1B)
GND
VDD
GND
VDD
GND
VDD
Q12B
Q11B
Q13B
(QCS1B)
L
Q8A
PAR_IN
GND
GND
GND
Q14B
(QODT0B)
RESET
QERR
VDD
VDD
VDD
Q15B
(QCS0B)
Q16B
(QCS1B)
D15
(DCS0)
Q15A
(QCS0A)
GND
GND
GND
GND
Q17B
Q18B
Q16A
(QCS1A)
VDD
VDD
VDD
VDD
Q19B
Q20B
Q17A
GND
GND
GND
GND
Q18A
Q21B
(QCKE0B)
L
CLK
CSGEN
PAR_IN
GND
GND
GND
Q14B
(QCS0B)
M
CLK
RESET
QERR
VDD
VDD
VDD
Q15B
(QODT0B)
Q16B
(QODT1B)
M
CLK
N
D15
(DODT0)
Q15A
(QODT0A)
GND
GND
GND
GND
Q17B
Q18B
N
CLK
CSGEN
P
D16
(DODT1)
Q16A
(QODT1A)
VDD
VDD
VDD
VDD
Q19B
Q20B
P
D16
(DCS1)
R
D17
Q17A
GND
GND
GND
GND
Q18A
Q21B
R
D17
T
D18
Q19A
VDD
VDD
VDD
VDD
Q20A
Q22B
T
D18
Q19A
VDD
VDD
VDD
VDD
Q20A
Q22B
GND
GND
GND
GND
Q22A
Q23B
(QCKE1B)
U
D19
Q21A
GND
GND
GND
GND
Q22A
Q23B
U
D19
Q21A
(QCKE0A)
V
D20
Q23A
VDD
VDD
VDD
VDD
Q24A
Q24B
V
D20
Q23A
(QCKE1A)
VDD
VDD
VDD
VDD
Q24A
Q24B
W
D21
D22
GND
GND
GND
GND
Q25A
Q25B
W
D21
(DCKE0)
D22
GND
GND
GND
GND
Q25A
Q25B
Y
D23
D24
VDD
VDD
VDD
VDD
Q26A
Q26B
Y
D23
(DCKE1)
D24
VDD
VDD
VDD
VDD
Q26A
Q26B
AA
D25
D26
GND
GND
GND
GND
Q27A
Q27B
AA
D25
D26
GND
GND
GND
GND
Q27A
Q27B
AB
D27
D28
NC
VDD
VREF
VDD
Q28A
Q28B
AB
D27
D28
NC
VDD
VREF
VDD
Q28A
Q28B
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1:2 REGISTER B (C = 1)
1:2 REGISTER A (C = 0)
NOTE: NC denotes a no-connect (ball present but not
connected to the die).
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COMMERCIAL TEMPERATURE GRADE
Function Table
Inputs1
Outputs
RESET
DCS0
DCS1
CSGEN
CLK
CLK
Dx, DODT,
DCKE
Qn
H
L
L
X
↑
↓
L
L
H
L
L
X
↑
↓
H
H
H
L
L
X
L or H
L or H
X
Q 02
H
L
H
X
↑
↓
L
L
H
L
H
X
↑
↓
H
H
H
L
H
X
L or H
L or H
X
Q 02
H
L
L
X
↑
↓
L
L
H
L
L
X
↑
↓
H
H
H
L
L
X
L or H
L or H
X
Q 02
H
H
H
L
↑
↓
L
L
H
H
H
L
↑
↓
H
H
H
H
H
L
L or H
L or H
X
Q 02
H
H
H
H
↑
↓
L
Q 02
H
H
H
H
↑
↓
H
Q 02
H
H
H
H
L or H
L or H
X
L
X or
Floating
X or
Floating
X or
Floating
1
2
X or
X or
X or Floating
Floating Floating
QCS0 QCS1 QODT,
QCKE
Q 02
Q 02
Q02
Q 02
Q 02
Q02
Q 02
Q 02
Q02
Q 02
Q 02
Q02
Q 02
Q 02
Q 02
Q02
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
Output Level before the indicated steady-state conditions were established.
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COMMERCIAL TEMPERATURE GRADE
Parity and Standby Function Table
Inputs1
Outputs
RESET
DCS0
DCS1
CLK
CLK
Σ of Inputs = H (D1 - D28)
PAR_IN2
H
L
X
↑
↓
Even
L
H
H
L
X
↑
↓
Odd
L
L
H
L
X
↑
↓
Even
H
L
H
L
X
↑
↓
Odd
H
H
H
X
L
↑
↓
Even
L
H
H
X
L
↑
↓
Odd
L
L
H
X
L
↑
↓
Even
H
L
H
X
L
↑
↓
Odd
H
H
H
H
H
↑
↓
X
X
QERR04
H
X
X
↑
↓
X
X
QERR0
L
X or
Floating
X or
Floating
X or
Floating
X or
Floating
X or Floating
X or Floating
H
QERR3
1
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2 PAR_IN arrives one clock cycle after the data to which it applies.
3 This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
4 If DCS0, DCS1, and CSGEN are driven HIGH, the device is placed in low-power mode (LPM). If a parity
error occurs on the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays
latched LOW for the LPM plus two clock cycles or until RESET is driven LOW.
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Absolute Maximum Ratings
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Item
Rating
Supply Voltage, VDD
-0.5V to 2.5V
1
-0.5V to VDD + 2.5V
VO1,2
-0.5V to VDDQ + 0.5V
Input Voltage Range, VI
Output Voltage Range,
Input Clamp Current, IIK
±50mA
Output Clamp Current, IOK
±50mA
Continuous Output Clamp Current, IO
±50mA
Continuous Current through each VDD or GND
±100mA
Package Thermal Impedance (θja)3
0m/s Airflow
40.4°C/W
1m/s Airflow
29.1°C/W
Storage Temperature
-65 to +150°C
1 The input and output negative voltage ratings may be exceeded if the ratings of the I/P and
O/P clamp current are observed.
2 This current will flow only when the output is in the high state level VO > VDDQ.
3 The package thermal impedance is calculated in accordance with JESD 51.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range
VDD = 1.8V ± 0.1V
Parameter
dV/dt_r
dV/dt_f
dV/dt_Δ
1
1
Min.
Max.
Units
1
4
V/ns
1
4
V/ns
1
V/ns
Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
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Terminal Functions
Terminal Name
Electrical
Characteristics
GND
Ground Input
Ground
VDD
1.8V nominal
Power Supply Voltage
VREF
0.9V nominal
Input Reference Clock
CLK
Differential Input
Positive Master Clock Input
CLK
Differential Input
Negative Master Clock Input
C
LVCMOS Input
Configuration Control Inputs - Register A or Register B
RESET
LVCMOS Input
Asynchronous Reset Input. Resets registers and disables Vref data
and clock differential-input receivers.
CSGEN
LVCMOS Input
Chip select gate enable – When high, D1-D28 inputs will be latched
only when at least one chip select input is low during the rising edge
of the clock. When low, the D1-D28 inputs will be latched and
redriven on every rising edge of the clock.
D1 - D28
SSTL_18 Input
Data Input. Clocked in on the crossing of the rising edge of CLK
and the falling edge of CLK.
DCS0, DCS1
SSTL_18 Input
Chip select inputs – These pins initiate DRAM address/command
decodes, and as such at least one will be low when a valid
address/command is present. The Register can be programmed to
redrive all D inputs (CSGEN high) only when at least one chip select
input is low. If CSGEN, DCS0, and DCS1 inputs are high, D1-D28
inputs will be disabled.
DCKE0, DCKE1
SSTL_18 Input
The outputs of this register bit will not be suspended by the DCS0
and DCS1 controls
DODT0, DODT1
SSTL_18 Input
The outputs of this register bit will not be suspended by the DCS0
and DCS1 controls
PAR_IN
SSTL_18 Input
Parity Input arrives one cycle after corresponding data input
Q1 - Q28
1.8V CMOS
Data Outputs that are suspended by the DCS0 and DCS1 controls
QCS0, QCS1
1.8V CMOS
Data Output that will not be suspended by the DCS0 and DCS1
controls
QCKE0, QCKE1
1.8V CMOS
Data Output that will not be suspended by the DCS0 and DCS1
controls
QODT0, QODT1
1.8V CMOS
Data Output that will not be suspended by the DCS0 and DCS1
controls
QERR
Open Drain Output
NC
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Description
Output Error bit, generated one cycle after the corresponding data
output
No Connection
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COMMERCIAL TEMPERATURE GRADE
Operating Characteristics, TA = 25°C
The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation.
The differential inputs must not be floating unless RESET is Low.
Symbol
Parameter
Min.
Typ.
Max.
Units
VDD
I/O Supply Voltage
1.7
1.8
1.9
V
VREF
Reference Voltage
0.49 * VDD
0.5 * VDD
0.51 * VDD
V
VTT
Termination Voltage
VREF - 0.04
VREF
VREF + 0.04
V
VDD
V
VI
Input Voltage
VIH
AC High-Level Input Voltage
VIL
AC Low-Level Input Voltage
VIH
DC High-Level Input Voltage
VIL
DC Low-Level Input Voltage
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
0
Data CSR
and
PAR_IN
inputs
RESET,
C0, C1
VREF + 0.25
VREF - 0.25
VREF + 0.125
VREF - 0.125
0.65 * VDDQ
0.35 * VDDQ
VICR
Common Mode Input Range
VID
Differential Input Voltage
IOH
High-Level Output Current
-6
IOL
Low-Level Output Current
6
TA
Operating Free-Air Temperature
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
CLK, CLK
0.675
1.125
600
0
12
V
V
V
mV
+70
ICSSSTUAF32868A
mA
°C
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28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
DC Electrical Characteristics Over Operating Range
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDDQ/VDD = 2.5V ± 0.2V.
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
IOH = -6mA, VDDQ = 1.7V
VOL
Output LOW Voltage
IOL = 6mA, VDDQ = 1.7V
All Inputs
VI = VDD or GND; VDD = 1.9V
Static Standby
IIL
IDD
IDDD
CI
Static Operating
Min.
Typ.
Max.
1.2
Units
V
0.5
V
+5
μA
IO = 0, VDD = 1.9V, RESET = GND
200
μA
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = CLK = VIH(AC)
or VIL(AC)
10
-5
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = VIH(AC), CLK =
VIL(AC)
mA
200
Dynamic Operating
(clock only)
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle
260
μA/Clock
MHz
Dynamic Operating
(per each data input)
1:2 mode
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle. One data
input switching at half clock frequency,
50% duty cycle.
75
μA/Clock
MHz/
Data
Data Inputs
VI = VREF ± 250mV
CLK and CLK
VICR = 0.9V, VIPP = 600mV
RESET
VI = VDD or GND
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
2
3.5
2.5
4
pF
5
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COMMERCIAL TEMPERATURE GRADE
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
VDD = 1.8V ± 0.1V
Symbol
fCLOCK
tW
t ACT
Clock Frequency
Pulse Duration, CLK, CLK HIGH or LOW
1,2
tINACT
Min.
Parameter
1,3
tSU
tH
Max.
Units
410
MHz
1
ns
Differential Inputs Active Time
10
ns
Differential Inputs Inactive Time
15
ns
Setup
Time
Hold
Time
DCS0 before CLK↑, CLK↓, DCS1 and CSGEN HIGH;
DCS1 before CLK↑, CLK↓, DCS0 and CSGEN HIGH;
0.7
ns
DCS0 before CLK↑, CLK↓, DCS1 LOW and CSGEN
HIGH or LOW; DCS1 before CLK↑, CLK↓, DCS0
LOW and CSGEN HIGH or LOW
0.5
ns
DODTn, DCKEn, PAR_IN, and data before CLK↑,
CLK↓
0.5
ns
DCSn, DODT,n DCKEn, and data after CLK↑, CLK↓
0.5
ns
PAR_IN after CLK↑, CLK↓
0.5
ns
1 This parameter is not production tested.
2 VREF must be held at a valid input voltage level and data inputs must be held at valid voltage levels for
a minimum time of tACT (max) after RESET is taken HIGH.
3 VREF data and clock inputs must be held at valid input voltage levels (not floating) for a minimum time
of tINACT (max) after RESET is taken LOW.
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
VDD = 1.8V ± 0.1V
Parameter
Min.
fMAX
Max Input Clock Frequency
410
tPDM
Propagation Delay, single bit switching, CLK↑ to CLK↓ to Qn
1.3
Symbol
tPDMSS
Propagation Delay, simultaneous switching, CLK↑ to CLK↓ to Qn
Max.
Units
MHz
1.9
ns
2
ns
tLH
LOW to HIGH Propagation Delay, CLK↑ to CLK↓ to QERR
1.2
3
ns
tHL
HIGH to LOW Propagation Delay, CLK↑ to CLK↓ to QERR
1
2.4
ns
tPLH
HIGH to LOW Propagation Delay, RESET↓ to Qn↓
3
ns
tPHL
LOW to HIGH Propagation Delay, RESET↓ to QERR↑
3
ns
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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COMMERCIAL TEMPERATURE GRADE
Register Timing
RESET
CSGEN
DCS0
DCS1
n
n +1
n+2
n+3
n+4
CLK
CLK
tACT
tH
tSU
Dn, DODTn,
DCKEn
tPDM, tPDMSS
CLK to Q
Qn, QODTn,
QCKEn
tSU
tH
PARIN
tPHL
CLK to QERR
tPHL, tPLH
CLK to QERR
Data to QERR Latency
QERR
H, L, or X
H or L
NOTES:
1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held LOW for a
minimum time of tACTMAX, to avoid false error.
2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and
it will be valid on the n+3 clock pulse.
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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COMMERCIAL TEMPERATURE GRADE
Register Timing
NOTE:
1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and
it will be valid on the n+3 clock pulse. If an error occurs and the QERR output is driven LOW, it stays latched LOW
for a minimum of two clock cycles or until RESET is driven LOW.
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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COMMERCIAL TEMPERATURE GRADE
Register Timing
RESET
tINACT
CSGEN
DCS0
DCS1
CLK
CLK
Dn, DODTn,
DCKEn
tRPHL
RESET to Q
Qn, QODTn,
QCKEn
PARIN
QERR
tRPLH
RESET to QERR
H, L, or X
H or L
NOTE:
1.After RESET is switched from LOW to HIGH, all data and clock inputs signals must be set and held at valid logic
levels (not floating) for a minimum time of tINACTMAX.
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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COMMERCIAL TEMPERATURE GRADE
Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
VDD/2
VDD
DUT
R L = 1KΩ
TL = 50Ω
CLK
CLK
CLK Inputs
ZO = 50Ω
Test
Point
ZO = 50Ω
Test
Point
CLK Inputs
Test Point
CL = 30 pF
Test
Point
CLK
TL = 350ps, 50Ω
Out
DUT
RL = 50Ω
ZO = 50Ω
Out
CLK
R L = 1KΩ
Test Point
RL = 100Ω
Test Point
Production-Test Load Circuit
Simulation Load Circuit
CLK
tPLH
VDD
LVCMOS
RESET
Input
VDD/2
V ICR
V ICR
CLK
V ID
tPHL
V OH
Output
VDD/2
V TT
V TT
V OL
0V
tACT
tINACT
Voltage Waveforms - Propagation Delay Times
90%
IDD
10%
LVCMOS
RESET
Input
Voltage and Current Waveforms Inputs Active and Inactive
Times
VIH
VDD/2
VIL
tRPHL
VOH
Output
VTT
VOL
tW
Input
VICR
VICR
Voltage Waveforms - Propagation Delay Times
VID
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and
Io = 0mA
3. All input pulses are supplied by generators having the following
characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns
±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per
measurement.
5. VTT = VREF = VDD/2
6. VIH = VREF + 250mV (AC voltage levels) for differential inputs.
VIH = VDD for LVCMOS input.
7. VIL = VREF - 250mV (AC voltage levels) for differential inputs.
VIL = GND for LVCMOS input.
8. VID = 600mV.
9. tPLH and tPHL are the same as tPDM.
Voltage Waveforms - Pulse Duration
CLK
VID
VICR
CLK
tSU
tH
VIH
Input
VREF
VREF
VIL
Voltage Waveforms - Setup and Hold Times
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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COMMERCIAL TEMPERATURE GRADE
Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
VDD
DUT
VDD
DUT
RL = 50Ω
Out
RL = 1KΩ
Out
Test Point
Test Point
CL = 10 pF
CL = 10 pF
Load Circuit: Error Output Measurements
Load Circuit: High-to-Low Slew-Rate Adjustment
Output
LVCMOS
RESET
Input
VOH
80%
VCC
VCC/2
0V
tPLH
VOH
20%
dv_f
0.15V
Output
Waveform 2
VOL
0V
dt_f
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to RESET input)
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
Timing
Inputs
DUT
VICR
VICR
VI(PP)
tHL
Out
Test Point
CL = 10 pF
VCC/2
VOL
Voltage Waveforms: Open Drain Output High-to-Low
Transition Time (with respect to clock inputs)
Load Circuit: Low-to-High Slew-Rate Adjustment
Timing
Inputs
dt_r
VOH
dv_r
VCC
Output
Waveform 1
RL = 50Ω
80%
VICR
VICR
VI(PP)
tHL
VOH
Output
Waveform 2
20%
Output
VOL
0.15V
0V
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to clock inputs)
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input
slew rate = 1 V/ns ±20% (unless otherwise specified).
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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COMMERCIAL TEMPERATURE GRADE
Package Outline and Package Dimensions - BGA
Package dimensions are kept current with JEDEC Publication No. 95
C
SEATING
PLANE
Numeric Designations
for Horizontal Grid
A1
b REF
T
4
3
2
1
A
B
C
D
Alpha Designations
for Vertical Grid
(Letters I, O, Q, and
S not used)
D
d TYP
D1
-e- TYP
TOP VIEW
E
c REF
-e- TYP
h TYP
E1
0.12 C
ALL DIMENSIONS IN MILLIMETERS
BALL GRID
d
T
Min/Max
e
D
E
Horiz Vert Total Min/Max
15.00 Bsc 6.00 Bsc 0.94/1.20 0.65 Bsc
8
22 176 0.35/0.45
h
Min/Max
0.25/0.35
REF. DIMS
D1
E1
b
c
13.65 Bsc 4.55 Bsc 0.675 0.725 ***
NOTE: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
* Source Ref.: JEDEC Publication 95, MO-205*, MO-255**, MO-246***
10-0055
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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COMMERCIAL TEMPERATURE GRADE
Ordering Information
ICSSSTUAF XX
Family
XX
XXX
Device Type Package
X
Shipping
Carrier
T
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Tape and Reel
HLF
Low Profile, Fine Pitch, Ball Grid Array - Lead-Free
868A
28-Bit Configurable Registered Buffer for DDR2
32
Double Density
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COMMERCIAL TEMPERATURE GRADE
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www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
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