ISL6801 ® Data Sheet July 25, 2005 High Voltage Bootstrap High Side Driver Features The ISL6801 is a single monolithic, inverting bootstrap driver. Its floating Level Shifter Section is optimized for the control of N-Channel Power MOSFETs in high side configurations with Bus Voltages up to 120VDC from a 5V Controller Output. It features two output stages pinned out separately to allow independent control of rise and fall times. To ensure static DC operation an integrated recharge path charges the bootstrap cap while the driver is switched off. A pull-up resistor forces the input low when no control signal is applied. The supply voltage is monitored to guarantee faultless operation at start-up. • Single Bootstrap High Side Driver Ordering Information • Supply Undervoltage Protection PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # ISL6801AB -40 to 125 8 Ld SOIC M8.15 ISL6801AB-T -40 to 125 8 Ld SOIC Tape and Reel M8.15 FN9087.2 • Bootstrap Supply Max Voltage. . . . . . . . . . . . . . . 120VDC • Peak Output Drive Current. . . . . . . . . . . . . . . . . . . 200mA • Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . 100kHz • Active Low Input • Separate Reset Input • Recharge Path for Static Operation • Separate High and Low Gate Drive Outputs Allow Independent Turn ON/OFF Time Control • Space Saving SO-8 Package • Wide Operating Temperature Range Applications • Driver for N-Channel MOSFETs in High Side Configurations that Control Ground Referenced Loads • Drives Solenoids, Motors, Relays and Lamps in Automotive Applications Pinout SL6801AB (SOIC) TOP VIEW 1 VCC 1 8 VB IN 2 7 HOH GND 3 6 HOL RES 4 5 VS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6801 Typical Application Block Diagram +150VDC MAX BOOTSTRAP SUPPLY VB VCC HOH CONTROLLER RES LEVEL SHIFTER INPUT LOGIC IN HOL VS RECHARGE PATH LOAD ISL6801 Functional Block Diagram VB VCC UV DETECT IN & & LEVEL SHIFTER OUTPUT RES HOH HOL ON DELAY OFF GND VS Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 VCC Driver Supply, Typical 5.0V 2 IN Driver Control Signal Input 3 GND Ground 4 RES Driver Enable Signal Input (‘RESET’) 5 VS 6 HOL MOSFET Gate Low Connection 7 HOH MOSFET Gate High Connection 8 VB MOSFET Source Connection Driver Output Stage Supply NOTE: The HOL and HOH are the low respective high gate drive output pins. The turn on and turn off time of the external MOSFET could be controlled by using different resistance values for high and low signal. 2 ISL6801 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V Driver Output Stage Voltage, VB (Referred to GND) . . . . . . . . .130V Source Reference Voltage, VS (-5V for 0.5ms, MOSFET Off). . . . . . . . . . . . . . . . . . . . (Min) -1.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (Max) 120V ESD Rating, VESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . (Min) 820V (Per MIL-STD-883 Method 3015.7) Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .245oC (SOIC Lead Tips Only) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC Supply Voltage Range (Max) . . . . . . . . . . . . . . . . . . . . 4.5V to 6.5V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications All values are over full temperature range. PARAMETER SYMBOL Operating Temperature Range TA Source Reference Voltage VS Supply Voltage (Note 2) TEST CONDITIONS -1.8V Continuous, VB/VOH must stay low, IN = 0V, RES = 5V, VCC = 4.5V and 6.5V, VB = 5V and 12V, (Load R = 50Ω, C = 6.8nF) TA = -40 to 125oC VCC Driver Output Supply VVB - VS VVB - GND Switching Frequency f Voltage Transconductance (Note 3) Ident. to VGS of MOSFET Device Functional Guaranteed by Design dVs/dt Peak Gate Drive Current IHOpeak Sink/Source Current VB = 5V and 16V, 100ns Continuous Gate Drive Current (Note 3) IHOcont Sink/Source Current Continuous MIN TYP MAX UNITS -40 - 125 oC -1.5 - 120 V 4.5 - 6.5 V 4.0 8.5 16.0 V 2.0 - - V 100 - - kHz - - 500 V/µs - 200 - mA 6.5 8 - mA Gate Drive Level LOW VHOL, VS IN at H, IHO = 1mA, VB-VS = 5V and 16V - - 0.3 V Gate Drive Level LOW VHOL, VS IN at H, IHO = 100mA - - 2.2 V Gate Drive Level HIGH VVB, HOH IN at L, IHO = 1mA, VB-VS = 5V and 16V - - 0.5 V Gate Drive Level HIGH VVB, HOH IN at L, IHO = 100mA - - 2.2 V at VCC = 5.0V, RES = 5V, Output Trigger Level: 3.5V ON at VB = 5V, 1.0V OFF at VB = 16V, Input 2.5V (Load R = 50Ω, C = 6.8nF) - 1.0 3.0 µs tdRES - HOH, L VB-VS = 5V and 16V, (Load R = 50Ω, C = 6.8nF) - 1.0 3.0 µs tHOH, L Fall/Rise VB-VS = 5V (Load R = 50Ω, C = 6.8nF) - 100 500 ns VB-VS = 16V - 200 500 ns VB-VS = 9.0V, C100 = 1µF, (Load R = 50Ω, C = 6.8nF) - 100 210 (Note 5) mV Total IN to Output Delay (Figure 1) Total RES to Output Delay (Figure 2) Output Rise/Fall Times VB Drop Voltage (Figure 4, Note 4) 3 tdIN-HOH, L VBDROP ISL6801 Electrical Specifications All values are over full temperature range. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VB Input Current (Note 6) IVB Static Current, VB-VS = 8.5V, VCC = 5V, IN = 0V, RES = 5V, (Load R = 50Ω, C = 6.8nF) 300 750 875 µA VB Input Current IVB Static Current, VB-VS = 8.5V, VCC = 5V, IN = 0V, RES = 0V, (Load R = 50Ω, C = 6.8nF) 100 550 700 µA - 1.2 2.5 mA Driver Supply Current IVCC at VCC = 4.5V and 6.5V (Load R = 50Ω, C = 6.8nF) Input Threshold LOW (Note 7) INLOW VCC = 4.5V and 6.5V 1.4 - - V Input Threshold HIGH (Note 7) INHIGH VCC = 4.5V and 6.5V - - 3.0 V Enable Threshold LOW (Note 7) RESLOW VCC = 4.5V and 6.5V 1.4 - - V Enable Threshold HIGH (Note 7) RESHIGH VCC = 4.5V and 6.5V - - 3.0 V RIN at VCC = 5.0V, RES = 5V, IN = 0V, VB = 12V 60 100 170 kΩ Input Impedance at RES RRES at VCC = 5.0V, RES = 5V, IN = 0V, VB = 12V 60 100 170 kΩ Logic Input Current at RES (Note 8) IRES at Logic LOW Response HIGH -0.1 - 1.0 mA Undervoltage Shutdown Threshold VUV VCC to GND, Incl. Hyst. - 3.5 - V 70 170 350 Ω Input Impedance at IN Recharge Resistance (Note 9) Rrecharge VB = VS = HOH = HOL = 7V, RES = 5V, IN = 5V, VCC = 4.5V and 6V Recharge Turn On Delay (Note 9) tRechargeON 7 10 15 µs Recharge Turn Off Delay tRechargeOFF - - 1.5 µs at a Constant Current of 1.0mA - - 0.8 V at a Constant Current of 10mA - - 3.5 V Recharge Path Voltage Drop Vdrop Recharge NOTES: 2. Shutdown between 3.5V and 4.5V. 3. Parametric limits are guaranteed by design, but not tested in production. 4. The drop voltage is caused by VB to VS current flow during switching. See Figure 3. 5. Assuming 3µs switching overlap, time delay use at testing 100µs. 6. External MOSFET ON or OFF. 7. Input and Enable thresholds tested at VCC = 4.5V and 6.5V, VB = 12V, VS = 0V, IN at 0V, Response RES at 5.0V. 8. The defined values are to be considered as a maximum allowed value. The input stage does not need to have sink or source capability. 9. The recharge path has to withstand transients in the 120V range for approximately 1µs while injector turn off, causing high power dissipation in the resistor. 4 ISL6801 Timing Diagrams IN RES 90% 90% VS HOH, L 10% OFF RECHARGE tHOH, Lrise tdIN-HOH, L tdIN-HOH, L 10% tHOH, Lfall ON tRechargeOFF tRechargeON FIGURE 1. INPUT/OUTPUT TIMING DIAGRAM IN RES HOH, L tdRES-HOH, L tdRES-HOH, L FIGURE 2. RESET TIMING DIAGRAM VB Drop Voltage Test Ig OFF 0A Ig IN 1 VCC VB 8 50R IN 2 IN RES HOH 7 50R 3 GND HOL 6 4 RES VS 5 1µ 7V VBDROP 6n8 ISL6801 VB-VS FIGURE 3. VB DROP VOLTAGE TEST CIRCUIT 5 BREAK BEFORE MAKE FIGURE 4. VB DROP VOLTAGE DIAGRAM ISL6801 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N INDEX AREA 0.25(0.010) M H 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- µα e A1 B C 0.25(0.010) M C A M B S NOTES: MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MAX A1 e 0.10(0.004) MIN α 8 0o 8 7 8o 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. Rev. 0 12/93 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6