INTERSIL ISL97678IRZ

ISL97678
Features
The ISL97678 is an 8-channel PWM dimming LED driver
for LCD backlight applications. The ISL97678 is capable
of driving up to 96 pieces of 3.4V/50mA LEDs but larger
numbers of LEDs is possible if the LED forward voltage
combined is less than 45V. The ISL97678 has 8 channels
of voltage controlled current sources with typical currents
matching to ±1%, which compensate for the
non-uniformity effect of forward voltages variance in the
LED strings. To minimize the voltage headroom and
power loss in the typical multi-string operation, the
ISL97678 features dynamic headroom control that
monitors the highest LED forward voltage string and uses
its feedback signal for output regulation.
• 8 Channels
The ISL97678 features PWM dimming up to 30kHz with
0.8%~100% duty cycle and maintains ±1% current
matching across all ranges. The PWM dimming frequency
can be adjusted between 100Hz and 30kHz. The boost
switching frequency can also be adjusted between
600kHz and 1.5MHz.
• Adjustable Switching Frequency
The ISL97678 features extensive protection functions
that include string open and short circuit detections, OVP,
and OTP.
• 4.75V ~ 26V Input
• 45V Maximum Output
• Drive Typically 96 LEDs (3.4V/50mA each)
• External PWM Input up to 25kHz Dimming
• Dimming range 0.8%~100% up to 30kHz
• Current Matching ±0.7%
• Protections
- String Open Circuit and Short Circuit Detections,
OVP, and OTP
• Adjustable Dimming Frequency
• 32 Ld (5mmx5mm) QFN Package
Applications
• Notebook Displays WLED or RGB LED Backlighting
• LCD Monitor LED Backlighting
ISL97678 is available in the 32 Leads QFN 5mmx5mm
and operate from -40°C to +85°C with input voltage
ranges from 4.75V to 26V.
November 5, 2009
FN6998.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
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ISL97678
8-Channel 45V 50mA LED Driver
ISL97678
Typical Application Circuit
L1
VIN* = 4.75V~26V
10uH/3A
Co
Ci
3x4.7uF
ISL97678
10uF
8x12 = 96 LEDs
Output 45V*, 50mA per string max
D1
LX1 20
1uF
1uF
16
VIN
18
VDC
10
VLOGIC
LX2 21
806kΩ
100pF
OVP
23
22kΩ
3.3nF
4
PWM
17
EN
14
COMP
13
RSET
11
FSW
12
FPWM
2
AGND
3
AGND
6
AGND
7
AGND
3.3nF
14.2kΩ
15kΩ
50kΩ
333kΩ
8
AGND
9
AGND
5
AGND
15
AGND
CH1
25
CH2
26
CH3
27
CH4
28
CH5
29
CH6
30
CH7
31
CH8
32
PGND
1
PGND
19
* Vin > = 12V for 45V/50mA
Applications
PGND 22
FIGURE 1. ISL97678 TYPICAL APPLICATION DIAGRAM
2
FN6998.1
November 5, 2009
ISL97678
Block Diagram
45V*, 50mA per string
96 (8x12) LEDs
VIN* = 4.75V~26V
10uH/3A
EN
VIN
VDC
VLOGIC
Analog Bias
REG1
O/P Short
Logic Bias
REG2
Boost SW
fsw
OSC &
RAMP
Comp
OVP
OVP
Fault
fSW
2x4.7uF/50V
LX
Σ=0
Imax
Logic
FET
Drivers
ILIMIT
PGND
pe
Open Ckt, Short Ckt
Detects
Fault Control
COMP
GM
AMP
VSET
AGND
CH8
+
-
1
REF
GEN
+
-
RSET
CH1
CH2
Highest VF
String Detect
Temp
Sensor
Fault
Control
REF_OVP
REF_VSC
2
+
-
* Vin >=12V for 45V/50mA apps
PWM
PWM
Dimming
Controller
fPWM
+
-
8
ISL97678
FIGURE 2. ISL97678 BLOCK DIAGRAM
Ordering Information
PART NUMBER
PART MARKING
ISL97678IRZ (Notes 1, 2)
ISL9767 8IRZ
PACKAGE
(Pb-free)
32 Ld 5x5 QFN
PKG.
DWG. #
L32.5x5B
NOTES:
1. Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97678. For more information on MSL please
see techbrief TB363.
3
FN6998.1
November 5, 2009
ISL97678
Pin Configuration
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
ISL97678
(32 LD 5X5 QFN)
TOP VIEW
32
31
30
29
28
27
26
25
PGND
1
24 NC
AGND
2
23 OVP
AGND
3
22 PGND
PWM
4
21 LX
EXPOSED THERMAL PAD
Pin Descriptions
7
18 VDC
AGND
8
17 EN
10
11
12
13
14
15
16
VIN
9
AGND
AGND
COMP
19 PGND
RSET
6
FPWM
AGND
FSW
20 LX
VLOGIC
5
AGND
AGND
(I = Input, O = Output, S = Supply)
PIN
NAME
TYPE
1, 19, 22
PGND
S
Power Ground
DESCRIPTION
2, 3, 5, 6, 7,
8, 9, 15
AGND
S
Analog Ground
4
PWM
I
PWM Brightness Control
10
VLOGIC
O
Internal 2.5V Logic Bias Regulator. Need Decoupling Capacitor for Regulation
11
FSW
I
When RFSW is 100kΩ, fSW is 500kHz.
When RFSW is 33kΩ, fSW is 1.5MHz
12
FPWM
I
When RFPWM is 333kΩ, FPWM is 200Hz.
When RFPWM is 3.3kΩ, FPWM is 20kHz.
13
RSET
I
Resistor Connection for Setting LED Current
14
COMP
O
Boost compensation
16
VIN
S
Main Power
17
EN
I
Enable
18
VDC
S
Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor for Regulation
20, 21
LX
O
Boost MOSFET Drain Terminal Switching Node
23
OVP
I
Overvoltage Protection Input as well as Output Voltage FB Monitoring
24
NC
I/O
25 ~ 32
CH1 ~ CH8
I
4
No Connect
LED Driver PWM Dimming Monitoring
FN6998.1
November 5, 2009
ISL97678
Absolute Maximum Ratings
Thermal Information
Voltage ratings are all with respect to AGND pin
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V
VDC, PWM . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
COMP, RSET, FPWM, FSW . . . . . . . . . . . . . . . . -0.3V to min
. . . . . . . . . . . . . . . . . . . . . . . . . . . . (VDC + 0.3V, 5.75V)
CH1 - CH8, LX, OVP . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Thermal Resistance (Typical)
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . -40°C to +85°C
θJA (°C/W)
32 Ld QFN (Notes 4, 5) . . . . . . . . . 31
Thermal Characterization (Typical, Note 6)
θJC (°C/W)
3
PSIJT (°C/W)
32 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . .
0.2
Maximum Continuous Junction Temperature . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C
Power Dissipation
TA < +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2W
TA < +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8W
TA < +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W
TA < +100°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with
this rating then the die junction temperature can be estimated more accurately than the θJC and θJC thermal resistance
ratings.
Electrical Specifications
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, /SHUT = 5V,
ISET = 36kΩ, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +85°C.
5.
PARAMETER
DESCRIPTION
CONDITION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
GENERAL
VIN
Backlight Supply Voltage
IVIN_SHDN
VIN Shutdown Current
VOUT
Output Voltage
VUVLO
Undervoltage Lockout Threshold
VUVLO_HYS
Undervoltage Lockout Hysteresis
4.75
/SHUT = 0
2.9
26
(Note 8)
V
5
µA
45
V
3.3
V
300
mV
LINEAR REGULATOR
VDC
5V Analog Bias Regulator
VIN > 6V
VDC_DROP
VDC LDO Dropout Voltage
IVDC
4.8
5
5.1
V
IVDC = 30mA
71
100
mV
Active Current
/SHUT = 5V, R = 33kΩ
10
VLOGIC
2.5V Logic Bias Regulator
VIN > 6V
VLOGIC_DROP
VLOGIC LDO Dropout Voltage
IVLOGIC = 30mA
2.3
mA
2.4
2.5
V
31
100
mV
BOOST SWITCHING REGULATOR
SS
Soft-Start
SWILimit
Boost FET Current Limit
rDS(ON)
Internal Boost Switch ON-Resistance
5
16
TA = +25°C to +85°C
3.0
ms
4.7
130
A
mΩ
FN6998.1
November 5, 2009
ISL97678
Electrical Specifications
PARAMETER
Eff_peak
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, /SHUT = 5V,
ISET = 36kΩ, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
DESCRIPTION
Peak Efficiency
CONDITION
MIN
(Note 7)
MAX
(Note 7)
UNIT
VIN = 24V, 96LEDs,
20mA each, L = 10µH
with DCR ≤100mΩ,
FSW = 600kHz,
TA = +25°C
92.4
%
VIN = 12V, 96 LEDs,
20mA each, L = 10µH
with DCR ≤100mΩ,
FSW = 600kHz,
TA = +25°C
91.5
%
VIN = 6V, 96 LEDs,
20mA each, L = 10µH
with DCR ≤100mΩ,
FSW = 600kHz,
TA = +25°C
81.6
%
VIN = 24V, 80 LEDs,
40mA each, L = 10µH
with DCR ≤100mΩ,
FSW=600kHz,
TA = +25°C
93.4
%
VIN = 12V, 80 LEDs,
40mA each, L = 10µH
with DCR ≤100mΩ,
FSW = 600kHz,
TA = +25°C
90.7
%
DMAX
Boost Maximum Duty Cycle
fSW = 500kHz
DMIN
Boost Minimum Duty Cycle
fSW = 500kHz
fSW
Boost Switching Frequency
Rfsw = 100kΩ
0.45
Rfsw = 33kΩ
1.35
ILX_leakage
TYP
90
%
10
%
0.5
0.55
MHz
1.5
1.65
MHz
10
µA
+1.1
%
Lx Leakage Current
VLX = 45V, /SHUT = 0V
IMATCH
Channel-to-Channel Current Matching
ILED = 20mA
-1.1
IACC
Absolute Current Accuracy
IRSET = 36kΩ,
TA = +25°C
-1.5
+1.5
%
-2
+2
%
REFERENCE
IRSET = 36kΩ,
TA = -40°C to +80°C
±0.7
FAULT DETECTION
VSC
Channel Short Circuit Threshold
Vtemp
Over-Temperature Threshold
Vtemp_acc
Over-Temperature Threshold Accuracy
VOVP
Overvoltage Limit on OVP Pin
3.3
1.18
4.6
V
150
°C
5
°C
1.22
1.24
V
0.8
V
5.5
V
DIGITAL INTERFACE
VIL
Logic Input Low Voltage
VIH
Logic Input High Voltage
1.5
CURRENT SOURCES
VHEADROOM
Dominant Channel Current Source
Headroom at CH Pin
6
ILED = 50mA
TA = +25°C
1.0
V
FN6998.1
November 5, 2009
ISL97678
Electrical Specifications
PARAMETER
All specifications below are characterized at TA = -40°C to +85°C; VIN = 12V, /SHUT = 5V,
ISET = 36kΩ, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
DESCRIPTION
CONDITION
VISET
Voltage at ISET Pin
ILEDmax
Maximum LED Current per Channel
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
1.18
1.21
1.24
V
LED config = 8P10S
with VF = 3.4V and
VIN = 11V
50
mA
PWM GENERATOR
FPWM
Generated PWM Frequency
RFPWM = 330kΩ
180
200
220
Hz
RFPWM = 3.3kΩ
18
20
22
kHz
100
%
1.24
V
20k
Hz
1.25
V
Dimming Range
PWM Dimming Duty Cycle Limits (Note 9)
fPWM ≤ 30kHz
0.4
VFSW
fSW Voltage
RFSW = 33kΩ
1.18
FPWMI
PWMI Input Frequency Range (Note 9)
VFPWM
VFPWM Voltage
1.21
200
RFPWM = 3.3kΩ
1.18
1.21
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
8. At maximum VIN of 26V, minimum VOUT is 28V. Minimum VOUT can be lower at lower VIN
9. Limits established by characterization and are not production tested.
Typical Performance Curves
100
100
50mA
8P11S
fSW = 600kHz
95
0°C
90
+85°C
85
EFFICIENCY (%)
EFFICIENCY (%)
95
-40°C
+25°C
80
0
5
10
15
20
25
30
VIN (V)
FIGURE 3. EFFICIENCY vs VIN vs TEMPERATURE AT
50mA
7
-40°C
0°C
90
+85°C
85
80
75
75
70
20mA
8P11S
fSW = 600kHz
70
+25°C
0
5
10
15
20
25
30
VIN (V)
FIGURE 4. EFFICIENCY vs VIN vs TEMPERATURE AT
20mA
FN6998.1
November 5, 2009
ISL97678
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
95
8P10S
93
12V/50mA
24V/50mA
0
10
20
30
ILED (mA)
40
89
88
87
12V
1.0
20mA - 8P12S
50mA - 8P11S
0.2
0.0
-0.2
-0.4
-0.6
12V/50mA
-0.8
1
2
3
4
5
CHANNEL
6
7
0.6
0°C
0.4
0.2
0.0
+25°C
-0.2
+85°C
-0.4
-0.6
-0.8
-1.0
8
FIGURE 7. CHANNEL-TO-CHANNEL CURRENT
MATCHING EXAMPLE
-40°C
0
5
10
15
VIN (V)
2.0
20mA - 8P12S
50mA - 8P11S
24V/50mA
1.0
0.8
5V/20mA
0.6
0.4
24V/20mA
0.2
0.0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
PWM DIMMING DUTY CYCLE (%)
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM
DIMMING DUTY CYCLE
8
CHANNEL VOLTAGE (V)
1.8
12V/50mA
20
25
30
FIGURE 8. CURRENT MATCHING vs VIN vs
TEMPERATURE
2.0
1.2
1.6k
50mA
8P11
0.8
12V/20mA
0.4
600
800
1k
1.2k
1.4k
SWITCHING FREQUENCY (Hz)
FIGURE 6. EFFICIENCY vs SWITCHING FREQUENCY
0.6
-1.0
ILED (mA)
90
84
400
50
CURRENT MATCHING (%)
CURRENT MATCHING (%)
0.8
1.4
24V
91
85
1.0
1.6
92
86
FIGURE 5. EFFICIENCY vs ILED
1.8
50mA
8P11S
94
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves (Continued)
12V/50mA
1.6
20mA - 8P12S
50mA - 8P11S
1.4
1.2
1.0
0.8
0.6
12V/20mA
0.4
HEADROOM CONTROL CHANNEL
0.2
0.0
1
2
3
4
5
CHANNEL
6
7
8
FIGURE 10. TYPICAL CHANNEL VOLTAGE EXAMPLE
FN6998.1
November 5, 2009
ISL97678
Typical Performance Curves (Continued)
1.00
1.0
50mA
8P11S
0.90
0.8
0.85
0.7
0.80
+85°C
0.75
0.70
0°C
0.65
0.4
0.1
10
15
VIN (V)
20
25
30
10
+25°C
0.3
0.2
FIGURE 11. VHEADROOM vs VIN vs TEMPERATURE AT
50mA
0.0
0
5
10
0°C
15
VIN (V)
20
25
30
FIGURE 12. VHEADROOM vs VIN vs TEMPERATURE AT
20mA
/SHUT = HIGH
PWM DUTY CYCLE = 0%
9
LX (20V/DIV)
8
IIN (mA)
0.5
0.55
5
+85°C
0.6
0.60
0.50
0
20mA
8P11S
0.9
+25°C
VHEADROOM (V)
VHEADROOM (V)
0.95
7
+85°C
6
VO (100mV/DIV)
5
4
-40°C
3
ILED (20mA/DIV)
2
1
0
0
5
10
15
VIN (V)
20
25
30
FIGURE 13. QUIESCENT CURRENT vs VIN vs
TEMPERATURE WITH /SHUT ENABLE
FIGURE 14. VOUT RIPPLE VOLTAGE
VO (20V/DIV)
VO (20V/DIV)
EN (5V/DIV)
EN (5V/DIV)
IIN (1A/DIV)
IIN (1A/DIV)
ILED (50mA/DIV)
FIGURE 15. IN-RUSH CURRENT and LED CURRENT AT
VIN = 12V
9
ILED (50mA/DIV)
FIGURE 16. IN-RUSH CURRENT AND LED CURRENT
AT VIN = 26V
FN6998.1
November 5, 2009
ISL97678
Typical Performance Curves (Continued)
VIN (10V/DIV)
VIN (10V/DIV)
IIN (500mA/DIV)
IIN (500mA/DIV)
ILED (50mA/DIV)
FIGURE 17. LINE REGULATION WITH VIN CHANGES
FROM 12V TO 26V DISABLE PROFILE
ILED (50mA/DIV)
FIGURE 18. LINE REGULATION WITH VIN CHANGES
FROM 26V TO 12V
VO (1V/DIV)
VO (1V/DIV)
ILED (20mA/DIV)
ILED (20mA/DIV)
FIGURE 19. LOAD REGULATION WITH ILED CHANGES
FROM 0.4% TO 100% PWM DIMMING
VO (1V/DIV)
FIGURE 20. LOAD REGULATION WITH ILED CHANGES
FROM 100% TO 0.4% PWM DIMMING
VO (500mV/DIV)
ILED (20mA/DIV)
ILED (20mA/DIV)
FIGURE 21. LOAD REGULATION WITH ILED CHANGES
FROM 0% TO 100% PWM DIMMING
10
FIGURE 22. LOAD REGULATION WITH ILED CHANGES
FROM 100% to 0% PWM DIMMING
FN6998.1
November 5, 2009
ISL97678
Typical Performance Curves (Continued)
VO (20V/DIV)
EN (5V/DIV)
IIN (1A/DIV)
ILED (50mA/DIV)
FIGURE 23. DISABLE PROFILE
Theory of Operation
.
PWM Boost Converter
The current mode PWM boost converter produces the
minimal voltage needed to enable the LED string with the
highest forward voltage drop to run at the programmed
current. The ISL97678 employs current mode control
boost architecture that has a fast current sense loop and
a slow voltage feedback loop. Such architecture achieves
a fast transient response that is essential for the
notebook backlight application where the power can be
several Li-ion cell batteries or instantly change to an
AC/DC adapter without rendering a noticeable visual
nuisance. The number of LEDs that can be driven by
ISL97678 depends on the type of LED chosen in the
application. The ISL97678 is capable of boosting up to
45V and drive 8 channels of LEDs at maximum of 45mA
per channel.
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the
current source circuit, as shown in Figure 24.
The LED peak current is set by translating the RSET
current to the output with a scaling factor of 707.9/RSET.
The source terminals of the current source MOSFETs are
designed to run at 500mV to optimize power loss versus
accuracy requirements. The sources of errors of the
channel-to-channel current matching come from the
op amps offset, internal layout, reference, and current
source resistors. These parameters are optimized for
current matching and absolute current accuracy.
However, the absolute accuracy is additionally
determined by the external RSET. A 0.1% tolerance
resistor is recommended.
11
+
-
+
REF
RSET
+
PWM DIMMING
FIGURE 24. SIMPLIFIED CURRENT SOURCE CIRCUIT
Dynamic Headroom Control
The ISL97678 features a proprietary Dynamic Headroom
Control circuit that detects the highest forward voltage
string or effectively the lowest voltage from any of the
CH pins. When this lowest IIN voltage is lower than the
short circuit threshold, VSC, such voltage will be used as
the feedback signal for the boost regulator. The boost
makes the output to the correct level such that the
lowest CH pin is at the target headroom voltage. Since all
LED strings are connected to the same output voltage,
the other CH pins will have a higher voltage, but the
regulated current source circuit on each channel will
ensure that each channel has the same programmed
current. The output voltage will regulate cycle-by-cycle
and is always referenced to the highest forward voltage
string in the architecture.
FN6998.1
November 5, 2009
ISL97678
OVP and VOUT Requirement
PWM Dimming Frequency Adjustment
The Overvoltage Protection (OVP) pin has a function of
setting the overvoltage trip level as well as limiting the
VOUT regulation range.
The dimming frequencies are set by an external
resistor at the FPWM pin as shown by Equation 3:
The ISL97678 OVP threshold is set by RUPPER and
RLOWER as shown in Equation 1:
V OUT_OVP = 1.21V × ( R UPPER + R LOWER ) ⁄ R LOWER
(EQ. 1)
VOUT can only regulate between 64% and 100% of the
VOUT_OVP such that:
Allowable VOUT = 64% to 100% of VOUT_OVP
7
6.66 ×10
f PWM = -----------------------RPWM
(EQ. 3)
where fPWM is the desirable PWM dimming frequency
and RFPWM is the setting resistor.
Switching Frequency
The boost switching frequency can be adjusted by a
resistor as shown in Equation 4:
10
For example, if 10 LEDs are used with the worst case
VOUT of 35V. If R1 and R2 are chosen such that the OVP
level is set at 40V, then the VOUT is allowed to operate
between 25.6V and 40V. If the requirement is changed to
a 6 LEDs 21V VOUT application, then the OVP level must
be reduced and users should follow VOUT = (64%
~100%)OVP requirement. Otherwise, the headroom
control will be disturbed such that the channel voltage
can be much higher than expected and sometimes it can
prevents the driver from operating properly.
The ratio of the OVP capacitors should be the inverse of
the OVP resistors. For example, if RUPPER/RLOWER=
33/1, then CUPPER/CLOWER=1/33 with CUPPER = 100pF
and CLOWER = 3.3nF.
( 5 ×10 )
f SW = ----------------------R OSC
(EQ. 4)
where fSW is the desirable boost switching frequency
and ROSC is the setting resistor.
5V and 2.3V Low Dropout Regulators
A 5V LDO regulator is present at the VDC pin to develop
the necessary low voltage supply, which is used by the
chips internal control circuitry. Because VDC is an LDO
pin, it requires a bypass capacitor of 1µF or more for the
regulation. The VDC pin can be used for a coarse
regulator or reference but do not pull more than few mA
from it.
1. DC current adjustment
Similarly, a 2.3V LDO regulator is present at the
VLOGIC pin to develop the necessary low voltage supply
for the chip’s internal logic control circuitry. A 1µF
bypass capacitor or more is needed for regulation. The
VLOGIC pin can be used as a coarse regulator or
reference but do not pull more than few mA from it.
2. PWM chopping of the LED current defined in Step 1.
Soft-Start
Dimming Controls
The ISL97678 allows two ways of controlling the LED
current, and therefore, the brightness. They are:
There are various ways to achieve DC or PWM current
control, which will be described in the following.
In any dimming controls, the EN pin must be high. EN
is a high voltage pin that can be applied with a digital
signal or tied directly to VIN for enable function.
MAXIMUM DC CURRENT SETTING
The initial brightness should be set by choosing an
appropriate value for RSET. This should be chosen to fix
the maximum possible LED current:
The ISL97678 uses a digital soft-start where the boost
current limit is stepped up in 8 steps. The initial current
limit level is set to one ninth of the full current limit, with
subsequent steps increasing this by a ninth every 2ms.
In the event that no LEDs have been conducting during
the interval since the last step (for example if the LEDs
are running at low duty cycle at low PWM frequency)
then the step will be delayed until the LEDs are
conducting. If the LEDs are disabled and re-enabled
again then soft start will be restarted when the LEDs are
enabled.
Fault Protection and Monitoring
707.9
I LEDmax = --------------R SET
(EQ. 2)
Alternatively, the RSET can be replaced by a digital
potentiometer for adjustable current.
PWM CONTROL
The ISL97678 provides PWM dimming by PWM chopping
of the current in the LEDs for all 8 channels. To achieve
PWM dimming, the users need to apply a PWM signal at
the PWM pin. The PWM output will follow the PWM input
and the dimming frequency will be set by RPWM. During
the On periods, the LED current will be defined by the
value of RSET, as described in Equation 1.
12
The ISL97678 features extensive protection functions to
cover all the perceivable failure conditions. The failure
mode of a LED can be either open circuit or as a short.
The behavior of an open circuited LED can additionally
take the form of either infinite resistance or, for some
LEDs, a zener diode, which is integrated into the device
in parallel with the now opened LED.
For basic LEDs (which do not have built-in zener diodes),
an open circuit failure of an LED will only result in the loss
of one channel of LEDs without affecting other channels.
Similarly, a short circuit condition on a channel that
FN6998.1
November 5, 2009
ISL97678
results in that channel being turned off does not affect
other channels unless a similar fault is occurring.
Due to the lag in boost response to any load change at its
output, certain transient events (such as significant step
changes in LED duty cycle) can transiently look like LED
fault modes. The ISL97678 uses feedback from the LEDs
to determine when it is in a stable operating region and
prevents apparent faults during these transient events
from allowing any of the LED strings to fault out. See
Table 1 for more details.
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each
channel and disables faulty channels which are detected
above the programmed short circuit threshold. When an LED
becomes shorted, the action taken is described in Table 1. The
short circuit threshold is 4V.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can
behave as either an infinite resistance or a gradually
increasing finite resistance. The ISL97678 monitors the
current in each channel such that any string which
reaches the intended output current is considered
“good”. Should the current subsequently fall below the
target, the channel will be considered an “open circuit”.
Furthermore, should the boost output of the ISL97678
reach the OVP limit or should the lower over-temperature
threshold be reached, all channels which are not “good”
will immediately be considered as “open circuit”.
Detection of an “open circuit” channel will result in a
time-out before disabling of the affected channel.
Some users employ some special types of LEDs that
have zener diode structure in parallel with the LED for
ESD enhancement, thus enabling open circuit operation.
When this type of LED goes open circuit, the effect is as
if the LED forward voltage has increased, but no light
will be emitted. Any affected string will not be disabled,
unless the failure results in the boost OVP limit being
reached, allowing all other LEDs in the string to remain
functional. Care should be taken in this case that the
boost OVP limit and SCP limit are set properly, so as to
make sure that multiple failures on one string do not
cause all other good channels to be faulted out. This is
due to the increased forward voltage of the faulty
channel making all other channel look as if they have
LED shorts. See Table 1 for details for responses to fault
conditions.
13
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage
and keeps the voltage at a safe level. The OVP threshold
is set as shown in Equation 5:
OVP = 1.21V × ( RUPPER + R LOWER ) ⁄ R LOWER
(EQ. 5)
These resistors should be large to minimize the power
loss. For example, a 1MkΩ RUPPER and 30kΩ RLOWER
sets OVP to 41.2V. Large OVP resistors also allow COUT
discharges slowly during the PWM Off time. Parallel
capacitors should be placed across the OVP resistors
such that RUPPER/RLOWER = CLOWER/CUPPER. Using a
CUPPER value of at least 30pF is recommended. These
capacitors reduce the AC impedance of the OVP node,
which is important when using high value resistors.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.8V, the
device will stop switching and be reset. Operation will
restart only if the device control interface re-enables it
once the input voltage is back in the normal operating
range. Also all digital settings will be reset to their default
states.
Over-Temperature Protection (OTP)
The ISL97678 includes two over-temperature thresholds.
The lower threshold is set to +130°C. When this
threshold is reached, any channel which is outputting
current at a level significantly below the regulation target
will be treated as “open circuit” and disabled after a
time-out period. The intention of the lower threshold is to
allow bad channels to be isolated and disabled before
they cause enough power dissipation (as a result of other
channels having large voltages across them) to hit the
upper temperature threshold.
The upper threshold is set to +150°C. Each time this is
reached, the boost will stop switching and the output
current sources will be switched off and stay off until the
control driver is power off and and re-enables it. Also
unless disabled via the /SHUT pin, the device stays in an
active state throughout.
For the extensive fault protection conditions, please refer
to Figure 25 and Table 1 for details.
Shutdown
When the EN pin is low the entire chip is shut down to
give close to zero shutdown current. The digital
interfaces will not be active during this time.
FN6998.1
November 5, 2009
ISL97678
VIN
VOUT
LX
FAULT
O/P
SHORT
DRIVER
IMAX
ILIMIT
OVP
FET
DRIVER
LOGIC
CH1
VSC
CH8
VSET/2
REG
THRM
SHDN
REF
OTP
T2
TEMP
SENSOR
T1
VSET
+
Q1 VSET
CONTROL
LOGIC
Q8
-
PWM1/OC1/SC1
+
PWM8/OC8/SC8
DC CURRENT
FIGURE 25. SIMPLIFIED FAULT PROTECTIONS
TABLE 1. PROTECTIONS TABLE
DETECTION MODE
CASE
FAILURE MODE
1
CH1 Short Circuit
Upper
CH1 ON and burns power
Over-Temperature
Protection limit (OTP)
not triggered and
VIIN0 < VSC
CH2 through CH8 Normal
Highest VF of
CH2 through
CH8
2
CH1 Short Circuit
Upper OTP triggered
but VIN1 < VSC
CH1 goes off
Same as CH1
Highest VF of
CH2 through
CH8
3
CH1 Short Circuit
Upper OTP not
triggered but VIIN1 >
VSC
CH1 disabled after 6 PWM
cycles time-out.
Highest VF of
If 3 channels are already
shut down, all channels will CH2 through
CH8
be shut down. Otherwise
CH2-8 will remain as normal
4
CH1 Open Circuit
with infinite
resistance
Upper OTP not
triggered and VIIN1
< VSC
VOUT will ramp to OVP. CH1 will CH2 through CH8 Normal
time-out after 6 PWM cycles
and switch off. VOUT will drop
to normal level.
5
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP not
CH1 remains ON and has
triggered and VIIN1 < highest VF, thus VOUT
VSC
increases
CH2 through CH8 ON, Q2
through Q8 burn power
VF of CH1
6
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP triggered
but VIIN1 < VSC
Same as CH1
VF of CH1
14
FAILED CHANNEL ACTION
CH1 goes off
GOOD CHANNELS ACTION
VOUT
REGULATED
BY
Highest VF of
CH2 through
CH8
FN6998.1
November 5, 2009
ISL97678
TABLE 1. PROTECTIONS TABLE (Continued)
CASE
7
FAILURE MODE
CH1 LED Open
Circuit but has
paralleled Zener
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION
VOUT
REGULATED
BY
CH1 OFF
Upper OTP not
triggered but VIIN1 >
VSC
CH2 through CH8 Normal
Highest VF of
CH2 through
CH8
CH1 remains ON and has
Upper OTP not
triggered but VIINx > highest VF, thus VOUT
VSC
increases.
VOUT increases then CH-X
switches OFF. This is an
unwanted shut off and can
be prevented by setting OVP
and/or VSC at an
appropriate level.
VF of CH1
8
Channel-toChannel ΔVF too
high
Lower OTP triggered
but VIINx < VSC
Any channel at below the target current will fault out after
6 PWM cycles.
Remaining channels driven with normal current.
Highest VF of
CH1 through
CH8
9
Channel-toChannel ΔVF too
high
Upper OTP triggered
but VIINx < VSC
All channels switched off
Highest VF of
CH1 through
CH8
10
Output LED string
voltage too high
VOUT > VOVP
Driven with normal current. Any channel that is below the
target current will time-out after 6 PWM cycles.
Highest VF of
CH1 through
CH8
11
VOUT/LX shorted
to GND
LX will not switch
15
FN6998.1
November 5, 2009
ISL97678
Components Selections
According to the inductor Voltage-Second Balance
principle, the change of inductor current during the
switching regulator On-time is equal to the change of
inductor current during the switching regulator Off-time.
Since the voltage across an inductor is as shown in
Equation 6:
(EQ. 6)
V L = L × ΔI L ⁄ Δt
and ΔIL @ On = ΔIL @ Off, therefore:
( V I – 0 ) ⁄ L × D × tS = ( VO – VD – VI ) ⁄ L × ( 1 – D ) × tS
(EQ. 7)
where D is the switching duty cycle defined by the
turn-on time over the switching periods. VD is Schottky
diode forward voltage that can be neglected for
approximation.
Rearranging the terms without accounting for VD gives
the boost ratio and duty cycle respectively as Equations 8
and 9:
VO ⁄ VI = 1 ⁄ ( 1 – D )
(EQ. 8)
D = ( VO – VI ) ⁄ VO
(EQ. 9)
Input Capacitor
Switching regulators require input capacitors to deliver
peak charging current and to reduce the impedance of
the input supply. This reduces interaction between the
regulator and input supply, thereby improving system
stability. The high switching frequency of the loop causes
almost all ripple current to flow in the input capacitor,
which must be rated accordingly.
A capacitor with low internal series resistance should be
chosen to minimize heating effects and improve system
efficiency, such as X5R or X7R ceramic capacitors, which
16
offer small size and a lower value of temperature and
voltage coefficient compared to other ceramic capacitors.
It is recommended that an input capacitor of at least
10µF be used. Ensure the voltage rating of the input
capacitor is suitable to handle the full supply range.
Inductor
The selection of the inductor should be based on its
maximum and saturation current (ISAT) characteristics,
power dissipation (DCR), EMI susceptibility (shielded vs
unshielded), and size. Inductor type and value influence
many key parameters, including ripple current, current
limit, efficiency, transient performance and stability.
The inductor’s maximum current capability must be
adequate enough to handle the peak current at the worst
case condition. Additionally, if an inductor core is chosen
with too low a current rating, saturation in the core will
cause the effective inductor value to fall, leading to an
increase in peak to average current level, poor efficiency
and overheating in the core. The series resistance, DCR,
within the inductor causes conduction loss and heat
dissipation. A shielded inductor is usually more suitable
for EMI susceptible applications, such as LED
backlighting.
The peak current can be derived from the voltage across
the inductor during the Off-period, as expressed in
Equation 10:
IL peak = ( V O × I O ) ⁄ ( 85% × V I ) + 1 ⁄ 2 [ V I × ( V O – V I ) ⁄ ( L × V O × f SW )
(EQ. 10)
The choice of 85% is just an average term for the
efficiency approximation. The first term is the average
current, which is inversely proportional to the input
voltage. The second term is the inductor current change,
which is inversely proportional to L and fSW. As a result,
for a given switching.
FN6998.1
November 5, 2009
ISL97678
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
11/5/09
FN6998.1
Changed VSC spec from Changed VSC spec from “3.3min, 4.4max” to “3.3min, 4.6max”.
10/26/09
FN6998.0
Initial Release
Products
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17
FN6998.1
November 5, 2009
ISL97678
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 11/07
4X 3.5
5.00
28X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
32
25
1
5.00
24
3 .30 ± 0 . 15
17
(4X)
8
0.15
9
16
TOP VIEW
0.10 M C A B
+ 0.07
32X 0.40 ± 0.10
4 32X 0.23 - 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
(
( 28X 0 . 5 )
SIDE VIEW
3. 30 )
(32X 0 . 23 )
C
0 . 2 REF
5
( 32X 0 . 60)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
18
FN6998.1
November 5, 2009