TECHNICAL DATA IN74LV273 Octal D Flip-Flop with Common Clock and Reset The IN74LV273 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT273. The IN74LV273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flipflop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Supply voltage range: 1.2 to 5.5 V • Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ • High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC DIP 20 1 DW SUFFIX SO 20 1 ORDERING INFORMATION IN74LV273N IN74LV273DW IZ74LV273 Plastic DIP SOIC chip TA = -40° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM RESET 1 20 V CC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 10 11 CLOCK GND FUNCTION TABLE Inputs PIN 20=VCC PIN 10 = GND Output Reset Clock D Q L X X L H H H H L L X no change X no change H L H H= high level L = low level X = don’t care Z = high impedance INTEGRAL 1 IN74LV273 MAXIMUM RATINGS * Symbol VCC IIK * Value Unit DC supply voltage -0.5 to +7.0 V 1 Input diode current ±20 mA 2 Output diode current ±50 mA Output source or sink current ±25 mA VCC current ±50 mA GND current ±50 mA Power dissipation per package: Plastic DIP * 4 SO * 4 750 500 IOK * IO * Parameter 3 ICC IGND PD Tstg mW Storage Temperature TL -65 to +150 °C 260 °C Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 VI < -0.5 V or VI > VCC + 0.5 V. * 2 VO < -0.5 V or VO > VCC + 0.5 V. * 3 -0.5 V < VO < VCC + 0.5 V. * 4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 1.2 5.5 V VCC DC Supply Voltage VI DC Input Voltage 0 VCC V VO DC Output Voltage 0 VCC V TA Operating Temperature, All Package Types -40 +125 °C tr, t f Input Rise and Fall Time (Figure 1) 0 0 0 0 500 200 100 50 ns 0 V ≤ VCC ≤ 2.0 V 2.0 V ≤ VCC ≤ 2.7 V 2.7 V ≤ VCC ≤ 3.6 V 3.6 V ≤ VCC ≤ 5.5 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV273 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test VCC conditions V Guaranteed Limit 25°C -40°C 85°C 125°C min max min max min max min max Unit VIH HIGH level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - V VIL LOW level output voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 V VOH HIGH level VI = VIH or VIL output IO = -100 µÀ voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.05 1.85 2.55 2.85 3.45 4.35 5.35 - 1.05 1.85 2.55 2.85 3.45 4.35 5.35 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - V VI = VIH or VIL IO = -6 mÀ 3.0 2.48 - 2.48 - 2.40 - 2.20 - V VI = VIH or VIL IO = -12 mÀ 4.5 3.70 - 3.70 - 3.60 - 3.50 - V LOW level VI = VIH or VIL output IO = 100 µÀ voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 V VI = VIH or VIL IO = 6 mÀ 3.0 - 0.33 - 0.33 - 0.40 - 0.50 V VI = VIH or VIL IO = 12 mÀ 4.5 - 0.40 - 0.40 - 0.55 - 0.65 V VOL II Input current VI = VCC or 0 V 5.5 - ±0.1 - ±0.1 - ±1.0 - ±1.0 µÀ ICC Supply current VI =VCC or 0 V IO = 0 µÀ 5.5 - 8.0 - 8.0 - 80 - 160 µÀ ICC1 Additional VI = VCC – 0.6V supply current per input 2.7 3.6 - 0.2 - 0.2 - 0.5 0.85 mA INTEGRAL 3 IN74LV273 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t r=tf=2.5 ns) Symbol Parameter tPHL, tPLH Propagation delay , Clock to Q tPHL Propagation delay , Reset to Q CI Test VCC conditions V Power dissipation capacitance (per flip-flop) -40°C to 25°C 85°C 125°C min max min max min max Unit VI = 0 V or V1 Figures 1,4 1.2 2.0 2.7 3.0 4.5 - 150 30 22 17 14 - 150 32 24 19 16 - 150 41 30 24 20 ns VI = 0 V or V1 Figures 2,4 1.2 2.0 2.7 3.0 4.5 - 160 40 30 23 19 - 160 44 33 26 22 - 160 56 41 33 28 ns 5.0 - 6.0* - - - - pF 5.5 - 40* - - - - pF Input capacitance CPD Guaranteed Limit VI = 0 V or VCC * T = 25oC TIMING REQUIREMENTS (CL=50 pF, t r=t f=2.5 ns) Symbol Parameter Test VCC conditions V Guaranteed Limit -40°C to 25°C 85°C 125°C min max min max min max Unit tw Pulse Width, Clock (low or VI = 0 V or V1 high), Reset (low) Figures 1,2,4 1.2 2.0 2.7 3.0 4.5 60 28 21 16 12 - 70 34 25 20 16 - 80 41 30 24 20 - ns tsu Setup Time, Data to Clock VI = 0 V or V1 Figures 3,4 1.2 2.0 2.7 3.0 4.5 40 18 13 11 9 - 50 22 16 13 11 - 60 26 19 15 13 - ns trem Removal Time, Reset to Clock VI = 0 V or V1 Figures 2,4 1.2 2.0 2.7 3.0 4.5 5 5 5 5 5 - 5 5 5 5 5 - 5 5 5 5 5 - ns th Hold Time, Clock to Data VI = 0 V or V1 Figures 3,4 1.2 2.0 2.7 3.0 4.5 50 5 5 5 5 - 50 5 5 5 5 - 50 5 5 5 5 - ns INTEGRAL 4 IN74LV273 fc Clock Frequency VI = 0 V or V1 Figures 1,4 1.2 2.0 2.7 3.0 4.5 - 2 17 23 30 32 - 1 14 19 24 27 - 1 12 16 20 24 MHz VOL and VOH are the typical output voltage drop that occur with the output load. Figure 1. Switching Waveforms Figure 2. Switching Waveforms INTEGRAL 5 IN74LV273 Figure 3. Switching Waveforms Level of a signal, V Symbol VCC 1,2 2,0 2,7 3,0 4,5 V1 1,2 2,0 2,7 2,7 4,5 VM 0,6 1,0 1,5 1,5 2,25 TEST POINT DEVICE UNDER TEST OUTPUT * CL * Includes all probe and jig capacitance Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM INTEGRAL 6 IN74LV273 CHIP PAD DIAGRAM 17 18 16 15 14 1.53 + 0.03 19 13 12 20 11 01 10 Chip marking 25LV273 02 03 09 04 05 06 07 08 Y (0,0) 1.48 + 0.03 X Location of marking (mm): left lower corner x=0.119, y=0.082. Chip thickness: 0.46 ± 0.02 mm, (0.35 ± 0.02 mm – for SOIC). PAD LOCATION Pad No Symbol 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Reset Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND Clock Q4 D4 D5 Q5 Q6 D6 D7 Q7 VCC Location (left lower corner), mm X 0.1415 0.1415 0.1375 0.4535 0.6245 0.7800 0.9520 1.2685 1.2480 1.2650 1.2650 1.2425 1.2465 0.9520 0.7800 0.6245 0.4535 0.1160 0.1440 0.1190 Y 0.6270 0.3880 0.1515 0.1190 0.1190 0.1190 0.1180 0.1185 0.2960 0.5160 0.8430 1.0820 1.3165 1.3120 1.3110 1.3110 1.3110 1.3115 1.1350 0.9140 Pad size, mm 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 Note: Pad location is given as per passivation layer. INTEGRAL 7