PRELIMINARY CMOS SRAM KM62256C Family 32Kx8 bit Low Power CMOS Static RAM FEATURES ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü GENERAL DESCRIPTION Process Technology : 0.7§- CMOS Organization : 32Kx8 Power Supply Voltage : Single 5V ¡¾ 10% Low Data Retention Voltage : 2V(Min) Three state output and TTL Compatible Package Type : JEDEC Standard 28-DIP, 28-SOP, 28-TSOP I -Forward/Reverse The KM62256C family is fabricated by SAMSUNG's advanced CMOS process technology. The family can support various operating temperature ranges and has various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family KM62256CL Operating Temperature. Speed (ns) Commercial (0~70¡É) 45*/55/70ns PKG Type KM62256CL-L KM62256CLE KM62256CLI 28-DIP, 28-SOP 28-TSOP I R/F 100§Ë 100§Ë 100§Ë Extended (-25~85¡É) 70/100ns 28-SOP 28-TSOP I R/F Industrial (-40~85¡É) 70/100ns 28-SOP 28-TSOP I R/F KM62256CLE-L KM62256CLI-L Standby (ISB1, Max) Operating (Icc2) 20§Ë 70mA 50§Ë 50§Ë * The parameter is measured with 30pF test load. PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM A0~A2, A9~11 A12 1 28 2 VCC 27 WE 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 A3 7 A2 8 A1 9 A0 10 I/O1 11 23 28-DIP 28-SOP A11 22 OE 21 A10 20 CS 19 18 I/O8 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 VSS 14 15 I/O4 28 A10 A11 2 27 CS A9 3 26 I/O8 A8 4 25 I/O7 A13 5 24 I/O6 WE 6 23 I/O5 VCC 7 22 I/O4 A14 8 21 VSS A12 9 20 I/O3 A7 10 19 I/O2 A6 11 18 I/O1 A5 12 17 A0 A4 13 16 A1 A3 14 15 A2 28-TSOP Type I - Forward A3~A8, A12~14 I/O1~8 A3 14 15 A2 A4 13 16 A1 A5 12 17 A0 A6 11 18 I/O1 A7 10 19 I/O2 A12 9 20 I/O3 A14 8 21 VSS 28-TSOP Type I - Reverse VCC 7 22 I/O4 WE 6 23 I/O5 A13 5 24 I/O6 A8 4 25 I/O7 A9 3 26 I/O8 A11 2 27 CS OE 1 28 A10 NameName Y-Decoder Cell Array I/O Buffer Control Logic A7 1 X-Decoder A14 OE CS WE,OE Function A0~A14 Address Inputs WE Write Enable Input CS Chip Select Input OE Output Enable Input I/O1~I/O8 Data Inputs/Outputs Vcc Power(5V) Vss Ground Revision 3.0 April 1996 PRELIMINARY CMOS SRAM KM62256C Family PRODUCT LIST & ORDERING INFORMATION PRODUCT LIST Commercial Temp Product (0~70¡É) Part Name Function Extended Temp Products (-25~85¡É) Part Name Function Industrial Temp Products (-40~85¡É) Part Name Function KM62256CLP-4 28-DIP, 45ns, L-pwr KM62256CLGE-7 28-SOP, 70ns, L-pwr KM62256CLGI-7 KM62256CLP-4L 28-DIP, 45ns, LL-pwr KM62256CLGE-7L 28-SOP, 70ns, LL-pwr KM62256CLGI-7L 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr KM62256CLP-5 28-DIP, 55ns, L-pwr KM62256CLGE-10 28-SOP, 100ns, L-pwr KM62256CLGI-10 28-SOP, 100ns, L-pwr KM62256CLP-5L 28-DIP, 55ns, LL-pwr KM62256CLGE-10L 28-SOP, 100ns, LL-pwr KM62256CLGI-10L 28-SOP, 100ns, LL-pwr KM62256CLP-7 28-DIP, 70ns, L-pwr KM62256CLTGE-7 28-TSOP F, 70ns, L-pwr KM62256CLTGI-7 28-TSOP F, 70ns, L-pwr KM62256CLP-7L 28-DIP, 70ns, LL-pwr KM62256CLTGE-7L 28-TSOP F, 70ns, LL-pwr KM62256CLTGI-7L 28-TSOP F, 70ns, LL-pwr KM62256CLG-4 28-SOP, 45ns, L-pwr KM62256CLTGE-10 28-TSOP F, 100ns, L-pwr KM62256CLTGI-10 28-TSOP F, 100ns, L-pwr KM62256CLG-4L 28-SOP, 45ns, LL-pwr KM62256CLTGE-10L 28-TSOP F, 100ns, LL-pwr KM62256CLTGI-10L KM62256CLG-5 28-SOP, 50ns, L-pwr KM62256CLRGE-7 28-TSOP R, 70ns, L-pwr KM62256CLRGI-7 28-TSOP F, 100ns, LL-pwr 28-TSOP R, 70ns, L-pwr KM62256CLG-5L 28-SOP, 50ns, LL-pwr KM62256CLRGE-7L 28-TSOP R, 70ns, LL-pwr KM62256CLRGI-7L 28-TSOP R, 70ns, LL-pwr KM62256CLG-7 28-SOP, 70ns, L-pwr KM62256CLRGE-10 28-TSOP R, 100ns, L-pwr KM62256CLRGI-10 28-TSOP R, 100ns, L-pwr KM62256CLG-7L 28-SOP, 70ns, LL-pwr KM62256CLRGE-10L 28-TSOP R, 100ns, LL-pwr KM62256CLRGI-10L KM62256CLTG-4 28-TSOP F, 45ns, L-pwr 28-TSOP R, 100ns, LL-pwr KM62256CLTG-4L 28-TSOP F, 45ns, LL-pwr KM62256CLTG-5 28-TSOP F, 55ns, L-pwr KM62256CLTG-5L 28-TSOP F, 55ns, LL-pwr KM62256CLTG-7 28-TSOP F, 70ns, L-pwr KM62256CLTG-7L 28-TSOP F, 70ns, LL-pwr KM62256CLRG-4 28-TSOP R, 45ns, L-pwr KM62256CLRG-4L 28-TSOP R, 45ns, LL-pwr KM62256CLRG-5 28-TSOP R, 55ns, L-pwr KM62256CLRG-5L 28-TSOP R, 55ns, LL-pwr KM62256CLRG-7 28-TSOP R, 70ns, L-pwr KM62256CLRG-7L 28-TSOP R, 70ns, LL-pwr ORDERING INFORMATION KM6 2 X 256 C X X X - XX X L-Low Low Power, Blank-Low Power or High Power Access Time : 4=45ns, 5=55ns, 7=70ns, 10=100ns Operating temperature : Blank=Commercial, I=Industrial, E=Extended Package Type : G=SOP, P=DIP, TG=TSOP Forward, RG=TSOP Reverse L-Low Power or Low Low Power, Blank-High Power Die Version : C=4th generation Density : 256=256K bit Blank=5V, V=3.0~3.6V, U=2.7~3.3V Organization : 2=x8 SEC Standard SRAM Revision 3.0 April 1996 PRELIMINARY CMOS SRAM KM62256C Family ABSOLUTE MAXIMUM RATINGS* Item Symbol Ratings Unit Remark VIN,VOUT -0.5 to VCC+0.5 V - Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V - Power Dissipation PD 1.0 W - TSTG -65 to 150 ¡É - TA 0 to 70 ¡É KM62256CL/L-L -25 to 85 ¡É KM62256CLE/LE-L -40 to 85 ¡É KM62256CLI/LI-L 260¡É, 10sec (Lead Only) - Voltage on any pin relative to Vss Storage temperature Operating Temperature Soldering temperature and time TSOLDER - * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not impl ied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS* Item Symbol Min Typ** Max Unit Supply voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.5V V Input low voltage VIL -0.5*** - 0.8 V * 1) Commercial Product : TA=0 to 70¡É, unless otherwise specified 2) Extended Product : TA=-25 to 85¡É, unless otherwise specified 3) Industrial Product : TA=-40 to 85¡É, unless otherwise specified ** TA=25¡É *** VIL(min)=-3.0V for ¡Â 50ns pulse width CAPACITANCE* (f=1MHz, T A=25¡É) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 6 pF Input/Output capacitance CIO VIO=0V - 8 pF * Capacitance is sampled not 100% tested Revision 3.0 April 1996 PRELIMINARY CMOS SRAM KM62256C Family DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions* Min Typ** Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 §Ë Output leakage current ILO CS=VIH or WE=VIL VIO=Vss to Vcc -1 - 1 §Ë Operating power supply current ICC CS=VIL, VIN=VIH or VIL, IIO=0mA - 7 15*** mA ICC1 Cycle time=1§Á 100% duty CS¡Â 0.2V, VIL¡Â 0.2V VIN ¡ÃVcc -0.2V, IIO=0mA - - 7**** mA ICC2 Min cycle, 100% duty CS=VIL, IIO=0mA - - 70 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS=VIH - - 1***** mA L(Low Power) LL(L Low Power) - 2 1 100 20 §Ë §Ë L(Low Power) LL(L Low Power) - - 100 50 §Ë §Ë L(Low Power) LL(L Low Power) - - 100 50 §Ë §Ë Average operating current KM62256CL KM62256CL-L Standby Current (CMOS) KM62256CLE KM62256CLE-L ISB1 CS ¡ÃVcc-0.2V VIN¡Ã 0.2V or VIN ¡ÂVCC-0.2V KM62256CLI KM62256CLI-L * 1) Commercial Product : TA=0 to 70¡É, Vcc=5V¡¾10% unless otherwise specified 2) Extended Product : TA=-25 to 85¡É, Vcc=5V¡¾10% nless otherwise specified 3) Industrial Product : TA=-40 to 85¡É, Vcc=5V¡¾10% unless otherwise specified ** TA=25¡É *** 20mA for Extended and Industrial Products ****10mA for Extended and Industrial Products *****2mA for Extended and Industrial Products A.C CHARACTERISTICS TEST CONDITIONS(1.Test Load and Test Input/Output Reference)* Item Value Remark 0.8 to 2.4V - Input rising & falling time 5ns - input and output reference voltage 1.5V - CL=100pF+1TTL - **CL=30pF+1TTL - Input pulse level Output load (See right) * See DC Operating conditions ** Test load for 45ns commercial products CL* * Including scope and jig capacitance Revision 3.0 April 1996 PRELIMINARY CMOS SRAM KM62256C Family TEST CONDITIONS(2. Temperature and Vcc Conditions) Product Family Temperature Power Supply(Vcc) Speed Bin Comments KM62256CL/L-L 0~70¡É 5V ¡¾ 10% 45*/55/70ns Commercial KM62256CLE/LE-L -25~85¡É 5V ¡¾ 10% 70/100ns Extended KM62256CLI/LI-L -40~85¡É 5V ¡¾ 10% 70/100ns Industrial * The parameter is measured with 30pF test load PARAMETER LIST FOR EACH SPEED BIN Speed Bins Parameter List Read 45ns* 55ns 70ns Units 100ns Min Max Min Max Min Max Min Max Read cycle time tRC 45 - 55 - 70 - 100 - ns Address access time tAA - 45 - 55 - 70 - 100 ns Chip select to output tCO - 45 - 55 - 70 - 100 ns Output enable to valid output tOE - 25 - 25 - 35 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 20 0 30 0 35 ns tOHZ 0 20 0 20 0 30 0 35 ns Output hold from address change tOH 5 - 5 - 5 - 5 - ns Write cycle time tWC 45 - 55 - 70 - 100 - ns Chip select to end of write tCW 45 - 45 - 60 - 80 - ns Address set-up time tAS 0 - 0 - 0 - 0 - ns Address valid to end of write tAW 45 - 45 - 60 - 80 - ns Write pulse width tWP 40 - 40 - 50 - 60 - ns Write recovery time tWR 0 - 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 20 0 25 0 35 ns Data to write time overlap tDW 25 - 25 - 30 - 50 - ns Data hold from write time tDH 0 - 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - 5 - ns Output disable to high-Z output Write Symbol * The parameter is measured with 30pF test load Revision 3.0 April 1996 PRELIMINARY CMOS SRAM KM62256C Family DATA RETENTION CHARACTERISTICS Item Symbol Vcc for data retention Test Condition* VDR KM62256CLE KM62256CLE-L IDR Vcc=3.0V CS¡ÃVcc-0.2V KM62256CLI KM62256CLI-L Data retention set-up time tSDR Recovery time tRDR Typ** Max Unit 2.0 - 5.5 V L-Ver LL-Ver - 1 0.5 50 10 L-Ver LL-Ver - - 50 25 L-Ver LL-Ver - - 50 25 0 - - 5 - - CS¡ÃVcc-0.2V KM62256CL KM62256CL-L Data retention current Min See data retention waveform §Ë ms * 1) Commercial Product : Ta=0 to 70¡É, unless otherwise specified 2) Extended Product : TA=-25 to 85¡É, nless otherwise specified 3) Industrial Product : Ta=-40 to 85¡É, unless otherwise specified ** TA=25¡É DATA RETENTION WAVE FORM 1) CS Controlled VCC Data Retention Mode tSDR tRDR 4.5V 2.2V VDR CS¡Ã VCC - 0.2V CS GND FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Current Mode H X X Power Down High-Z ISB ISB1 L H H Output Disable High-Z ICC L H L Read Dout ICC L L X Write Din ICC * X means don't care Revision 3.0 April 1996 PRELIMINARY CMOS SRAM KM62256C Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE (1)(Address Controlled) ( CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH) tRC Address tOH tAA tCO CS tHZ tOE OE tOLZ tOHZ Data out High-Z tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device output voltage levels. to device. Revision 3.0 April 1996 PRELIMINARY CMOS SRAM KM62256C Family TIMING WAVEFORM OF WRITE CYCLE(1)(WE Controlled) tWC Address tWR(4) tCW(2) CS tAW tWP(1) WE tAS(3) tDW Data in tDH Data Valid tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tWR(4) tAS(3) tCW(2) CS tAW tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap( tWP) of low CS and low WE. A write begins at the latest transition among CS goes low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. Revision 3.0 April 1996 PRELIMINARY CMOS SRAM KM62256C Family PACKAGE DIMENSIONS Units :Millimeters(Inches ) 28 PIN DUAL INLINE PACKAGE(600mil) +0.10 -0.05 +0.004 0.010-0.002 0.25 #15 15.24 0.600 #28 13.60 ¡¾ 0.20 0.535 ¡¾ 0.008 #1 #14 0~15¡É 3.81 ¡¾ 0.20 0.150 ¡¾ 0.008 36.72 MAX 1.446 5.08 0.200 MAX 36.32 ¡¾ 0.20 1.430 ¡¾ 0.008 3.30 ¡¾ 0.30 0.130 ¡¾ 0.012 0.46 ¡¾ 0.10 0.018 ¡¾ 0.004 1.52 ¡¾ 0.10 0.060 ¡¾ 0.004 ( 1.65 ) 0.065 0.38 0.015 MIN 2.54 0.100 28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil) 0~8¡É #15 8.38 ¡¾ 0.20 11.81 ¡¾ 0.30 0.465 ¡¾ 0.012 0.330 ¡¾ 0.008 #1 #14 +0.10 -0.05 0.006+0.004 -0.05 0.15 2.59 ¡¾ 0.20 0.102 ¡¾ 0.008 18.69 0.736 MAX 11.43 0.450 #28 1.02 ¡¾ 0.20 0.040 ¡¾ 0.008 3.00 0.118MAX 18.29 ¡¾ 0.20 0.720 ¡¾ 0.008 0.10 MAX 0.004 MAX ( 0.89 ) 0.035 0.41 ¡¾ 0.10 0.016 ¡¾ 0.004 1.27 0.050 0.05 MIN 0.002 Revision 3.0 April 1996 PRELIMINARY CMOS SRAM KM62256C Family PACKAGE DIMENSIONS Units :Millimeters(Inches ) 1.10 MAX 0.004 MAX 28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) +0.10 -0.05 +0.004 0.008-0.002 0.20 13.40 ¡¾ 0.20 0.528 ¡¾ 0.008 #1 #28 0.55 0.0217 #14 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( #15 1.00 ¡¾ 0.10 0.039 ¡¾ 0.004 0.05 0.002 MIN 1.20 0.047 MAX 1.10 MAX 0.004 MAX 28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R) +0.10 -0.05 +0.004 0.008-0.002 0.20 13.40 ¡¾ 0.20 0.528 ¡¾ 0.008 #14 #15 0.55 0.0217 #1 0.25 0.010 TYP #28 11.80 ¡¾ 0.10 0.465 ¡¾ 0.004 +0.10 -0.05 0.006+0.004 -0.002 0.15 1.00 ¡¾ 0.10 0.039 ¡¾ 0.004 0.05 0.002 MIN 1.20 0.047 MAX 0~8¡É 0.45 ~0.75 0.018 ~0.030 0.425 ) 0.017 8.00 0.315 8.40 0.331 MAX ( ( 0.50 ) 0.020 Revision 3.0 April 1996