SANYO LE28FV4001CTS-20

Preliminary Specifications
CMOS LSI
LE28FV4001CTS-20
4M-Bit (512k × 8) Flash EEPROM
Features
CMOS Flash EEPROM Technology
Single 3.3-Volt Read and Write Operations
Sector Erase Capability: 256 Bytes per sector
Fast Access Time: 200 ns
Low Power Consumption
Active Current(Read): 10 mA (Max.)
Standby Current: 15 µA (Max.)
High Read/Write Reliability
Sector-write Endurance Cycles: 104
10 Years Data Retention
Latched Address and Data
Self-timed Erase and Programming
Byte Programming: 40µ
µs (Max.)
End of Write Detection:Toggle Bit/ DATA Polling
Hardware/Software Data Protection
JEDEC Standard Byte-Wide EEPROM Pinouts
Packages Available
LE28FV4001CTS: 32-pin TSOP Normal(8×14mm)
Product Description
program or data memory. For all system applications, the
LE28FV4001C significantly improves performance and
reliability, while lowering power consumption when
compared with floppy diskettes or EPROM approaches.
EEPROM technology makes possible convenient and
economical updating of codes and control programs on-line.
The LE28FV4001C improves flexibility, while lowering the
cost, of program and configuration storage applications.
The LE28FV4001C is a 512K ×8 CMOS sector erase,
byte program EEPROM. The LE28FV4001C is
manufactured using SANYO's proprietary, high performance
CMOS Flash EEPROM technology. Breakthroughs in
EEPROM cell design and process architecture attain better
reliability
and
manufacturability
compared
with
conventional approaches. The LE28FV4001C erases and
programs with a 3.3-volt only power supply. LE28FV4001C
conforms to JEDEC standard pinouts for byte wide
memories and is compatible with existing industry standard
EPROM, flash EPROM and EEPROM pinouts.
Featuring high performance programming,
the
LE28FV4001C typically byte programs in 30µs. The
LE28FV4001C typically sector (256 bytes) erases in 2ms.
Both program and erase times can be optimized using
interface feature such as Toggle bit or DATA Polling to
indicate the completion of the write cycle. To protect against
an inadvertent write, the LE28FV4001C has on chip hardware
and software date protection schemes. Designed,
manufactured, and tested for a wide spectrum of applications,
the LE28FV4001C is offered with a guaranteed sector write
endurance of 104 cycles. Data retention is rated greater then
10 years.
Figure 1 shows the pin assignments for the 32 lead
Plastic TSOP packages. Figure 2 shows the functional block
diagram of the LE28FV4001C. Pin description and
operation modes can be found in Tables 1 through 3.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the device
using standard microprocessor write sequences. A command
is written by asserting WE low while keeping CE low.
The address bus is latched on the falling edge of WE , CE ,
whichever occurs last. The data bus is latched on the rising
edge of WE , CE , whichever occurs first. However, during
the software write protection sequence the address are
latched on the rising edge of OE or CE , whichever occurs
first.
The LE28FV4001C is best suited for applications that
require reprogrammable nonvolatile mass storage of
*This product incorporate technology licensed from Silicon Storage Technology, Inc.
This preliminary specification is subject to change without notice.
SANYO Electric Co., Ltd. Semiconductor Company
1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN
Revision 2.20-February 23,2001-AY/ay-1/14
LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
A11
A9
A8
A13
A14
A17
WE
Vcc
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 pin TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Normal
(Top View)
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
Figure 1: Pin Assignments for 32-pin Plastic TSOP
XDECODER
A18-A0
4,194,304 Bit
SuperFlash EEPROM
Cell Array
ADDRESS
BUFFERS
&
LATCHES
Y-DECODER
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
&
DATA LATCHES
DQ7-DQ0
Figure 2: Functional Block Diagram of LE28FV4001C
SANYO Electric Co., Ltd.
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LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Table 1: Pin Description
Symbol
Pin Name
A18-A0
Functions
Address Inputs
To provide memory address. Address are internally latched during write cycle.
DQ7-DQ0 Data Input/Output
To output data during read cycle and receive input data during write cycles. Data is internally
latched during a write cycle. The outputs are in tri-state when OE or CE is high.
CE
Chip Enable
To activate the device when CE is low. Deselects and puts the device to standby when CE is
high.
OE
Output Enable
To activate the data output buffers. OE is active low.
WE
Write Enable
To activate the write operation. WE is active low.
VDD
Power Supply
To provide 3.3V±0.3V supply.
VSS
Ground
Table 2: Operation Modes Selection
Mode
Read
Write
Standby
Write Inhibit
Product ID
CE
OE
WE
DQ
Address
VIL
VIL
VIH
X
X
VIL
VIL
VIH
X
VIL
X
VIL
VIH
VIL
X
X
VIH
VIH
DOUT
DIN
High-Z
High-Z / DOUT
High-Z / DOUT
Manufacturer Code (BF)
Device Code (04)
AIN
AIN
X
X
X
A18-A1=VIL, A9=12V, A0=VIL
A18-A1=VIL, A9=12V, A0=VIH
Table 3: Command Summary
Command
Sector_Erase
Byte_Program
Reset
Read_ID
Software_Data_Unprotect (6)
Software_Data_Protect (6)
Required
Setup Command Cycle
Cycle
Operation Address
Data
2
Write
X
20H
2
Write
X
10H
1
Write
X
FFH
3
Write
X
90H
7
7
Execute Command Cycle
Operation Address
Data
Write
SA
D0H
Write
PA
PD
Read
(7)
(7)
SDP
N
N
Y
Y
Definitions for Table 3:
1.
2.
3.
4.
5.
6.
Type definitions : X=high or low
Address definitions : SA=Sector Address=A18-A8 ; sector size=256byte ; A7-A0=X for this command
Address definitions : PA=Program Address=A18-A0
Data definition : PD=Program Data, H=number in hex.
SDP=Software Data Protect mode using 7-Read-Cycle-Sequence.
Y=the operation can be executed with software data protect enabled. N=the operation cannot be executed with software data protect enabled.
Refer to Figure 11 and 12 for the 7-Read-Cycle-Sequence Software Data Protection.
7.
Address 0000H retrieves the manufacturer code of BF(Hex), address 0001H retrieves the device code of 04(Hex).
SANYO Electric Co., Ltd.
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LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Command Definition
Table 3 contains a command list and a brief summary of the
commands.
The following is a detailed description of the options initiated
by each command.
The LE28FV4001C has to have the Software Data Unprotect
Sequence executed prior a Byte Program or Erase in order to
perform those functions.
Sector_Erase Operation
The Sector_Erase operation is initiated by a setup command
and an execute command. The setup command stages the device
for electrical erasing of all bytes within a sector. A sector contains
256 bytes. This sector erasability enhances the flexibility and
usefulness of the LE28FV4001C, since most applications only
need to change a small number of bytes or sectors, not the entire
chip. The setup command is performed by writing (20H) to the
device. To execute the sector-erase operation, the execute
command (D0H) must be written to the device. The erase operation
begins with the rising edge of the WE pulse and terminated
automatically by using an internal timer. See Figure 8 for timing
waveforms.
The two-step sequence of a setup command followed by an
execute command ensures that only memory contents within the
addressed sector are erased and other sectors are not inadvertently
erased.
Sector_Erase Flowchart Description
Fast and Reliable erasing of the memory contents within a
sector is accomplished by following the sector erase flowchart as
shown in Figure 3. The entire procedure consists of the execution
of two commands. The Sector_Erase operation will terminate after
a maximum of 4ms. A Reset command can be executed to
terminate the erase operation; however, if the erase operation is
terminated prior to the 4ms time-out, the sector may not be
completely erased. An erase command can be reissued as many
times an necessary to complete the erase operation. The
LE28FV4001C cannot be “overerased”.
Byte_Program Operation
operation begins with either the rising edge of WE , CE ,
whichever occurs first. The programming operation is terminated
automatically by an internal timer. See the programming
characteristics and waveforms for details, Figures 4, 6 and 7.
The two-step sequence of a setup command followed by an
execute command ensures that only the addressed byte is
programmed and other bytes are not inadvertently programmed.
The Byte_Program Flow Chart Description
Programming data into the device is accomplished by following
the Byte_Program flowchart as shown in Figure 3. The
Byte_Program command sets up the byte for programming. The
address bus is latched on the falling edge of WE , CE ,
whichever occurs last. The data bus is latched on the rising edge of
WE , CE , whichever occurs first, and begins the program
operation. The end of write can be detected using either the
DATA polling or Toggle bit.
Reset Operation
A Reset Command is provided as a means to safely abort the
erase or program command sequences. Following either setup
command (erase or program) with a write of (FFH) will safely
abort the operation. Memory contents will not be altered. After the
Reset command, the device returns to the read mode. The reset
command dose not enable write protect. See figure 10 for timing
waveforms.
Read Operation
The read operation is initiated by setting CE , OE and WE
into the read mode. See Figure 5 for read memory timing
waveforms and Table 2 for the read mode. Read cycles from the
host retrieve data from the array. The device remains enabled for
read until another operating mode is accessed.
During initial power-up, the device is in the read mode and is
write protected. The device must be unprotected in order to execute
a write operation
The read operation is controlled by OE and CE at logic low.
When CE is high, the chip is deselected and only standby power
will be consumed. OE is the output control and is used to gate to
the output pins. The data bus is in a high impedance state when
either CE or OE is high.
The Byte_Program operation is initiated by writing the setup
command (10H).
Once the program setup is performed, programming is executed
by the next WE pulse. See Figure 6 and 7 for timing waveforms.
The address bus is latched on the falling edge of WE , CE , or
the rising edge of OE , whichever occurs first. The programming
SANYO Electric Co., Ltd.
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LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Read_ID Operation
DATA Polling (DQ7)
The Read_ID operation is initiated by writing a single
command (90H). A read of address 0000H will outputs the
manufacturer’s code (BFH). A read of address 0001H will outputs
the device code (04H).Any other valid command will terminate this
operation.
The LE28FV4001C features DATA Polling to indicate the
and of a write cycle. During a write cycle, any attempt to read the
last byte loaded will result in the complement of the loaded data on
DQ7. Once the write cycle is completed, DQ7 will show true data.
See Figure 13 for timing waveforms. In order for DATA Polling
to function correctly, the byte being polled must be erased prior to
programming.
Data Protection from Inadvertent Writes
In order to protect the integrity of nonvolatile data storage, the
LE28FV4001C provides hardware and software features to prevent
writes to the device, for example, during system power-up or
power-down. Such provisions are described below.
Hardware Write Protection
The LE28FV4001C is designed with hardware features to
prevent inadvertent writes. This is done in the following ways:
1. Write Inhibit Mode: OE low, CE high or WE high
inhibit the write operation.
2. Noise and Glitch Protection: Write operations are initiated
when the WE pulse width is less than 15 ns.
3. After power-up the device is in the read mode and the
device is in the write protect state.
Toggle Bit (DQ6)
An alternate means for determining the end of a write cycle is
by monitoring the Toggle Bit DQ6. During a write operation,
successive attempts to read data from the device will result in DQ6
toggling between logic "1" (high) and "0" (low). Once the write
cycle has completed, DQ6 will stop toggling and valid data will be
read. The Toggle Bit may be monitored any time during the write
cycle. See Figure 14 for timing waveforms.
Successive Reads
An alternate means for determining the end of a write cycle is
by reading the same address for two consecutive data matches.
Product Identification
Software Data Protection
Provisions have been made to further prevent inadvertent writes
through software. In order to perform the write functions of erase
or program, a two-step command sequence consisting of a setup
command followed by an execute command avoids inadvertent
erasing or programming of the device.
The LE28FV4001C will default to write protect after power-up.
A sequence of seven consecutive reads at specified device
addresses will unprotect the device. The address sequence is
1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. The
address has to be latched in the rising edge of OE or CE ,
whichever occurs first. A similar seven read sequence of 1823H,
1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect the
device. Also, refer to Figure 11, 12 for the 7-read-sequence
Software Write Protection. The DQ pins can be in any state (i.e.,
high, low, or High-Z).
The Product Identification mode identifies the device and
manufacturer as SANYO. This mode may be accessed by hardware
or software operations. The hardware operation is typically used by
an external programming to identify the correct algorithm for the
SANYO LE28FV4001C. Users may wish to use the software
operation to identify the device (i.e., using the device code). For
details, see Table 2 for the hardware operation. The manufacturer
and device codes are the same for both operations.
Notes for Operation
During power up, the device’s state should be the write
inhibition mode. (During power up, the device’s state should be
CE =VIH or OE =VIL or WE =VIH)
If CE = WE =VIL and OE =VIH during power up, RESET
command should be asserted before operation.
End of Write Detection
Detection of where a write cycle ended is necessary to optimize
system performance. The end of a write cycle (erase or program)
can be detected by three means: 1) monitoring the DATA polling
bit; 2) monitoring the Toggle bit; 3) by two successive reads of the
same data. These three detection mechanisms are described below.
SANYO Electric Co., Ltd.
5/14
LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Start
Initial
Sector Address
Execute Two Step
Sector Erase Command
Read FF
from Device
N
Verify FF
Y
Increment
Address
N
Last Address?
Y
Sector Erase
Completed
Erase Error
Figure 3: Sector_Erase Flowchart
SANYO Electric Co., Ltd.
6/14
LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Start
Initialize
Addresses
Setup Byte
Program Command
Load Address
and Data &
Start Programming
Read End of
Write Detection
Programming
Completed?
N
Y
Data Verifies?
N
Programming
Failure
Next Address
Y
N
Last Address
Y
Programming
Completed
Figure 4: Byte_Program Flowchart
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LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Absolute Maximum Stress Ratings
Temperature Under Bias..........................................................-55 °C ~ 125 °C
Storage Temperature................................................................-65 °C ~ 150 °C
D.C. Voltage on Any Pin to Grand Potential ...........................-0.5V ~ VCC+0.5V
Transient Voltage (<20ns) on any Pin to Grand Potential .......-1.0V ~ VCC+1.0V
Voltage on A9 to Grand Potential............................................-0.5V ~ 14.0V
Operating Range
Ambient Temperature..............................................................0 °C ~ 70 °C
Supply Voltage (VDD) .............................................................3.0V ~ 3.6V
DC Operating Characteristics
Symbol
Parameter
Limit
Min.
Typ.
Units
Test Condition
Max.
ICCR
Power Supply Current
(Read)
10
mA
CE = OE =VIL, WE =VIH, all DQs open
Address inputs=VIH / VIL, at f=1/tRC, VDD=VDD max.
ICCW
Power Supply Current
(Write)
25
mA
CE = WE =VIL, OE =VIH, VDD=VDD max.
ISB2
Standby VDD Current
(CMOS input)
15
µA
CE =VDD-0.3V, VDD=VDD max.
ILI
Input Leakage Current
10
µA
VIN=VSS~VDD, VDD=VDD max.
ILO
Output Leakage Current
10
µA
VOUT=Vss~VDD, VDD=VDD max.
VIL
Input Low Voltage
-0.3
0.6
V
VDD=VDD max.
VIH
Input High Voltage
2.0
Vcc+0.3
V
VDD=VDD max.
VOL
Output Low Voltage
0.4
V
IOL=100µA, VDD=VDD min.
VOH
Output High Voltage
V
IOH= -100µA, VDD=VDD min.
2.4
Power-up Timing
Symbol
Parameter
Minimum
Units
tPU_READ
Power-up to Read Operation
10
ms
tPU_WRITE
Power-up to Write Operation
10
ms
Capacitance (Ta=25°C, f=1MHz)
Maximum
Units
CDQ
Symbol
DQ Pin Capacitance
Descriptions
12
pF
VDQ = 0V
Test Condition
CIN
Input Capacitance
6
pF
VIN = 0V
SANYO Electric Co., Ltd.
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LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
AC Characteristics
Read Cycle Timing Parameters
Symbol
tRC
tCE
tAA
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Parameter
-20
Min.
200
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold Time
Units
Max.
200
200
100
0
0
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Erase/Program Cycle Timing Parameters
Symbol
Parameter
-20
Min.
tSE
tBP
tAS
tAH
tCS
tCH
tOES
tOEH
tCP
tWP
tCPH
tWPH
tDS
tDH
tRST
tPCP
tPCH
tPAS
tPAH
Sector Erase Cycle Time
Byte Program Cycle Time
Address Setup Time
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
Output Enable Setup Time from WE
Output Enable Hold Time from WE
Write Pulse Width ( CE )
Write Pulse Width
CE High Pulse Width
WE High Pulse Width
Data Setup Time
Data Hold Time
Reset Command Recovery Time
Protect Chip Enable Pulse Width
Protect Chip Enable High Time
Protect Address Setup Time
Protect Address Hold Time
Units
Max.
4
40
10
50
0
0
10
10
100
100
50
50
50
10
4
100
150
40
100
ms
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
AC Test Conditions
Input Load Levels ....................................................................1TTL Gate and CL=30pF
Input Rise/Fall Time ................................................................10ns
SANYO Electric Co., Ltd.
9/14
LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Figure 5: Read Cycle Diagram
tRC
A18-0
tCE
CE
tOE
tAA
OE
tOHZ
tOLZ
WE
tOH
tCHZ
tCLZ
DQ7-0
DATA VALID
DATA VALID
Figure 6: WE Controlled Write Cycle Timing Diagram
tAS
tAH
A18-0
tCS
tCH
CE
tOEH
OE
tOES
tWPH
tWP
WE
tDS
DQ7-0
tDH
DATA VALID
SANYO Electric Co., Ltd.
10/14
LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Figure 7: CE Controlled Write Cycle Timing Diagram
tAS
tAH
A18-0
tCP
CE
tCPH
OE
tOES
tOEH
WE
tDS
DQ7-0
tDH
DATA VALID
Figure 8: Sector Erase Timing Diagram
Self-timed Page
Erase Cycle
Execute command
Setup command
A18-0
AIN
tAS
tAH
WE(CE)
OE
tSE
CE(WE)
tDS
DQ7-0
tDH
tDS
(20H)
tDH
(D0H)
SANYO Electric Co., Ltd.
11/14
LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Figure 9: Byte Program Timing Diagram
Self-timed Program
Cycle
Execute command
Setup command
A18-0
AIN
tAS
tAH
WE(CE)
OE
tBP
CE(WE)
tDS
DQ7-0
tDH
tDS
(10H)
tDH
DIN
Figure 10: Reset Command Timing Diagram
Reset command
A18-0
WE(CE)
OE
CE(WE)
tDS
DQ7-0
tDH
(FFH)
tRST
SANYO Electric Co., Ltd.
12/14
LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Figure 11: Software Data Unprotect Sequence
OE
tPCH
tPCP
CE
Address
1823
1820
1822
0418
041B
0419
041A
041B
0419
040A
tPAH
tPAS
Notes on Figure 11
1.
2.
The address is latched on the rising edge of CE or WE , whichever is earlier.
Pins A16 to A18 should be at either VIL or VIH
Figure 12: Software Data Protect Sequence
OE
tPCH
tPCP
CE
Address
1823
tPAS
1820
1822
0418
tPAH
Notes on Figure 12
1.
2.
The address is latched on the rising edge of CE or WE , whichever is earlier.
Pins A16 to A18 should be at either VIL or VIH
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13/14
LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
Figure 13: DATA Polling Timing Diagram (DQ7)
A18-0
AN
AN
AN
AN
tBP
WE
tCE
tOES
CE
tOEH
tOE
OE
DQ7
DIN=X
DOUT=X
DOUT=X
DOUT=X
Figure 14: Toggle Bit Timing Diagram (DQ6)
A18-0
Note
WE
tCE
CE
tOEH
OE
tOES
tOE
DQ6
Note: This time interval signal can be tSE or tBP, depending upon the selected operation mode.
SANYO Electric Co., Ltd.
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