Ordering number : EN8370B Bi-CMOS IC LV23100V For Portable Audio System 1-chip Tuner IC Incorporating PLL Overview The LV23100V is a one-chip tuner IC incorporating PLL for portable audio system. Functions • AM tuner • FM tuner • MPX stereo decoder • PLL frequency synthesizer Specifications Maximum Ratings at Ta = 25 °C Parameter Symbol Conditions Maximum supply voltage VCC max Maximum input voltage VIN2 max XIN Allowable power dissipation Maximum output voltage Ratings Unit VCC 4.0 V VDD max VDD 4.0 V VIN1 max CE, CI, CL 6.0 V VDD+0.3 V Ta≤70°C 180 mW VO1 max Pd max DO 6.0 V VO2 max XOUT, PD VDD+0.3 V VO3 max BO1, BO2, AOUT 12.0 V Operating temperature Topr -20 to +70 °C Storage temperature Tstg -40 to +125 °C Note : This product should be handled with care because the resistance against electrostatic discharge damage is low. • • CCB is a registered trademark of SANYO Electric Co., Ltd. CCB is SANYO Semiconductor's original bus format. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 42308 MS / 31407 MS PC / 63005 MS PC No.8370-1/12 LV23100V Operating Condition at Ta = 25 °C Parameter Recommended supply voltage Operating supply voltage range Symbol Conditions Ratings Unit VCC 3.0 V VDD 3.0 V VCC op 2.2 to 3.6 V VDD op 2.2 to 3.6 V PLL block Allowable Operating Range at Ta = -20°C to +70°C, VSS = 0V Parameter Symbol Ratings Conditions min Supply voltage VDD Input high level voltage VIH CE, CL, DI Input low level voltage VIL Output voltage VO1 Operating frequency typ Unit max 2.2 3.6 V 0.7VDD 6.0 V CE, CL, DI 0 0.3VDD - DO 0 6.0 V VO2 BO1, BO2, AOUT 0 fIN1 XIN ; VIN1 fIN2 FMIN ; VIN2 10 75 10 V kHz 160 MHz fIN3 AMIN (SNS = 1) ; VIN3 2 40 MHz fIN4 AMIN (SNS = 0) ; VIN4 0.5 10 MHz Note : Due attention must be paid on leak because the XIN pin has an extremely high input impedance. Operating Characteristics at Ta = 25°C, VCC = VDD = 3.0V, See the specified circuit. Parameter Symbol Ratings Conditions min typ Unit max [Current dissipation] FM tuner block ICCFM No input in FM mode 9 12.5 16 mA AM tuner block ICCAM No input in AM mode 4 6 8 mA PLL block IDDFM fr = 98MHz, No input at tuner 1 2 4 mA [FM-FE characteristics] : fc = 98MHz, fm = 1kHz, dev = 22.5kHz 3dB sensitivity -3dBLS VIN = 60dBµV EMF reference, -3dB input 10 dBµV S/N = Input at S/N = 30dB 13 dBµV EMF Actual sensitivity QS EMF [FM-IF characteristics] : fc = 10.7MHz, fm = 1kHz, dev = 75kHz (L+R = 90%, Pilot = 10%) Demodulation output VO VIN = 100dBµV 3dB sensitivity LS VIN = 100dBµV reference, -3dB input Signal-to-noise ratio 180 210 mVrms 26 31 36 dBµV VIN = 100dBµV 63 70 IF count sensitivity IF-C1 0%mod, SDC = 1 42 50 56 dBµV Total harmonic distortion THD VIN = 100dBµV, MAIN-MOD 0.5 1.5 % SEP VIN = 100dBµV, L output/R output 25 40 dB VIN = 100dBµV, L output 55 60 dB Separation Mute attenuation S/N 140 MUTE dB [AM characteristics] : fc = 1000kHz, fm = 1kHz, 30%mod Demodulation output VO VIN = 80dBµV 30 50 Signal-to-noise ratio 1 S/N1 VIN = 23dBµV 15 20 Signal-to-noise ratio 2 S/N2 VIN = 80dBµV 47 53 Total harmonic distortion THD VIN = 80dBµV IF count sensitivity IF-C 0%mod 0.5 20 27 70 mVrms dB dB 1.5 % 34 dBµV Continued on next page. No.8370-2/12 LV23100V Continued from preceding page. Parameter Symbol Ratings Conditions min typ Unit max [PLL characteristics] Internal return resistance Rf Built-in output resistance XIN Rd XOUT Hysteresis width VHIS CE, CL, DI Output high level voltage VOH VOL1 PD ; IO = -1mA PD ; IO = 1mA VOL2 Output low level voltage Input high level current Input low level current 8 MΩ 250 kΩ 0.1VDD V VDD-1.0 V 1.0 V BO1, BO2 ; IO = 1mA 0.25 V BO1, BO2 ; IO = 5mA 1.25 V VOL3 DO ; IO = 1mA 0.25 V VOL4 AOUT ; IO = 1mA, AIN = 2.0V 0.5 V 5.0 µA 0.9 µA IIH1 CE, CL, DI ; VI = 6.0V IIH2 XIN ; VI = VDD 0.16 IIH3 AIN ; VI = 6.0V 200 nA IIL1 CE, CL, DI ; VI = 0V 5.0 µA IIL2 XIN ; VI = 0V 0.9 µA IIL3 0.16 AIN ; VI = 0V 200 nA IOFF1 BO1, AOUT, BO2 ; VO = 10V 5.0 µA IOFF2 DO ; VO = 6.0V 5.0 µA ”H” level 3-state off-leak current IOFFH PD ; VO = 6.0V 0.01 200 nA ”L” level 3-state off-leak current IOFFL PD ; VO = 0V 0.01 200 NA Output off-leak current Package Dimensions unit : mm (typ) 3247A 7.6 19 0.5 5.6 36 1 18 0.2 (0.7) 0.8 (1.5) 0.1 15.0 1.7max 0.3 SANYO : SSOP36(275mil) No.8370-3/12 LV23100V Composition of DI control data (serial data input) (1) IN mode Address DI (2)R-CTR R3 R1 TEST0 R2 0 R0 1 DVS CTE SNS GT1 XS P15 GT0 (3)IF-CTR P14 0 P12 P13 P11 UL0 DZ P10 DOC2 P9 DOC1 P8 (1)P-CTR P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 1 0 1 0 0 (2) IN2 mode Address TEST2 TEST1 (2)R-CTR (13)TEST DLC (12)PD-C (3)IF-CTR (11)DZ-C UL1 SDC (8)SD-C (10)UNLOCK STSW (6)BDSW (7)STSW (9)DO-C BDSW (5)IFSW DOC0 IFSW BO1 (4)O-PORT BO2 0 1 1 0 0 1 0 1 0 0 0 DI Description of DI control Data No. (1) Control block data DO pin Control data Description Related data • Data to set the dividing number of programmable divider Binary value with P15 assumed to be MSB. LSB varies according to DVS and SNS. (* : don’t care) DOC0 DVS DOC1 DOC2 SNS LSB set dividing number (N) actual dividing number 1 * P0 272 to 65535 Twice the set value 0 1 P0 272 to 65535 Set value 0 0 P4 4 to 4095 Set value * P0 to P3 invalid when LSB : P4 • To select the signal input (FMIN, AMIN) to the programmable divider and to change the input frequency range. (* : don’t care) DVS SNS Input Operation frequency range 10 to 160MHz 1 * FMIN 0 1 AMIN 2 to 40MHz 0 0 AMIN 0.5 to 10MHz Continued on next page. No.8370-4/12 LV23100V Continued from preceding page. No. Control block data (2) Reference divider data Description Related data • Reference frequency (fref) selection data R3 R2 R1 R0 Reference frequency R0 to R3 0 0 0 0 25kHz XS 0 0 0 1 25kHz 0 0 1 0 25kHz 0 0 1 1 25kHz 0 1 0 0 12.5kHz 0 1 0 1 6.25kHz 0 1 1 0 3.125kHz 0 1 1 1 3.125kHz 1 0 0 0 5kHz 1 0 0 1 5kHz 1 0 1 0 5kHz 1 0 1 1 1kHz 1 1 0 0 3kHz 1 1 0 1 15kHz 1 1 1 0 PLL INHIBIT+X’tal OSC STOP 1 1 1 1 PLL INHIBIT * PLL INHIBIT • The programmable divider and IF counter stop, with FMIN, AMIN, and IFIN inputs being in the pull-down condition (GND), and the charge pump has the high impedance. • XS must be zero. (3) IF counter • IF counter counting start data control data CTE = 1 : Counting start = 0 : Counting start CTE GT0, GT1 (4) Output port data • Determines the counting time of universal counter GT1 GT0 Counting time Wait time 0 0 4ms 3 to 4ms 0 1 8ms 3 to 4ms 1 0 16ms 3 to 4ms 1 1 32ms 3 to 4ms • Data to determine output of output ports BO1 and BO2 “Data” = 0 : OPEN BO1, BO2 (5) MUTE control data 1 : Low • Data to determine the output of output port IFSW, controlling the MUTE function. “Data” = 0 : at receiving 1 : MUTE IFSW (6) FM/AM BAND selection control data • Data to determine the output of output port BDSW, controlling selection of BAND. “Data” = 0 : AM 1 : FM BDSW (7) Forced monaural control data • Data to determine the output of output port STSW, controlling the forced stereo functions. “Data” = 0 : MONO 1 : STEREO STSW (8) SD sensitivity control data SDC • Data to determine the output of output port SDC, controlling the FM-SD sensitivity (at IF input). SDC FM-SD sensitivity 0 38dBµV 1 48dBµV Continued on next page. No.8370-5/12 LV23100V Continued from preceding page. No. Control block data (9) DO pin control data Description Related data • Data to determine the output of the DO pin. UL0, UL1 DOC2 DOC1 DOC0 DO pin condition DOC0 0 0 0 Open DOC1 0 0 1 Low when unlock is detected. DOC2 0 1 0 end-UC (See the item with asterisk below) 0 1 1 Open 1 0 0 Open 1 0 1 Low when stereo 1 1 0 Low when SDON 1 1 1 Open CTE • The open condition is selected at power ON/reset. ~ ~ * IF counter counting end check ~ ~ DO pin 1 Counting start 2 Counting end 3 CE : HI 1 With end-UC set and IF counter starting (CTE = 0→1), DO pin opens automatically. 2 At end of counting of the IF counter, DO pin goes LOW and check on counting end can be made. 3 DO pin opens when serial data is entered/output (CE pin : Hi) Note : DO pin is always in the open condition during data input (IN1 and IN2 modes, during CE : Hi period), regardless of DO pin control data (DOC0 to 2). In the DO pin condition during data output (OUT mode, CE-Hi period), the content of internal DO serial data is output in synchronization with CL, regardless of DO pin control data (DOC). (10) Unlock detection • Phase error (φE) detection width selection data to judge if PLL is locked. DOC0 data • Phase error exceeding the detection width is judged that PLL is locked DOC1 (* : don’t care) UL0, UL1 UL1 UL0 φE Detection width 0 0 Stop Open 0 1 0 Direct output of φE 1 * ±6.67µs φE extended by 1 to 2 ms DOC2 Detection output * DO pin is LOW. Serial data output : UL = 0. (11) Phase comparator control data DZ • Data to control the dead zone of phase comparator DZ Charge pump output 0 DZA 1 DZB Dead zone width : DZA<DZB (12) Charge pump control data DLC • Data to enforce control of charge pump output DLC Charge pump output 0 Normal 1 Forced to LOW In case of dead lock because of VCO oscillation stop when the VCO control voltage (Vtune) is 0V, it is possible to clear dead lock by setting the charge pump output to LOW and V tune to VCC. (Dead lock clear circuit) (13) LSI test data • LSI test data TEST0 TEST0 to 2 TEST1 All to be set to “0” TEST2 All set to zero at power ON/reset No.8370-6/12 LV23100V DO control data (serial data output) composition (1) OUT mode C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 (3)IF-CTR C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 (2)UNLOCK (1)IN-PORT UL DO 0 0 1 0 1 0 1 0 0 STIND DI SDIND Address Description of DO output data No. Control block data (1) SD and Stereo • Data latching SD and stereo indicator conditions. indicators Latching made in the data output (OUT) mode. control data Description SDIND←SD indicator condition 0 : SD ON, 1 : SD OFF STIND←Stereo indicator condition 0 : ST ON, 1 : ST OFF Related data STIND, SDIND (2) PLL unlock data • Data latching the content of unlock detection circuit UL←0 : At unlock UL (3) IF counter, binary counter UL0 UL1 1 : At lock or detection stop mode • Data latching the content of IF counter (20-bit binary counter) CTE C19←MSB of binary counter GT0 C0 ←MSB of binary counter GT1 C19 to C0 No.8370-7/12 LV23100V Serial data input (IN1/IN2) tSU, tHD, tEL, tES, tEH≥0.75µs tLC<0.75µs CL : Normally Hi tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data CL : Normally Low tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data Serial data output (OUT) tSU, tHD, tEL, tES, tEH≥0.75µs tDC, tDH<0.35µs CL : Normally Hi tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC tDC I2 DC I1 tDH UL C3 C2 C1 C0 CL : Normally Hi tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC DC tDC I2 I1 tDH UL C3 C2 C1 C0 (Note) DO pin is an Nch open drain pin, so that the data varying time (tDC and tDH) differs depending on the pull-up resistance and substrate capacity. No.8370-8/12 LV23100V ~ Serial data timing VIH tCL VIH VIL VIH VIH DI VIL tSU VIH VIL tHD tEL ~ ~ ~ ~ ~ ~ CL VIL VIL DO Internal data latch VIH VIL ~ ~ ~ ~ ~ ~ ~ tCH ~ ~ CE tES tDC tDC tEH tDH tLC Old New VIH VIL VIH VIH VIH DI VIL tSU tHD DO Internal data latch ~ ~ ~ ~ ~ ~ ~ VIH VIL ~ tCL VIH VIL tEL VIL tES tDC tEH ~ ~ ~ ~ ~ ~ tCH ~ CE CL ~ << When CL stops at the “L” level >> tDH tLC Old New << When CL stops at the “H” level >> Parameter Symbol Pin Conditions Min Typ Max Unit Data setup time tSU DI, CL 0.75 µs Data hold time tHD DI, CL 0.75 µs Clock “L” level time tCL CL 0.75 µs Clock “H” level time tCH CL 0.75 µs CE wait time tEL CE, CL 0.75 µs CE setup time tES CE, CL 0.75 µs CE hold time the CE, CL 0.75 Data latch change time tLC Data output time tDC DO, CL Differs depending on the pull-up resistance tDH DO, CE and substrate capacity µs 0.75 µs 0.35 µs No.8370-9/12 LV23100V Block Diagram and Sample Application Circuit No.8370-10/12 LV23100V Test Circuit No.8370-11/12 LV23100V Coil specifications (bottom view) • FM-BPF : GFWB3 (Soshin) 76MHz to 108MHz • FM-RF : SA-149 (Sumida) 3.6mm diameter, air core, 0.6mm wire, 4.5T • FM-OSC : SA-151 (Sumida) 3.6mm diameter, air core, 0.6mm wire, 3.5T • FM-IF Filter : SFELA10M7GA00 (Murata) • FM-Discriminator : CDALA10M7GA121 (Murata) • AM-OSC : SA-181 (Sumida) S V.D. 4 pin31 3 6-4 37T 3-1 74T 0.06UEW 2 fo = 796kHz GND 1 6 V CC Qo≥80 S L = 140µH • AM-MIX : SA-164 (Sumida) 1-2 S pin5 3 VCC 4 C.F. 2 122T 4-6 9T 2-3 62T 0.06UEW 1 fo = 450kHz, Qo≥65 6 GND S C = 180pF • AM-IF Filter : SFULA450KU2B (Murata) • MW Bar-antenna : C8E-A0105 (Toko) 1 S1 V.D. 2 3 S2 4 GND Pin1 Pin2 1-2 67T 3-4 9T fo = 796kHz 1 4 2 3 Qo = 180min L = 260µH • Crystal oscillator : CFV-206 (Citizen) SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of April, 2008. Specifications and information herein are subject to change without notice. PS No.8370-12/12