SANYO LV4124W

Ordering number : EN6000
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Monolithic Linear IC
LV4124W
Single-chip LCD panel driver IC
(Supports the ALP202 LCD panel)
Overview
Package Dimensions
The LV4124W is a LCD panel driver for use in lowtemperature polysilicon TFT LCDs that integrates an RGB
decoder, a driver, and a timing controller in a single chip.
This IC is manufactured in Bi-CMOS process and
supports the ALP202 2.0-inch color LCD panel.
unit: mm
SQFP-64
[LV4124W]
Functions
• Analog block: RGB decoder/driver
• Digital block: Timing generator
Features
•
•
•
•
•
•
•
Supports NTSC/PAL standard
Supports composite, Y/C, and Y/color difference inputs
Built-in BPF, TRAP, and DL circuits
Sharpness function
Dual point γ correction circuit
Pre-charge circuit
R and B outputs delay time correction circuit
(Supports up and down and right and left inversions)
• Polarity reverse circuit
• External RGB input supported
• Line inversion supported
• Supports AC drive for the LCD panel during no signal
• Serial bus for mode setting and electric VR
SANYO: SQFP64
Package
• SQFP-64 plastic package
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
82198RM (OT) No.6000-1/21
LV4124W
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Maximum supply voltage
Allowable power dissipation
Conditions
Rating
Units
VCC1 max
Analog 4.5V system
6
VCC2 max
Analog 12V system
14
V
VDD max
Digital system
4.5
V
Pd max
With Ta ≤ 75°C*
V
350
mV
Operating temperature
Topr
–15 to +75
°C
Storage temperature
Tstg
–40 to +125
°C
Input pin voltage
VINA
Analog input pins
VIND
Digital input pins
–0.3 to VCC1
V
–0.3 to VDD+0.3
V
Rating
Units
Note *: When mounted on a printed circuit board (30 × 30 mm, t = 1.6 mm, material: glass/epoxy)
Operating Conditions at Ta = 25°C
Parameter
Symbol
Recommended supply voltage
Operating supply voltage range
Conditions
VCC1
Analog 4.5V system
4.5
VCC2
Analog 12V system
12.0
V
VDD
Digital system
3.0
V
V
VCC1op
Analog 4.5V system
4.25 to 5.25
V
VCC2op
Analog 12V system
11 to 13.5
V
VDDop
Digital system
2.7 to 3.6
V
Electrical Characteristics at VCC1 = 4.5 V, VCC2 = VCCPCD = 12.0 V, GND1 = GND2 = GNDPCD = 0 V, VDD =
3.0 V VSS1 = VSS2 = 0 V, and Ta = 25°C
DC Characteristics
Ratings
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Parameter
Symbol
Conditions
min
typ
max
Unit
[Current Characteristics]
ICC11
Input SIG4 to (A) and SIG2 (0 dB) to (B).
Measure the ICC1 current.
Composite input
22
29
35
mA
Y/C input
21
28
34
mA
ICC13
Input SIG4 to (A), (D), and (E).
Measure the ICC1 current.
Y/color difference
input
18
23
28
mA
Current drain: VCC2
12V system
ICC2
Input SIG4 to (A) and SIG2 (0 dB) to (B).
Measure the ICC2 current.
4.5
6.5
8.5
mA
Current drain: VDD
MOS circuit blocks
IDD
Input SIG4 to (A) and SIG2 (0 dB) to (B).
Measure the IDD current.
4.5
6.0
7.5
mA
Current drain: VCC1
4.5V system
ICC12
[Digital Block Input and Output Characteristics]
Input current
II1
Input pins with built-in pull-up resistors *1
VIN = VSS
–24
–60
–145
µA
II2
Input pins with built-in pull-down resistors *2
VIN = VDD
24
60
145
µA
High-level output voltage
VOH1
Ioh = –1 mA *3
Low-level output voltage
VOL1
Iol = 1 mA *3
CKO pin high-level output voltage
VOH2
Ioh = –3 mA
CKO pin low-level output voltage
VOL2
Iol = 3 mA
RPD pin high-level output voltage
VOH3
Ioh = –0.5 mA
RPD pin low-level output voltage
VOL3
Ioh = 0.7 mA
RPD pin output off leakage current
IOFF
In the high-impedance state, VOUT = VSS or VDD.
Input voltage threshold (high)
VTDH
Input pins *1, *2
Input voltage threshold (low)
VTDL
Input pins *1, *2
VDD – 0.2
V
0.3
0.5VDD
0.5VDD
VDD – 1.2
–40
V
V
V
V
1.0
V
40
µA
0.7VDD
V
0.3VDD
V
Notes: 1. Input pins with built-in pull-up resistors: VDIN, CSH, CSV, SCLK, DATA, and LOAD
2. Input pins with built-in pull-down resistors: PANEL and TEST
3. Output pins other than CKO and RPD: XSTH, STH, CKH2, CKH1, PCG2, PCG1, HD, XSTV, STV, CKV2, CKV1, XENB, ENB, and VD.
No.6000-2/21
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LV4124W
AC Characteristics (1) when the T41, T44, and T46 outputs are measured at the noninverted outputs.
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
[Luminance Signal System]
Contrast characteristics (typ.)
GCNTTP
Input SIG4 to (A) and measure the ratio of the T44 output
amplitude (white - black) to the input amplitude.
13
17
21
dB
Contrast characteristics (min.)
GCNTMN
Input SIG4 to (A) and measure the ratio of the T44 output
amplitude (white - black) to the input amplitude.
–9
–5
–1
dB
GV
Input SIG4 to (A) and measure the ratio of the T44 output
amplitude (white - black) to the input amplitude.
19
22
25
dB
Maximum video gain
[Luminance Signal Frequency Characteristics]
Y/C input
FCYYC
NTSC
FCYCMN
PAL
FCYCMP
Composite input
GSHP1X
Image quality adjustment
range 1 (Y/C input)
GSHP1N
GSHP3X
Image quality adjustment
range 3 (composite input)
GSHP3N
Chrominance signal leakage
CRLEKY
5.0
Take the T44 output amplitude with SIG7 (0 dB, no burst,
100 kHz) input to (A) as 0 dB. Modify the input frequency
and determine the frequency such that the output is down
–3 dB.
2.5
MHz
2.5
Take the T44 output amplitude with SIG7
(100 kHz) input to (A) as 0 dB. Determine
the ratio of the output amplitude with a
2.5-MHz SIG7 input.
MAX
Take the T44 output amplitude with SIG7
(100 kHz) input to (A) as 0 dB. Determine the
ratio of the output amplitude with a 2.0-MHz
SIG7 input.
MAX
12
16
dB
MIN
0
6
2
10
dB
MIN
–2
Input SIG2 (0 dB) to (A) and using a spectrum analyzer,
measure the 3.58 and 4.43 MHz components in the input and
in T44. Let ∆CLK be that difference. Use that value to
determine CRLEKY from the following formula:
CRLEKY = 150 mV × 10∆CLK/20
3
30
mV
[Luminance Signal Input to Output Delay]
Y/C input
TDYYC
NTSC
TDYCMN
PAL
TDYCMP
Composite input
Input SIG5 (VL = 150 mV) to (A).Measure the delay time
between a rising edge in the input and the corresponding
rising edge in the T44 noninverted output.
250
350
450
ns
500
600
700
ns
500
600
700
ns
+4
+6
[Color Difference Signal System]
GEXCMX
Color difference input color
adjustment
GEXCMN
Color difference balance
VEXCBL
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (D). Let VC0 be the T41 output amplitude
(100 kHz) when COL = 128. Let VC2 be the T41 output
amplitude (100 kHz) when COL = 0. Let VC1 be the T41
output amplitude (100 kHz) when SIG1 is set to -10 dB and
COL = 255. Then calculate the following formulas.
GEXCMX = 20log (VC1/VC0) +10
GEXCMN = 20log (VC2/VC0)
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (D) and (E).
Let VB be the T41 output amplitude (100 kHz), and let VR
be the T46 output amplitude (100 kHz).
Calculate VEXCBL = VR/VB.
0.85
dB
–15
–11
dB
1
1.15
–
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No.6000-3/21
LV4124W
Continued from preceding page
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
[Color Difference Signal System]
GEXRMX
Input SIG5 (VL = 150 mV) to (A) and SIG1 (–6 dB, 100 kHz,
no burst) to (D) and (E).
When TINT = 128, let VR0 be the T46 output amplitude
(100 kHz) and let VB0 be the T41 output amplitude (100 kHz).
When TINT = 255, let VR1 be the T46 output amplitude and
let VB1 be the T41 output amplitude.
When TINT = 0, let VR2 be the T46 output amplitude and let
VB2 be the T41 output amplitude.
Then calculate the following formulas.
GEXRMX = 20log (VR1/VR0) GEXRMN = 20log (VR2/VR0)
GEXBMX = 20log (VB1/VB0) GEXBMN = 20log (VB2/VB0)
+2
+3
dB
–3
–4.5
dB
–3
–4.5
dB
+2
+3
dB
VEXGBN
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (D).
Let VEXB be the T41 output amplitude (100 kHz) and
VEXBG be the T44 output amplitude (100 kHz).Calculate
VEXGB = VEXBG/VEXB.
0.21
0.24
0.27
–
VEXGRN
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (E).
Let VEXR be the T46 output amplitude (100 kHz) and
VEXRG be the T44 output amplitude (100 kHz).
Calculate VEXGR = VEXRG/VEXR.
0.46
0.51
0.56
–
VEXGRP
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (D).
Let VEXB be the T41 output amplitude (100 kHz) and
VEXBG be the T44 output amplitude (100 kHz).Calculate
VEXGB = VEXBG/VEXB.
0.17
0.19
0.21
–
VEXGRP
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (E).
Let VEXR be the T46 output amplitude (100 kHz) and
VEXRG be the T44 output amplitude (100 kHz).
Calculate VEXGR = VEXRG/VEXR.
0.46
0.51
0.56
–
Color difference input balance
adjustment R
GEXRMN
GEXBMX
Color difference input balance
adjustment B
GEXBMN
G-Y matrix characteristics
(NTSC)
G-Y matrix characteristics
(PAL)
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AC Characteristics (2)
Parameter
Symbol
Ratings
Conditions
min
typ
max
Unit
[Chrominance Signal System]
ACC amplitude characteristics 1
ACC amplitude characteristics 2
APC pull-in range
ACC1
ACC2
FAPC
Input SIG5 (VL = 150 mV) to (A), and to (B),
input SIG2 (0, +6, and –20 dB, 3.58 MHz,
burst/chrominance phase = 180°, and also
4.43 MHz, burst/chrominance phase = ±135°).
Measure the T53 output amplitude, and let V0,
V1, and V2 correspond to 0 dB, +6 dB, and
–20 dB, respectively.
ACC1 = 20log (V1/V0)
ACC2 = 20log (V2/V0)
Input SIG5 (VL = 150 mV) to (A), and to (B),
input SIG2 (0 dB, 3.58 MHz, burst/chrominance
phase = 180°, and also 4.43 MHz,
burst/chrominance phase = ±135°).
Measure the T44 output amplitude. Modify the
SIG2 burst frequency, until the killer is
released. Measure the frequency f1 that
appears in the T41 output.
NTSC f1 = 3579545 Hz
PAL
f1 = 4433619 Hz
NTSC
–3
0
+3
PAL
–3
0
+3
VTSC
–3
0
+3
PAL
–3
0
+3
dB
NTSC
±500
Hz
PAL
±500
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No.6000-4/21
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LV4124W
Continued from preceding page
Parameter
Symbol
Ratings
Conditions
min
typ
max
Unit
[Chrominance Signal System]
Color adjustment
characteristics (maximum)
GCOLMX
Color adjustment
characteristics (minimum)
GCOLMN
Tint adjustment range
(maximum)
TNTMX
Tint adjustment range
(minimum)
TNTMN
ACKN
Killer operating input level
ACKP
VRBN
Demodulator output
amplitude ratio (NTSC)
VGBN
θ RBN
Demodulator output phase
difference (NTSC)
θ GBN
VRBP
Demodulator output
amplitude ratio (PAL)
VGBP
θ RBP
Demodulator output phase
difference (PAL)
θ GBP
Input SIG5 (VL = 150 mV) to (A), and input SIG2 (0 dB,
burst/chrominance phase = 180°) to (B).
Let V0, V1, and V2 be the chrominance signal amplitude
when COL = 128, COL = 255, and COL = 0, respectively.
Calculate GCOLMX = 20log (V1/V0), and GCOLMN = 20log
(V2/V0).
Input SIG5 (VL = 150 mV) to (A), and input SIG2 (0 dB, with
a variable burst/chrominance phase) to (B).
Let θ 0, θ 1, and θ 2 be the phases when the T41 output
amplitude is minimum when TINT = 128, TINT = 255, and
TINT = 0, respectively.
Calculate TNTMX = θ1 – θ0, and TNTMN = θ2 – θ0.
Input SIG5 (VL = 150 mV) to (A), and to (B),
input SIG2 (with a variable level,
burst/chrominance phase = 180°, and also
burst/chrominance phase = ±135°).
Measure the T41 output amplitude.
Gradually lower the SIG3 level (amplitude) until
the killer function operates and measure that
level.
+4
+6
–20
dB
–15
dB
–30
–40
deg
30
40
deg
NTSC
–36
30
dB
PAL
–33
–27
dB
0.53
0.63
0.73
–
0.25
0.32
0.39
–
99
109
119
deg
230
242
254
deg
0.65
0.75
0.85
–
0.33
0.40
0.47
–
80
90
100
deg
232
244
256
deg
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
Modify the chrominance signal phase, let VB be the
maximum amplitude of the T41 chrominance demodulated
signal, let VG be the maximum amplitude of the T44
chrominance demodulated signal, and let VR be the
maximum amplitude of the T46 chrominance demodulated
signal
Calculate VRBN = VR/VB and VGBN = VG/VB.
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
Modify the chrominance signal phase, let θ B be the phase
at the maximum amplitude of the T41 chrominance
demodulated signal, let θ G be the phase at the maximum
amplitude of the T44 chrominance demodulated signal, and
let θ R be the phase at the maximum amplitude of the T46
chrominance demodulated signal.
Calculate θ RBN = θ R – θ B and θ GBN = θ G – θ B.
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
Modify the chrominance signal phase, let VB be the
maximum amplitude of the T41 chrominance demodulated
signal, let VG be the maximum amplitude of the T44
chrominance demodulated signal, and let VR be the
maximum amplitude of the T46 chrominance demodulated
signal
Calculate VRBP = VR/VB and VGBP = VG/VB.
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
Modify the chrominance signal phase, let θ B be the phase
at the maximum amplitude of the T41 chrominance
demodulated signal, let θ G be the phase at the maximum
amplitude of the T44 chrominance demodulated signal, and
let θ R be the phase at the maximum amplitude of the T46
chrominance demodulated signal.
Calculate θ RBP = θ R – θ B and θ GBP = θ G – θ B.
No.6000-5/21
LV4124W
AC Characteristics (3)
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
[RGB Signal and PCD Output Systems]
RGB signal and PCD output
DC voltage
VOUT
Input SIG5 (VL = 0 mV) to (A), adjust the BRIGHT parameter
with the serial bus data so that T44 is 9 Vp-p, and measure
the DC voltages on T39, T41, T44, and T46.
RGB signal and PCD output
DC voltage difference
∆VOUT
Determine the maximum value of the differences in the
measured values of VOUT in the previous item for T39, T41,
T44, and T46.
5.85
6.00
6.15
V
0
100
mV
VLIMMN
Input SIG3 to (A), and measure the maximum value
(VLIMMX) and minimum value (VLIMMN) of the voltage
range (black - black) over which the black limiter operates
when V54 is varied for T39, T41, T44, and T46.
Measure VLIMMX when V54 = 0 V, and measure VLIMMN
when V54 = 4.5 V.
BRTMX
Input SIG5 (VL = 0 mV) to (A) and set BRT to 0. Measure
the T41, T44, and T46 outputs (black - black).
BRTMN
Input SIG5 (VL = 0 mV) to (A) and set BRT to 255. Measure
the T41, T44, and T46 outputs (black - black).
PCDMX
Input SIG5 (VL = 0 mV) to (A) and measure the T39 output
(black - black) when P-BRT is set to 255.
PCDMN
Input SIG5 (VL = 0 mV) to (A) and measure the T39 output
(black - black) when P-BRT is set to 0.
Sub-brightness variation
SBBRT
Input SIG5 (VL = 0 mV) to (A) and measure the T44 output
(black - black) with respect to the T41 and T46 outputs
(black - black) when R-BRT = B-BRT = 0, and when R-BRT
= B-BRT = 255.
±2.0
±3.0
RGB inter-signal gain difference
∆GRGB
Input SIG4 to (A) and determine the level difference between
the largest and the smallest of the noninverted output
amplitudes (white - black) for T41, T44, and T46.
–0.5
0
0.5
dB
RGB inverted/noninverted gain
difference
∆GINV
Input SIG4 to (A) and determine the difference between
the inverted output amplitude and the noninverted output
amplitude (white - black) for T41, T44, and T46.
–0.5
0
0.5
dB
RGB inter-signal black level
potential difference
∆VBL
Input SIG4 to (A) and determine the difference between the
highest and lowest black levels in the inverted and
noninverted T41, T44, and T46 outputs.
300
mV
VLIMMX
RGB signal and PCD output
Color difference input balance
Brightness variation
PCD variation
9.0
Vpp
5.2
9.0
Vpp
Vpp
4.0
9.0
Vpp
Vpp
3
Vpp
V
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Gγ1
Gamma gain
Gγ2
Gγ3
Vγ1MN
Gamma 1 adjustment range
Vγ1MX
Vγ2MN
Gamma 2 adjustment range
Vγ2MX
tPCDH
PCD transition time
tPCDL
Input SIG8 to (A), adjust the T44 inverted output black level
to be 1.5 V with BRT, and adjust the amplitude (black white) to be 3.5 V with CONT. Measure VG1, VG2, and VG3
and calculate the following formulas.
Gγ1 = 20log (VG1/0.0357)
Gγ2 = 20log (VG2/0.0357)
Gγ3 = 20log (VG3/0.0357)
Input SIG8 to (A) and set the T44 output (black - black) to 9
V p-p with the BRIGHT adjustment. Read the gamma gain
transition point at the input signal IRE level when γ1 = 0 and
when γ1 = 255.
V γ1MN is when γ1 = 0, and Vγ1MX is when γ1 = 255.
Input SIG8 to (A) and set the T44 output (black - black) to 9
V p-p with the BRIGHT adjustment. Read the gamma gain
transition point at the input signal IRE level when γ2 = 0 and
when γ2 = 255.
V γ2MN is when γ2 = 0, and Vγ2MX is when γ2 = 255.
The transition time for a load of 8000 pF and an amplitude of
9 V p-p.
tPCDH: For rising edges. tPCDL: For falling edges.
23.0
26.0
29.0
dB
12.0
15.0
18.0
dB
18.0
21.0
25.0
dB
0
IRE
70
IRE
100
IRE
30
IRE
2.5
µs
2.5
µs
No.6000-6/21
LV4124W
AC Characteristics (4)
Parameter
Symbol
Ratings
Conditions
min
typ
max
Unit
[Filter Characteristics]
Bandpass filter attenuation
ATBPF
ATRAPN
Trap attenuation
ATRAPP
R-Y and B-Y low-pass filter
Input SIG5 (VL = 0 mV) to (A) and SIG1
(0 dB) to (B). Take the T53 chrominance
amplitude when the center frequency
(3.58 and 4.43 MHz) is input to be 0 dB,
and measure the T53 output attenuation
for the frequencies listed at the right.
NTSC 1.50 MHz
–15
–10
dB
PAL
2.00 MHZ
–15
–10
dB
NTSC 5.50 MHz
–7
–2
dB
PAL
–8
–3
dB
NTSC
–40
–30
dB
PAL
–40
–30
dB
0.9
1.1
MHz
Input SIG7 (0 dB, 3.58 and 4.43 MHz) to (A)
and measure the T44 output with a spectrum
analyzer. Taking the T44 amplitude in Y/C
mode to be 0 dB, determine the attenuation in
composite input mode.
6.80 MHz
Input SIG5 (VL = 150 mV) to (A) and SIG2 (0 dB, 3.58 MHz
+ 100 kHz) to (B). Take the T44 output 100 kHz component
am plitude at this time to be 0 dB, and determine the
frequency at which the output beat component is reduced by
3 dB when the SIG2 frequency is increased from 3.58 MHz.
0.7
WSSEP
Input SIG5 (VL = 0 mV, VS = 143 mV, variable WS) to (A)
and verify synchronization with the T23 HD output.
Determine the value of WS at the point synchronization with
the T23 HD output is lost when the SIG5 WS is gradually
made narrower starting at 4.7 µs.
2.0
VSSEP
Input SIG5 (VL = 0 mV, WS = 4.7 µs, variable VS) to (A) and
verify synchronization with the T23 HD output. Determine the
value of VS at the point synchronization with the T23 HD
output is lost when the SIG5 VS is gradually reduced starting
at 143 mV.
DEMLPF
[Sync Separator Circuit and TG System]
Input synchronizing signal
amplitude sensitivity
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Sync separator circuit input
sensitivity
TDSYL
Sync separator circuit output
delay
TDSYH
HPLLN
Horizontal pull-in range
HPLLP
Input SIG5 (VL = 0 mV, WS = 4.7 µs, VS = 143 mV) to (A)
and measure the delay time with respect to the T12 RPD
output. Here, TDSYL is the delay from the fall of the input
HSYNC signal to the fall of the T12 RPD output, and TDSYH
is the delay from the rise of the input HSYNC signal to the
rise of the T12 RPD output.
Input SIG5 (VL = 0 mV, WS = 4.7 µs, VS =
143 mV, variable horizontal frequency) to (A)
and verify synchronization withthe T23 HD
output. Determine the frequency fH at which
synchronization is achieved when the SIG5
horizontal frequency is varied starting from the
state where I/O synchronization is lost.
Calculate HPLLN = fH – 15734 and HPLLP =
fH – 15625.
µs
40
60
mV
430
630
830
ns
4.7
5.0
5.3
µs
NTSC
±500
Hz
PAL
±500
Hz
Continued on next page.
No.6000-7/21
LV4124W
Continued from preceding page
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
[External I/O Characteristics]
VTEXTB
External RGB input threshold
voltage
VTEXTW
TDEXTH
External RGB input to output
transmission delay time
TDEXTL
Input SIG5 (VL = 0 mV) to (A) and SIG6 (variable VL) to (C).
Let VEXTB be the voltage at which the T41, T44, and T46
outputs reach the black level when the amplitude (VL) is
raised starting at 0 V. Then, let VTEXTW be the voltage at
which the outputs reach the white level as the amplitude is
increased further.
Input SIG5 (VL = 0 mV) to (A) and SIG6 (VL = 3 V) to (C).
Measure TDEXTH, the delay in the T41, T44, and T46
output rise, and TDEXTL, the delay in the output fall time.
External RGB input to output
blanking level difference
EXTBK
Input SIG5 (VL = 0 mV) to (A) and SIG6 (VL = 1.7 V) to (C)
and measure the difference from the T41, T44, and T46
black levels.
External RGB input to output
white level difference
EXTWT
Input SIG5 (VL = 0 mV) to (A) and SIG6 (VL = 2.7 V) to (C)
and measure the difference from the T41, T44, and T46
black levels.
0.8
1
1.2
V
1.8
2.0
2.2
V
70
100
120
ns
70
100
120
ns
0
V
3.5
V
[Digital Block Output Characteristics]
Output transition time
(For the pins *3.)
Cross point time difference
CKH duty
tTLH
Input SIG5 (VL = 0 mV) to (A). Use a load of 30 pF.
tTHL
∆T
Input SIG5 (VL = 0 mV) to (A). Use a load of 30 pF.
CKH1/CKH2
DTYHC
Input SIG5 (VL = 0 mV) to (A). Use a load of 30 pF.
Measure the CKH1 and CKH2 duty.
47
50
30
ns
30
ns
10
ns
53
%
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No.6000-8/21
LV4124W
Block Diagram
SERIAL
BUS I/F
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No.6000-9/21
LV4124W
Analog Block Pin Functions
Units (Capacitors: F, Resistors: Ω)
Pin No.
Pin
Pin voltage
I/O
Input handling
Pin function
Equivalent circuit
External trap circuit
connection.
1
TRAP
Chrominance components are
excluded by a series LC
circuit (inductor and capacitor)
connected to ground.
–
(This pin is left open in Y/color
difference input mode.)
2
GND1
0V
Analog 4.5V system ground
Sync separator circuit lowpass filter input.
3
SYNCIN
1.5 V
I
4
H.FILOUT
2.3 V
O
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The standard input signal
level is 0.5 Vp-p (sync tip to
100% white level). The input
should be provided with low
impedance (under 75 Ω).
Sync separator circuit lowpass filter output
Sync separator circuit input.
5
S.SEPIN
1.0 V
I
Input the waveform that
results from passing the input
signal through the sync
separator circuit low-pass
filter to this pin.
Continued on next page.
No.6000-10/21
LV4124W
Continued from preceding page.
Units (Capacitors: F, Resistors: Ω)
Pin No.
Pin
6
EXTR
7
EXTG
8
EXTB
37
FBPCD
42
Pin voltage
I/O
Input handling
Pin function
Equivalent circuit
These pins are used to input
external digital signals.
–
I
FBB
2.5 V
O
There are two threshold
levels: Vth1 (about 1.0 V) and
Vth2 (about 2.0 V). If one of
the RGB signal exceeds Vth1,
then all of the RGB outputs
are set to the black level, and
the output only goes to the
white level when the input
exceeds Vth2.
Feedback circuit smoothing
capacitor connections. These
circuits are used to control the
DC levels in the RGB and
PCD outputs.
Since these are highimpedance circuits, capacitors
with low leakage must be
used.
45
FBG
47
FBR
38
GNDPCD
0V
39
PCD
6.0 V
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40
VCCPCD
12 V
Ground for the PCD circuit
O
PCD output
12V system power supply
used for the PCD circuit.
Use the same potential as
used for VCC2.
Continued on next page.
No.6000-11/21
www.DataSheet4U.com
LV4124W
Continued from preceding page.
Units (Capacitors: F, Resistors: Ω)
Pin No.
Pin
41
BOUT
44
GOUT
46
ROUT
43
GND2
0V
Analog 12V system ground
48
VCC2
12 V
Analog 12V system power
supply
49
VCC1
4.5 V
Analog 4.5V power supply
50
SIG
CENTER
Pin voltage
I/O
6.0 V
O
6.0 V
I
Input handling
Pin function
Equivalent circuit
RGB signal outputs
RGB output DC level setting
Continued on next page.
No.6000-12/21
www.DataSheet4U.com
LV4124W
Continued from preceding page.
Units (Capacitors: F, Resistors: Ω)
Pin No.
51
Pin
Pin voltage
I/O
BYIN
–
I
52
RYIN
53
COUT
1.6 V
O
54
BLKLIM
–
I
55
APC
2.7 V
O
56
VXOOUT
2.9 V
O
Input handling
Pin function
Equivalent circuit
These pins are used for the
color difference signal inputs
in Y/color difference input
mode. The clamp level in this
mpde is 2.8 V.
In other modes, the signal
from pin 53 is input to these
pins. In those modes the pin
voltage will be about 1.6 V.
The standard input signal
level is 0.3 V p-p for a 75%
color bar signal.
Provides the ACC output.
(This pin is left open in Y/color
difference input mode.)
Sets the RGB output
amplitude (black to black)
clipping level
APC filter connection.
(This pin is left open in Y/color
difference input mode.)
VXO output
(This pin is left open in Y/color
difference input mode.)
Continued on next page.
No.6000-13/21
LV4124W
Continued from preceding page.
Units (Capacitors: F, Resistors: Ω)
Pin No.
Pin
Pin voltage
I/O
57
VXOIN
3.2 V
I
58
VREG
3.6 V
O
Input handling
Pin function
Equivalent circuit
VXO input
(This pin is left open in Y/color
difference input mode.)
Regulator output
Connect a 1-µF or larger
external capacitor to this pin.
Inputs the video signal if a
composite input is used.
59
CIN
–
I
Inputs the chrominance signal
if separate Y and C signals
are used.
(This pin is left open in Y/color
difference input mode.)
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Connection for the capacitor
that determines the time that
the RGB outputs are held at
the black level when power is
first applied.
60
START-UP
–
I
Connect this pin to VCC1
through a resistor of about
22 KΩ if this function is not
used.
(Threshold level: 2.3 V)
Luminance (Y) signal input.
61
Y-IN
3.1 V
I
The standard input signal
level is 0.5 Vp-p (from the
sync tip to the 100% white
level.) The input should be
provided with low impedance
(under 75 Ω).
Continued on next page.
No.6000-14/21
LV4124W
Continued from preceding page.
Units (Capacitors: F, Resistors: Ω)
Pin No.
62
Pin
PICT
Pin voltage
–
I/O
I
Input handling
Pin function
Equivalent circuit
Used to adjustment the
luminance signal frequency
characteristics.
Outlines are emphasized as
the voltage is increased.
Filter adjustment resistor
connection.
63
64
FOADJ
PWRST
3.0 V
–
O
I
The reference current is
created by a 15-kΩ resistor
connected to ground.
Reset pin for the IC internal
CMOS circuits. A capacitor
should normally be connected
between this pin and ground.
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(Threshold level: 2.2 V)
No.6000-15/21
LV4124W
Digital Block Pin Functions
Units (Capacitors: F, Resistors: Ω)
Pin No.
Pin
9
VDIN
10
CSH
11
CSV
33
SCLK
Pin voltage
I/O
VDD
I
H
These input pins include
internal pull-up resistors
VSS2
I
L
These input pins include
internal pull-down resistors
O
34
DATA
35
LOAD
24
PANEL
36
TEST
12
RPD
–
13
VSS1
–
Input handling
Pin function
Equivalent circuit
Phase comparator output
(tristate)
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14
CKI
15
CKO
–
VCO circuit digital system
ground
I/O
Oscillator cell input and output
(L: Pulled down, H: Pulled up)
Continued on next page.
No.6000-16/21
www.DataSheet4U.com
LV4124W
Continued from preceding page.
Units (Capacitors: F, Resistors: Ω)
Pin No.
Pin
Pin voltage
16
VDD
–
17
XSTH
18
STH
19
CKH2
20
CKH1
21
PCG2
22
PCG1
23
HD
25
XSTV
26
STV
27
CKV2
28
CKV1
29
XENB
30
ENB
32
VD
31
VSS2
–
0V
I/O
Input handling
Pin function
Equivalent circuit
Digital system power supply
O
Digital block outputs
Digital system ground
No.6000-17/21
LV4124W
Electrical Characteristics Test Circuit
Units (Capacitors: F, Resistors: Ω)
220 pF
www.DataSheet4U.com
Notes: 1. The crystal used is the Kinseki, Ltd. CX-5F
Frequency deviation: Under ±30 ppm, Frequency temperature
characteristics: ±30 ppm
NTSC: 3.579545 MHz
PAL: 4.433619 MHz
2. Variable capacitance diode: 1T369 (Sony Corporation)
3. Inductance: 10 µH
4. Trap (TDK)
NTSC: NLT4532-S3R6B
PAL: NLT4532-S4R4
5. Resistor tolerance: ±2%, temperature coefficient: Under ±200 ppm.
No.6000-18/21
LV4124W
Measurement Waveforms
SG No.
Waveform
Sine wave video signal; with or
without burst.
(Variable amplitude, variable
frequency)
← The value at the left is 0 dB.
SIG1
Chrominance signal: burst and chrominance frequency (3.579545 or 4.433619 MHz)
Variable chrominance phase, variable burst frequency
← The value at the left is 0 dB.
SIG2
SIG3
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Five-step staircase wave
0.15 V
SIG4
The VL amplitude is variable.
Variable VS: 143 mV unless
otherwise specified.
SIG5
Variable WS: 4.7 µs unless otherwise
specified.
Variable fH: NTSC: 15.734 kHz or
PAL: 15.625 kHz unless
otherwise specified.
Continued on next page.
No.6000-19/21
LV4124W
Continued from preceding page
SG No.
Waveform
The VL amplitude is variable.
SIG6
SYNC timing
Variable frequency
SIG7
Ten-step staircase wave
SIG8
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2T pulse
The VL amplitude is variable.
Variable VS: 143 mV unless
otherwise specified.
SIG9
Variable WS: 4.7 µs unless otherwise
specified.
Variable fH: NTSC: 15.734 kHz or
PAL: 15.625 kHz unless
otherwise specified.
No.6000-20/21
LV4124W
www.DataSheet4U.com
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any and all SANYO products described or contained herein fall under strategic
products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of
Japan, such products must not be exported without obtaining export license from the Ministry of
International Trade and Industry in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of August, 1998. Specifications and information herein are subject to
change without notice.
PS No. 6000-21/21