MAXIM MAX12555

19-3447; Rev 0; 10/04
KIT
ATION
EVALU
E
L
B
A
AVAIL
14-Bit, 95Msps, 3.3V ADC
Features
♦ Direct IF Sampling Up to 400MHz
♦ Excellent Dynamic Performance
74.2dB/72.1dB SNR at fIN = 3MHz/175MHz
88.4dBc/74.7dBc SFDR at fIN = 3MHz/175MHz
♦ Low Noise Floor: 74.7dBFS
♦ 3.3V Low-Power Operation
465mW (Single-Ended Clock Mode)
497mW (Differential Clock Mode)
300µW (Power-Down Mode)
♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Full-Scale Analog Input Range
±0.35V to ±1.10V
♦ Common-Mode Reference
♦ CMOS-Compatible Outputs in Two’s Complement
or Gray Code
♦ Data-Valid Indicator Simplifies Digital Interface
♦ Data Out-of-Range Indicator
♦ Miniature, 6mm x 6mm x 0.8mm 40-Pin Thin QFN
Package with Exposed Paddle
♦ Evaluation Kit Available (Order MAX12555EVKIT)
Ordering Information
PART*
PIN-PACKAGE
PKG CODE
MAX12555ETL
40 Thin QFN
T4066-3
MAX12555ETL+
40 Thin QFN
T4066-3
+Denotes lead-free package.
*All devices specified over the -40°C to +85°C operating range.
Pin-Compatible Versions
PART
SAMPLING
RATE
(Msps)
RESOLUTION
(BITS)
TARGET
APPLICATION
MAX12555
95
14
IF/Baseband
IF and Baseband Communication Receivers
Cellular, Point-to-Point Microwave, HFC, WLAN
MAX12554
80
14
IF/Baseband
MAX12553
65
14
IF/Baseband
Medical Imaging Including Positron Emission
Tomography (PET)
Video Imaging
Portable Instrumentation
MAX19538
95
12
IF/Baseband
MAX1209
80
12
IF
MAX1211
65
12
IF
MAX1208
80
12
Baseband
Low-Power Data Acquisition
MAX1207
65
12
Baseband
MAX1206
40
12
Baseband
Applications
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX12555
General Description
The MAX12555 is a 3.3V, 14-bit, 95Msps analog-to-digital
converter (ADC) featuring a fully differential wideband
track-and-hold (T/H) input amplifier, driving a low-noise
internal quantizer. The analog input stage accepts singleended or differential signals. The MAX12555 is optimized
for high dynamic performance, low power, and small
size. Excellent dynamic performance is maintained from
baseband to input frequencies of 175MHz and beyond,
making the MAX12555 ideal for intermediatefrequency (IF) sampling applications.
Powered from a single 3.3V supply, the MAX12555 consumes only 497mW while delivering a typical 72.1dB
signal-to-noise ratio (SNR) performance at a 175MHz
input frequency. In addition to low operating power, the
MAX12555 features a 300µW power-down mode to
conserve power during idle periods.
A flexible reference structure allows the MAX12555 to use
the internal 2.048V bandgap reference or accept an
externally applied reference. The reference structure
allows the full-scale analog input range to be adjusted
from ±0.35V to ±1.10V. The MAX12555 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits.
The MAX12555 supports either a single-ended or differential input clock. Wide variations in the clock duty
cycle are compensated with the ADC’s internal dutycycle equalizer (DCE).
ADC conversion results are available through a 14-bit,
parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two’s complement or Gray code. A data-valid indicator eliminates
external components that are normally required for reliable digital interfacing. A separate digital power input
accepts a wide 1.7V to 3.6V supply, allowing the
MAX12555 to interface with various logic levels.
The MAX12555 is available in a 6mm x 6mm x 0.8mm,
40-pin thin QFN package with exposed paddle (EP),
and is specified for the extended industrial (-40°C to
+85°C) temperature range.
See the Pin-Compatible Versions table for a complete
family of 14-bit and 12-bit high-speed ADCs.
MAX12555
14-Bit, 95Msps, 3.3V ADC
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +3.6V
OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V
INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V
REFIN, REFOUT, REFP, REFN, COM
to GND................-0.3V to the lower of (VDD + 0.3V) and +3.6V
CLKP, CLKN, CLKTYP, G/T, DCE,
PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V
D13–D0, DAV, DOR to GND....................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
40-Pin Thin QFN 6mm x 6mm x 0.8mm
(derated 26.3mW/°C above +70°C)........................2105.3mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, fCLK = 95MHz (50% duty cycle, 1.4VP-P square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 2)
Resolution
14
Bits
Integral Nonlinearity
INL
fIN = 3MHz
±1.6
Differential Nonlinearity
DNL
fIN = 3MHz
±0.65
LSB
Offset Error
VREFIN = 2.048V
±0.1
±0.78
%FS
Gain Error
VREFIN = 2.048V
±0.35
±5.3
%FS
VDIFF
Differential or single-ended inputs
±1.024
V
VDD / 2
V
CPAR
Fixed capacitance to ground
LSB
ANALOG INPUT (INP, INN)
Differential Input Voltage Range
Common-Mode Input Voltage
Input Capacitance
(Figure 3)
CSAMPLE
2
Switched capacitance
pF
4.5
CONVERSION RATE
Maximum Clock Frequency
fCLK
95
MHz
Minimum Clock Frequency
5
Data Latency
Figure 6
MHz
8.0
Clock
cycles
-74.7
dBFS
DYNAMIC CHARACTERISTICS (Differential Inputs) (Note 2)
Small-Signal Noise Floor
SSNF
Input at less than -35dBFS
fIN = 3MHz at -0.5dBFS (Notes 3, 4)
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
SNR
SINAD
74.2
fIN = 47.5MHz at -0.5dBFS
73.8
fIN = 70MHz at -0.5dBFS
73.6
fIN = 175MHz at -0.5dBFS (Notes 3, 4)
66.9
72.1
fIN = 3MHz at -0.5dBFS (Notes 3, 4)
66.7
73.8
fIN = 47.5MHz at -0.5dBFS
73.5
fIN = 70MHz at -0.5dBFS
72.5
fIN = 175MHz at -0.5dBFS (Notes 3, 4)
2
67.6
64.0
69.8
_______________________________________________________________________________________
dB
dB
14-Bit, 95Msps, 3.3V ADC
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, fCLK = 95MHz (50% duty cycle, 1.4VP-P square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
fIN = 3MHz at -0.5dBFS (Notes 3, 4)
Spurious-Free Dynamic Range
SFDR
Second Harmonic
THD
HD2
Third Harmonic
HD3
Intermodulation Distortion
Third-Order Intermodulation
Two-Tone Spurious-Free
Dynamic Range
IMD
IM3
SFDRTT
TYP
88.4
fIN = 47.5MHz at -0.5dBFS
86.9
fIN = 70MHz at -0.5dBFS
80.5
fIN = 175MHz at -0.5dBFS (Notes 3, 4)
Total Harmonic Distortion
MIN
73.5
67.1
MAX
UNITS
dBc
74.7
fIN = 3MHz at -0.5dBFS
-85.1
fIN = 47.5MHz at -0.5dBFS
-84.7
fIN = 70MHz at -0.5dBFS
-79.0
fIN = 175MHz at -0.5dBFS
-73.6
fIN = 3MHz at -0.5dBFS
-89
fIN = 47.5MHz at -0.5dBFS
-92
fIN = 70MHz at -0.5dBFS
-91
fIN = 175MHz at -0.5dBFS
-82
fIN = 3MHz at -0.5dBFS
-92
fIN = 47.5MHz at -0.5dBFS
-93
fIN = 70MHz at -0.5dBFS
-81
fIN = 175MHz at -0.5dBFS
-75
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS
-79
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS
-75
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS
-80
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS
-76
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS
80
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS
76
-72.8
dBc
-66.1
dBc
dBc
dBc
dBc
dBc
Aperture Delay
tAD
Figure 4
1.2
ns
Aperture Jitter
tAJ
Figure 4
<0.2
psRMS
Output Noise
nOUT
INP = INN = COM
1.07
LSBRMS
1
Clock
cycles
Overdrive Recovery Time
±10% beyond full scale
_______________________________________________________________________________________
3
MAX12555
ELECTRICAL CHARACTERISTICS (continued)
MAX12555
14-Bit, 95Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, fCLK = 95MHz (50% duty cycle, 1.4VP-P square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.048
2.066
V
INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally)
REFOUT Output Voltage
VREFOUT
1.980
COM Output Voltage
VCOM
VDD / 2
1.65
V
Differential-Reference Output
Voltage
VREF
VREF = VREFP - VREFN = VREFIN x 3/4
1.536
V
REFOUT Load Regulation
REFOUT Temperature Coefficient
-1.0mA < IREFOUT < +0.1mA
TCREF
REFOUT Short-Circuit Current
35
mV/mA
+50
ppm/°C
Short to VDD—sinking
0.24
Short to GND—sourcing
2.1
mA
BUFFERED EXTERNAL REFERENCE (REFIN driven externally; VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated internally)
REFIN Input Voltage
VREFIN
2.048
V
REFP Output Voltage
VREFP
(VDD / 2) + (VREFIN x 3/8)
2.418
V
REFN Output Voltage
VREFN
(VDD / 2) - (VREFIN x 3/8)
0.882
V
COM Output Voltage
VCOM
VDD / 2
1.60
Differential-Reference Output
Voltage
VREF
VREF = VREFP - VREN = VREFIN x 3/4
1.454
1.65
1.70
V
1.604
V
Differential-Reference
Temperature Coefficient
±25
ppm/°C
REFIN Input Resistance
>50
MΩ
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; VREFP, VREFN, and VCOM are applied externally)
COM Input Voltage
VDD / 2
1.65
V
REFP Input Voltage
VREFP - VCOM
0.768
V
REFN Input Voltage
VREFN - VCOM
-0.768
V
VREF
VREF = VREFP - VREFN = VREFIN x 3/4
1.536
V
REFP Sink Current
IREFP
VREFP = 2.418V
1.4
mA
REFN Source Current
IREFN
VREFN = 0.882V
1.0
mA
COM Sink Current
ICOM
VCOM = 1.650V
1.0
mA
REFP, REFN Capacitance
13
pF
COM Capacitance
6
pF
Differential-Reference Input
Voltage
VCOM
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold
VIH
CLKTYP = GND, CLKN = GND
Single-Ended Input Low
Threshold
VIL
CLKTYP = GND, CLKN = GND
Minimum Differential Input
Voltage Swing
4
CLKTYP = high
0.8 x
VDD
V
0.2 x
VDD
0.2
_______________________________________________________________________________________
V
VP-P
14-Bit, 95Msps, 3.3V ADC
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, fCLK = 95MHz (50% duty cycle, 1.4VP-P square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Differential Input Common-Mode
Voltage
CONDITIONS
MIN
CLKTYP = high
Input Resistance
RCLK
Input Capacitance
CCLK
Figure 5
TYP
MAX
UNITS
VDD / 2
V
5
kΩ
2
pF
DIGITAL INPUTS (CLKTYP, DCE, G/T, PD)
Input High Threshold
VIH
Input Low Threshold
VIL
Input Leakage Current
Input Capacitance
0.8 x
OVDD
V
0.2 x
OVDD
VIH = OVDD
±5
VIL = 0
±5
CDIN
5
V
µA
pF
DIGITAL OUTPUTS (D13–D0, DAV, DOR)
Output-Voltage Low
VOL
Output-Voltage High
D13–D0, DOR, ISINK = 200µA
0.2
DAV, ISINK = 600µA
0.2
D13–D0, DOR, ISOURCE = 200µA
OVDD 0.2
DAV, ISOURCE = 600µA
OVDD 0.2
VOH
V
V
Tri-State Leakage Current
ILEAK
(Note 5)
±5
µA
D13–D0, DOR Tri-State Output
Capacitance
COUT
(Note 5)
3
pF
DAV Tri-State Output
Capacitance
CDAV
(Note 5)
6
pF
POWER REQUIREMENTS
Analog Supply Voltage
Digital Output Supply Voltage
VDD
3.15
3.3
3.60
V
OVDD
1.7
1.8
VDD +
0.3V
V
Normal operating mode,
fIN = 175MHz at -0.5dBFS, CLKTYP = GND,
single-ended clock
Analog Supply Current
IVDD
Normal operating mode,
fIN = 175MHz at -0.5dBFS,
CLKTYP = OVDD, differential clock
Power-down mode clock idle, PD = OVDD
141
mA
150.6
165
0.1
_______________________________________________________________________________________
5
MAX12555
ELECTRICAL CHARACTERISTICS (continued)
MAX12555
14-Bit, 95Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, fCLK = 95MHz (50% duty cycle, 1.4VP-P square wave), TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
Analog Power Dissipation
Digital Output Supply Current
SYMBOL
PDISS
IOVDD
CONDITIONS
MIN
TYP
MAX
UNITS
Normal operating mode,
fIN = 175MHz at -0.5dBFS, CLKTYP = GND,
single-ended clock
465
Normal operating mode,
fIN = 175MHz at -0.5dBFS,
CLKTYP = OVDD, differential clock
497
Power-down mode clock idle, PD = OVDD
0.3
Normal operating mode,
fIN = 175MHz at -0.5dBFS, OVDD = 1.8V,
CL ≈ 5pF
10.2
mA
Power-down mode clock idle, PD = OVDD
8
µA
mW
545
TIMING CHARACTERISTICS (Figure 6)
Clock Pulse-Width High
tCH
5.2
ns
Clock Pulse-Width Low
tCL
5.2
ns
5.2
ns
Data-Valid Delay
tDAV
CL = 5pF (Note 6)
Data Setup Time Before Rising
Edge of DAV
tSETUP
CL = 5pF (Notes 6, 7)
5.5
ns
Data Hold Time After Rising Edge
of DAV
tHOLD
CL = 5pF (Notes 6, 7)
4.0
ns
Wake-Up Time from Power-Down
tWAKE
VREFIN = 2.048V
10
ms
Note 1: Specifications ≥+25°C guaranteed by production test; <+25°C guaranteed by design and characterization.
Note 2: See definitions in the Parameter Definitions section at the end of this data sheet.
Note 3: Limit specifications include performance degradations due to a production test socket. Performance is improved when the
MAX12555 is soldered directly to the PC board.
Note 4: Due to test-equipment-jitter limitations at 175MHz, 0.15% of the spectrum on each side of the fundamental is excluded from
the spectral analysis.
Note 5: During power-down, D13–D0, DOR, and DAV are high impedance.
Note 6: Digital outputs settle to VIH or VIL.
Note 7: Guaranteed by design and characterization.
6
_______________________________________________________________________________________
14-Bit, 95Msps, 3.3V ADC
-60
HD3 HD5 HD7 HD9
-70
HD2
-80
-40
-50
HD5
-70
HD2
-80
-40
-50
-60
-90
-100
-100
-110
-110
5
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
-20
-30
-40
-50
-60
HD5
-70
0
-20
-30
HD2
-40
-50
-60
-70
-80
0
30 35 40 45
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
0
HD7
HD9
-20
-30
-40
-50
-60
-70
-90
-90
-100
-110
5
10 15 20 25
FREQUENCY (MHz)
-40
-50
-60
2 x fIN2 + fIN1 2 x fIN1 + fIN2
-70
2
-90
30 35 40 45
DIFFERENTIAL NONLINEARITY
0.8
0.6
0.4
1
0
-1
fIN1 + fIN2
-80
10 15 20 25
1.0
DNL (LSB)
fIN2
-30
5
FREQUENCY (MHz)
MAX12555 toc08
-20
fCLK = 95MHz
fIN1 = 172.4949MHz
AIN1 = -7.0dBFS
fIN2 = 177.493MHz
AIN2 = -7.0dBFS
SFDRTT = 74.6dBc
IMD = -73.6dBc
IM3 = -74.7dBc
0
INTEGRAL NONLINEARITY
INL (LSB)
fIN1
30 35 40 45
3
MAX12555 toc07
-10
2 x fIN1 + 3 x fIN2
2 x fIN1 + fIN2
FREQUENCY (MHz)
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
0
fIN2
-110
0
30 35 40 45
fIN1
fIN1 + fIN2
-80
-100
10 15 20 25
fCLK = 95MHz
fIN1 = 68.49579MHz
AIN1 = -6.9dBFS
fIN2 = 71.49933MHz
AIN2 = -7.0dBFS
SFDRTT = 77.9dBc
IMD = -76.4dBc
IM3 = -77.5dBc
2 x fIN2 + fIN1
-10
-90
5
30 35 40 45
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
-100
0
10 15 20 25
FREQUENCY (MHz)
-80
-110
5
FREQUENCY (MHz)
fCLK = 95MHz
fIN = 225.010376MHz
AIN = -0.5dBFS
SNR = 70.67dB
SINAD = 67.70dB
THD = -70.7dBc
SFDR = 72.5dBc
HD3
HD2
HD5
-10
AMPLITUDE (dBFS)
fCLK = 95MHz
fIN = 174.8895264MHz
AIN = -0.5dBFS
SNR = 71.29dB
SINAD = 68.98dB
THD = -72.8dBc
SFDR = 74.4dBc
HD3
MAX12555 toc04
0
-10
10 15 20 25
AMPLITUDE (dBFS)
0
10 15 20 25 30 35 40 45
FREQUENCY (MHz)
HD2
-80
-100
5
HD5
HD7
-70
-90
0
AMPLITUDE (dBFS)
-30
-90
-110
AMPLITUDE (dBFS)
MAX12555 toc02
-60
-20
MAX12555 toc06
-50
-30
fCLK = 95MHz
fIN = 70.00915527MHz
AIN = -0.5dBFS
SNR = 73.12dB
SINAD = 71.50dB
THD = -76.6dBc
SFDR = 77.8dBc
HD3
MAX12555 toc09
-40
-20
0
-10
AMPLITUDE (dBFS)
-30
fCLK = 95MHz
fIN = 47.30285645MHz
AIN = -0.5dBFS
SNR = 73.13dB
SINAD = 72.74dB
THD = -83.4dBc
SFDR = 85.1dBc
MAX12555 toc05
AMPLITUDE (dBFS)
-20
0
-10
AMPLITUDE (dBFS)
fCLK = 95MHz
fIN = 3.00354004MHz
AIN = -0.5dBFS
SNR = 73.82dB
SINAD = 73.31dB
THD = -82.8dBc
SFDR = 86.3dBc
MAX12555 toc01
0
-10
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
MAX12555 toc03
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
0.2
0
-0.2
-0.4
-0.6
-2
-0.8
-100
-110
-3
0
5
10 15 20 25
30 35 40 45
FREQUENCY (MHz)
-1.0
0
4096
8192
12288
DIGITAL OUTPUT CODE
16384
0
4096
8192
12288
16384
DIGITAL OUTPUT CODE
_______________________________________________________________________________________
7
MAX12555
Typical Operating Characteristics
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, fCLK ≈ 95MHz (50% duty cycle, 1.4VP-P square wave), TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, fCLK ≈ 95MHz (50% duty cycle, 1.4VP-P square wave), TA = +25°C, unless otherwise noted.)
74
fIN = 70MHz
95
90
SFDR, -THD (dBc)
70
68
66
64
75
65
SNR
SINAD
60
45
65
85
105
125
25
45
350
300
250
ANALOG + DIGITAL POWER
ANALOG POWER
200
65
85
105
125
25
45
65
85
105
125
105
125
SNR, SINAD
vs. SAMPLING RATE
SFDR, -THD
vs. SAMPLING RATE
POWER DISSIPATION
vs. SAMPLING RATE
SFDR, -THD (dBc)
68
66
64
85
80
75
70
65
SNR
SINAD
45
85
105
125
25
45
500
450
400
350
300
250
SFDR
-THD
60
65
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
550
POWER DISSIPATION (mW)
95
ANALOG + DIGITAL POWER
ANALOG POWER
200
65
85
105
MAX12555 toc15
fIN = 175MHz
90
70
600
MAX12555 toc14
MAX12555 toc13
100
72
125
25
45
65
85
fCLK (MHz)
fCLK (MHz)
fCLK (MHz)
SNR, SINAD
vs. ANALOG INPUT FREQUENCY
SFDR, -THD
vs. ANALOG INPUT FREQUENCY
POWER DISSIPATION
vs. ANALOG INPUT FREQUENCY
74
95
90
SFDR, -THD (dBc)
72
70
68
66
64
85
80
75
70
62
SNR
SINAD
60
65
SFDR
-THD
60
50
100 150 200 250 300 350 400
ANALOG INPUT FREQUENCY (MHz)
0
50
100 150 200 250 300 350 400
ANALOG INPUT FREQUENCY (MHz)
600
DIFFERENTIAL CLOCK
CL ≈ 5pF
550
POWER DISSIPATION (mW)
100
MAX12555 toc16
76
0
400
fCLK (MHz)
74
25
450
fCLK (MHz)
fIN = 175MHz
60
500
fCLK (MHz)
76
62
DIFFERENTIAL CLOCK
fIN = 70MHz
CL ≈ 5pF
550
SFDR
-THD
60
25
SNR, SINAD (dB)
80
70
62
8
85
MAX12555 toc17
SNR, SINAD (dB)
72
600
MAX12555 toc18
fIN = 70MHz
MAX12555 toc11
100
MAX12555 toc10
76
POWER DISSIPATION
vs. SAMPLING RATE
MAX12555 toc12
SFDR, -THD
vs. SAMPLING RATE
POWER DISSIPATION (mW)
SNR, SINAD
vs. SAMPLING RATE
SNR, SINAD (dB)
MAX12555
14-Bit, 95Msps, 3.3V ADC
500
450
400
350
300
250
ANALOG + DIGITAL POWER
ANALOG POWER
200
0
50
100 150 200 250 300 350 400
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
14-Bit, 95Msps, 3.3V ADC
80
60
55
50
45
40
75
70
65
60
35
55
SNR
SINAD
30
25
-35
-30
-25
-20
-15
-10
-5
0
-35
-30
-25
-20
-15
-10
-5
300
0
ANALOG + DIGITAL POWER
ANALOG POWER
-40
-35
-30
-25
-20
-15
-10
-5
SFDR, -THD
vs. ANALOG SUPPLY VOLTAGE
POWER DISSIPATION
vs. ANALOG SUPPLY VOLTAGE
fIN = 175MHz
95
SFDR, -THD (dBc)
69
68
85
80
75
70
66
65
SNR
SINAD
64
700
650
POWER DISSIPATION (mW)
MAX12555 toc22
100
60
2.8
3.0
3.2
3.4
600
550
500
450
400
ANALOG + DIGITAL POWER
ANALOG POWER
300
2.8
3.6
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
350
SFDR
-THD
3.0
3.2
3.4
3.6
2.8
3.0
3.2
3.4
3.6
AVDD (V)
AVDD (V)
SNR, SINAD
vs. DIGITAL SUPPLY VOLTAGE
SFDR, -THD
vs. DIGITAL SUPPLY VOLTAGE
POWER DISSIPATION
vs. DIGITAL SUPPLY VOLTAGE
SFDR, -THD (dBc)
90
70
68
66
64
85
80
75
70
65
SNR
SINAD
1.8
2.2
OVDD (V)
3.0
3.4
3.8
1.4
1.8
550
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
500
450
400
350
300
250
SFDR
-THD
60
2.6
600
POWER DISSIPATION (mW)
fIN = 175MHz
95
72
MAX12555 toc26
100
MAX12555 toc25
fIN = 175MHz
MAX12555 toc27
AVDD (V)
76
0
MAX12555 toc24
SNR, SINAD
vs. ANALOG SUPPLY VOLTAGE
67
SNR, SINAD (dB)
350
ANALOG INPUT AMPLITUDE (dBFS)
70
1.4
400
250
90
60
450
200
-40
71
62
500
ANALOG INPUT AMPLITUDE (dBFS)
72
74
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
ANALOG INPUT AMPLITUDE (dBFS)
fIN = 175MHz
65
550
50
74
73
600
SFDR
-THD
MAX12555 toc23
-40
SNR, SINAD (dB)
fIN = 175MHz
85
SFDR, -THD (dBc)
SNR, SINAD (dB)
65
MAX12555 toc20
fIN = 175MHz
70
90
MAX12555 toc19
75
POWER DISSIPATION
vs. ANALOG INPUT AMPLITUDE
MAX12555 toc21
SFDR, -THD
vs. ANALOG INPUT AMPLITUDE
POWER DISSIPATION (mW)
SNR, SINAD
vs. ANALOG INPUT AMPLITUDE
ANALOG + DIGITAL POWER
ANALOG POWER
200
2.2
2.6
OVDD (V)
3.0
3.4
3.8
1.4
1.8
2.2
2.6
3.0
3.4
3.8
OVDD (V)
_______________________________________________________________________________________
9
MAX12555
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, fCLK ≈ 95MHz (50% duty cycle, 1.4VP-P square wave), TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, fCLK ≈ 95MHz (50% duty cycle, 1.4VP-P square wave), TA = +25°C, unless otherwise noted.)
90
SFDR, -THD (dBc)
69
68
67
66
65
85
80
75
70
64
65
SNR
SINAD
62
-15
10
35
85
60
-15
10
35
60
350
300
ANALOG + DIGITAL POWER
ANALOG POWER
85
-40
-15
10
GAIN ERROR vs. TEMPERATURE
VREFIN = 2.048V
1.5
1.0
GAIN ERROR (%FS)
0.2
0.1
0
-0.1
-0.2
0.5
0
-0.5
-1.0
-0.3
-1.5
-0.4
-0.5
-2.0
-40
-15
10
35
TEMPERATURE (°C)
60
85
35
TEMPERATURE (°C)
2.0
MAX12555 toc31
VREFIN = 2.048V
0.3
OFFSET ERROR (%FS)
400
TEMPERATURE (°C)
OFFSET ERROR vs. TEMPERATURE
0.4
450
200
-40
TEMPERATURE (°C)
0.5
500
250
SFDR
-THD
60
-40
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
550
MAX12555 toc32
63
10
ANALOG POWER DISSIPATION (mW)
70
fIN = 175MHz
95
600
MAX12555 toc29
fIN = 175MHz
71
100
MAX12555 toc28
72
POWER DISSIPATION
vs. TEMPERATURE
SFDR, -THD vs. TEMPERATURE
MAX12555 toc30
SNR, SINAD vs. TEMPERATURE
SNR, SINAD (dB)
MAX12555
14-Bit, 95Msps, 3.3V ADC
-40
-15
10
35
60
85
TEMPERATURE (°C)
______________________________________________________________________________________
60
85
14-Bit, 95Msps, 3.3V ADC
2.04
2.03
3.0
2.5
1.99
1.97
2.0
1.5
2.031
0.5
1.96
1.95
-40°C
0
-1.5
-1.0
2.033
1.0
+25°C
-0.5
0.5
0
2.029
-3.0
-2.0
IREFOUT SINK CURRENT (mA)
-1.0
1.0
0
-40
-15
IREFOUT SINK CURRENT (mA)
35
60
85
REFP, COM, REFN
SHORT-CIRCUIT PERFORMACE
VREFP
3.5
2.5
MAX12555 toc37
3.0
3.0
VCOM
2.5
VOLTAGE (V)
2.0
1.5
VREFN
10
TEMPERATURE (°C)
REFP, COM, REFN
LOAD REGULATION
MAX12555 toc36
-2.0
2.035
+25°C
-40°C
1.98
2.037
+85°C
VREFOUT (V)
VREFOUT (V)
+85°C
2.00
VOLTAGE (V)
VREFOUT (V)
2.02
2.039
MAX12555 toc34
3.5
MAX12555 toc33
2.05
2.01
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
REFERENCE OUTPUT VOLTAGE
SHORT-CIRCUIT PERFORMANCE
MAX12555 toc35
REFERENCE OUTPUT VOLTAGE
LOAD REGULATION
VCOM
1.0
VREFP
2.0
1.5
VREFN
1.0
INTERNAL REFERENCE
MODE AND BUFFERED EXTERNAL
REFERENCE MODE
0.5
INTERNAL REFERENCE
MODE AND BUFFERED
EXTERNAL REFERENCE MODE
0.5
0
0
-2
-1
0
SINK CURRENT (mA)
1
2
-8
-4
0
4
8
12
SINK CURRENT (mA)
______________________________________________________________________________________
11
MAX12555
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T = low, fCLK ≈ 95MHz (50% duty cycle, 1.4VP-P square wave), TA = +25°C, unless otherwise noted.)
MAX12555
14-Bit, 95Msps, 3.3V ADC
Pin Description
PIN
NAME
FUNCTION
REFP
Positive Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFP to
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same
side of the PC board.
2
REFN
Negative Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFN to
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same
side of the PC board.
3
COM
Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to
GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the
opposite side of the PC board and connected to the MAX12555 through a via.
4, 7, 16,
35
GND
Ground. Connect all ground pins and EP together.
1
5
INP
Positive Analog Input
6
INN
Negative Analog Input
8
DCE
Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
Connect DCE high (OVDD or VDD) to enable the internal duty-cycle equalizer.
9
CLKN
Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND.
10
CLKP
Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND.
11
CLKTYP
12–15, 36
VDD
Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel
capacitor combination of ≥2.2µF and 0.1µF. Connect all VDD pins to the same potential.
17, 34
OVDD
Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a
parallel capacitor combination of ≥2.2µF and 0.1µF.
18
DOR
Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog
input is within its full-scale range (Figure 6).
19
D13
CMOS Digital Output Bit 13 (MSB)
20
D12
CMOS Digital Output Bit 12
21
D11
CMOS Digital Output Bit 11
22
D10
CMOS Digital Output Bit 10
23
D9
CMOS Digital Output Bit 9
24
D8
CMOS Digital Output Bit 8
25
D7
CMOS Digital Output Bit 7
26
D6
CMOS Digital Output Bit 6
27
D5
CMOS Digital Output Bit 5
12
Clock-Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect
CLKTYP to OVDD or VDD to define the differential clock input.
______________________________________________________________________________________
14-Bit, 95Msps, 3.3V ADC
PIN
NAME
28
D4
CMOS Digital Output Bit 4
FUNCTION
29
D3
CMOS Digital Output Bit 3
30
D2
CMOS Digital Output Bit 2
31
D1
CMOS Digital Output Bit 1
32
D0
CMOS Digital Output Bit 0 (LSB)
33
DAV
37
PD
38
REFOUT
39
REFIN
40
G/T
Output-Format-Select Input. Connect G/T to GND for the two’s-complement digital output format.
Connect G/T to OVDD or VDD for the Gray code digital output format.
—
EP
Exposed Paddle. The MAX12555 relies on the exposed paddle connection for a low-inductance ground
connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the
top-side PC board ground plane to the bottom-side PC board ground plane.
Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for
any input clock duty-cycle variations. DAV is typically used to latch the MAX12555 output data into an
external back-end digital circuit.
Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation.
Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN
or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a
≥0.1µF capacitor.
Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to
GND with a ≥0.1µF capacitor. In these modes, VREFP - VREFN = VREFIN x 3/4. For unbuffered external
reference mode operation, connect REFIN to GND.
MAX12555
T/H
+
Σ
−
FLASH
ADC
DAC
INP
T/H
STAGE 1
STAGE 2
STAGE 9
INN
STAGE 10
END OF PIPE
DIGITAL ERROR CORRECTION
D13–D0
OUTPUT
DRIVERS
D13–D0
Figure 1. Pipeline Architecture—Stage Blocks
______________________________________________________________________________________
13
MAX12555
Pin Description (continued)
MAX12555
14-Bit, 95Msps, 3.3V ADC
CLKP
CLKN
DCE
CLKTYP
CLOCK
GENERATOR
AND
DUTY-CYCLE
EQUALIZER
MAX12555
VDD
GND
OVDD
INP
INN
T/H
14-BIT
PIPELINE
ADC
DEC
OUTPUT
DRIVERS
MAX12555
CPAR
2pF
*CSAMPLE
4.5pF
CPAR
2pF
*CSAMPLE
4.5pF
D13–D0
DAV
DOR
BOND WIRE
INDUCTANCE
1.5nH
VDD
INN
REFIN
COM
VDD
INP
G/T
REFOUT
REFP
BOND WIRE
INDUCTANCE
1.5nH
REFERENCE
SYSTEM
POWER CONTROL
AND
BIAS CIRCUITS
PD
REFN
Figure 2. Simplified Functional Diagram
SAMPLING
CLOCK
Detailed Description
The MAX12555 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output, the total clock-cycle latency is 8.0
clock cycles.
Each pipeline converter stage converts its input voltage
into a digital output code. At every stage, except the
last, the error between the input voltage and the digital
output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12555 functional diagram.
Input Track-and-Hold (T/H) Circuit
Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies of 175MHz and beyond and
supports a common-mode input voltage of VDD / 2 ±0.5V.
The MAX12555 sampling clock controls the ADC’s
switched-capacitor T/H architecture (Figure 3) allowing
the analog input signal to be stored as a charge on the
sampling capacitors. These switches are closed (track)
when the sampling clock is high and open (hold) when
the sampling clock is low (Figure 4). The analog input
signal source must be capable of providing the dynamic current necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these
14
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS: RSAMPLE =
1
fCLK x CSAMPLE
Figure 3. Simplified Input T/H Circuit
capacitors must be charged to one-half LSB accuracy
within one-half of a clock cycle.
The analog input of the MAX12555 supports differential
or single-ended input drive. For optimum performance
with differential inputs, balance the input impedance of
INP and INN and set the common-mode voltage to midsupply (VDD / 2). The MAX12555 provides the optimum
common-mode voltage of V DD / 2 through the COM
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 10, 11, and 12.
Reference Output (REFOUT)
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX12555. The power-down logic input (PD) enables
and disables the reference circuit. The reference circuit
requires 10ms to power up and settle when power is
applied to the MAX12555 or when PD transitions from
high to low. REFOUT has approximately 17kΩ to GND
when the MAX12555 is in power-down.
The internal bandgap reference and its buffer generate
VREFOUT to be 2.048V. The reference temperature coefficient is typically +50ppm/°C. Connect an external ≥0.1µF
bypass capacitor from REFOUT to GND for stability.
______________________________________________________________________________________
14-Bit, 95Msps, 3.3V ADC
MAX12555
CLKP
CLKN
tAD
ANALOG
INPUT
tAJ
SAMPLED
DATA
T/H
TRACK
HOLD
TRACK
HOLD
TRACK
HOLD
TRACK
HOLD
Figure 4. T/H Aperture Timing
REFOUT sources up to 1.0mA and sinks up to 0.1mA
for external circuits with a load regulation of 35mV/mA.
Short-circuit protection limits I REFOUT to a 2.1mA
source current when shorted to GND and a 0.24mA
sink current when shorted to VDD.
Analog Inputs and Reference
Configurations
The MAX12555 full-scale analog input range is
adjustable from ±0.35V to ±1.10V with a VDD / 2 ±0.5V
common-mode input range. The MAX12555 provides
three modes of reference operation. The voltage at
REFIN (V REFIN ) sets the reference operation mode
(Table 1).
To operate the MAX12555 with the internal reference,
connect REFOUT to REFIN either with a direct short or
through a resistive divider. In this mode, COM, REFP,
and REFN are low-impedance outputs with V COM =
VDD / 2, VREFP = VDD / 2 + VREFIN x 3/8, and VREFN =
VDD / 2 - VREFIN x 3/8. The REFIN input impedance is
very large (>50MΩ). When driving REFIN through a
resistive divider, use resistances ≥10kΩ to avoid loading REFOUT.
Buffered external reference mode is virtually identical to
internal reference mode except that the reference
source is derived from an external reference and not
the MAX12555 REFOUT. In buffered external reference
mode, apply a stable 0.7V to 2.2V source at REFIN. In
this mode, COM, REFP, and REFN are low-impedance
outputs with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN
x 3/8, and VREFN = VDD / 2 - VREFIN x 3/8.
To operate the MAX12555 in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN
to GND deactivates the on-chip reference buffers for
COM, REFP, and REFN. With the respective buffers
deactivated, COM, REFP, and REFN become highimpedance inputs and must be driven through separate, external reference sources. Drive VCOM to VDD / 2
±5%, and drive REFP and REFN so VCOM = (VREFP +
VREFN) / 2. The full-scale analog input range is ±(VREFP
- VREFN) x 2/3.
Table 1. Reference Modes
VREFIN
REFERENCE MODE
35% VREFOUT to 100%
VREFOUT
0.7V to 2.2V
<0.4V
Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider.
The full-scale analog input range is ±VREFIN / 2:
VCOM = VDD / 2
VREFP = VDD / 2 + VREFIN x 3/8
VREFN = VDD / 2 - VREFIN x 3/8
Buffered External Reference Mode. Apply an external 0.7V to 2.2V reference voltage to REFIN.
The full-scale analog input range is ±VREFIN / 2:
VCOM = VDD / 2
VREFP = VDD / 2 + VREFIN x 3/8
VREFN = VDD / 2 - VREFIN x 3/8
Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources.
The full-scale analog input range is ±(VREFP - VREFN) x 2/3.
______________________________________________________________________________________
15
MAX12555
14-Bit, 95Msps, 3.3V ADC
All three modes of reference operation require the
same bypass capacitor combinations. Bypass COM
with a 2.2µF capacitor to GND. Bypass REFP and
REFN each with a 0.1µF capacitor to GND. Bypass
REFP to REFN with a 1µF capacitor in parallel with a
10µF capacitor. Place the 1µF capacitor as close to
the device as possible on the same side of the PC
board. Bypass REFIN and REFOUT to GND with a
0.1µF capacitor.
For detailed circuit suggestions, see Figure 13 and
Figure 14.
VDD
S1H
MAX12555
10kΩ
CLKP
10kΩ
Clock Input and Clock Control Lines
(CLKP, CLKN, CLKTYP)
The MAX12555 accepts both differential and singleended clock inputs. For single-ended clock input operation, connect CLKTYP to GND, CLKN to GND, and
drive CLKP with the external single-ended clock signal.
For differential clock input operation, connect CLKTYP
to OVDD or VDD, and drive CLKP and CLKN with the
external differential clock signal. To reduce clock jitter,
the external single-ended clock must have sharp falling
edges. Consider the clock input as an analog input and
route it away from any other analog inputs and digital
signal lines.
CLKP and CLKN are high impedance when the
MAX12555 is powered down (Figure 5).
Low clock jitter is required for the specified SNR performance of the MAX12555. Analog input sampling
occurs on the falling edge of the clock signal, requiring
this edge to have the lowest possible jitter. Jitter limits
the maximum SNR performance of any ADC according
to the following relationship:
⎛
⎞
1
SNR = 20 × log ⎜
⎟
⎝ 2 × π fIN × t J ⎠
where fIN represents the analog input frequency and tJ
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 72.1dB of SNR with a 175MHz
input frequency, the system must have less than 0.23ps
of clock jitter. In actuality, there are other noise sources
such as thermal noise and quantization noise that contribute to the system noise, requiring the clock jitter to
be less than 0.14ps to obtain the specified 72.1dB of
SNR at 175MHz.
16
DUTY-CYCLE
EQUALIZER
S2H
S1L
10kΩ
CLKN
10kΩ
S2L
GND
SWITCHES S1_ AND S2_ ARE OPEN
DURING POWER-DOWN, MAKING
CLKP AND CLKN HIGH IMPEDANCE.
SWITCHES S2_ ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
Figure 5. Simplified Clock Input Circuit
Clock Duty-Cycle Equalizer (DCE)
Connect DCE high to enable the clock duty-cycle
equalizer (DCE = OVDD or VDD). Connect DCE low to
disable the clock duty-cycle equalizer (DCE = GND).
With the clock duty-cycle equalizer enabled, the
MAX12555 is insensitive to the duty cycle of the signal
applied to CLKP and CLKN. Duty cycles from 35% to
65% are acceptable with the clock duty-cycle equalizer
enabled.
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the
MAX12555 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.
Although not recommended, disabling the clock dutycycle equalizer reduces the analog supply current by
1.6mA. With the clock duty-cycle equalizer disabled, the
MAX12555’s dynamic performance varies depending on
the duty cycle of the signal applied to CLKP and CLKN.
______________________________________________________________________________________
14-Bit, 95Msps, 3.3V ADC
N+5
N+3
N-3
N-2
N-1
N
N+1
MAX12555
N+4
DIFFERENTIAL ANALOG INPUT (INP–INN)
(VREFP - VREFN) x 2/3
N+6
N +2
N+7
N+9
N+8
(VREFN - VREFP) x 2/3
tAD
CLKN
CLKP
tDAV
tCL
tCH
DAV
tSETUP
D0–D11
tHOLD
N-3
8.0 CLOCK-CYCLE DATA LATENCY
N-2
N-1
N
N+1
N+2
N+3
N+4
N+5
tSETUP
N+6
N+7
N+8
N+9
tHOLD
DOR
Figure 6. System Timing Diagram
System-Timing Requirements
Figure 6 shows the relationship between the clock, analog inputs, DAV indicator, DOR indicator, and the resulting output data. The analog input is sampled on the
falling edge of the clock signal and the resulting data
appears at the digital outputs 8.0 clock cycles later.
The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end circuitry can be latched with the rising edge of the conversion clock (CLKP-CLKN).
Data-Valid Output (DAV)
DAV is a single-ended version of the input clock (CLKP)
with a delay (tDAV). Output data changes on the falling
edge of DAV, and DAV rises once output data is valid
(Figure 6).
The state of the duty-cycle equalizer input (DCE)
changes the waveform at DAV. With the duty-cycle
equalizer disabled (DCE = low), the DAV signal is a single-ended version of CLKP delayed by 5.2ns (tDAV).
With the duty-cycle equalizer enabled (DCE = high), the
DAV signal has a fixed pulse width that is independent of
CLKP. In either case, with DCE high or low, output data
at D13–D0 and DOR are valid from 5.5ns before the rising edge of DAV to 4.0ns after the rising edge of DAV,
and the falling edge of DAV is synchronized to have a
5.2ns (tDAV) delay from the falling edge of CLKP.
DAV is high impedance when the MAX12555 is in
power-down (PD = high). DAV is capable of sinking
and sourcing 600µA and has three times the drive
strength of D13–D0 and DOR. DAV is typically used to
latch the MAX12555 output data into an external backend digital circuit.
Keep the capacitive load on DAV as low as possible
(<25pF) to avoid large digital currents feeding back
into the analog portion of the MAX12555 and degrading
its dynamic performance. An external buffer on DAV
isolates it from heavy capacitive loads. Refer to the
MAX12555 evaluation kit schematic for an example of
DAV driving back-end digital circuitry through an external buffer.
______________________________________________________________________________________
17
MAX12555
14-Bit, 95Msps, 3.3V ADC
Data Out-of-Range Indicator (DOR)
The DOR digital output indicates when the analog input
voltage is out of range. When DOR is high, the analog
input is out of range. When DOR is low, the analog
input is within range. The valid differential input range is
from (VREFP - VREFN) x 3/4 to (VREFN - VREFP) x 3/4.
Signals outside this valid differential range cause DOR
to assert high as shown in Table 2 and Figure 6.
DOR is synchronized with DAV and transitions along
with the output data D13–D0. There is an 8.0 clockcycle latency in the DOR function as is with the output
data (Figure 6).
DOR is high impedance when the MAX12555 is in
power-down (PD = high). DOR enters a high-impedance state within 10ns after the rising edge of PD and
becomes active 10ns after PD’s falling edge.
Digital Output Data (D13–D0), Output Format (G/T)
The MAX12555 provides a 14-bit, parallel, tri-state output bus. D13–D0 and DOR update on the falling edge
of DAV and are valid on the rising edge of DAV.
The MAX12555 output data format is either Gray code
or two’s complement, depending on the logic input G/T.
With G/T high, the output data format is Gray code.
With G/T low, the output data format is two’s complement. See Figure 9 for a binary-to-Gray and Gray-tobinary code-conversion example.
The following equations, Table 2, Figure 7, and Figure 8
define the relationship between the digital output and
the analog input:
VINP − VINN = (VREFP − VREFN ) ×
for Gray code (G/T = 1).
18
4 CODE10 − 8192
×
3
16384
VINP − VINN = (VREFP − VREFN ) ×
4 CODE10
×
3
16384
for two’s complement (G/T = 0).
where CODE10 is the decimal equivalent of the digital
output code as shown in Table 2.
Digital outputs D13–D0 are high impedance when the
MAX12555 is in power-down (PD = high). D13–D0 transition high 10ns after the rising edge of PD and
become active 10ns after PD’s falling edge.
Keep the capacitive load on the MAX12555 digital outputs D13–D0 as low as possible (<15pF) to avoid large
digital currents feeding back into the analog portion of
the MAX12555 and degrading its dynamic performance. The addition of external digital buffers on the
digital outputs isolates the MAX12555 from heavy
capacitive loading. To improve the dynamic performance of the MAX12555, add 220Ω resistors in series
with the digital outputs close to the MAX12555. Refer to
the MAX12555 evaluation kit schematic for an example
of the digital outputs driving a digital buffer through
220Ω series resistors.
Power-Down Input (PD)
The MAX12555 has two power modes that are controlled with the power-down digital input (PD). With PD
low, the MAX12555 is in normal operating mode. With
PD high, the MAX12555 is in power-down mode.
The power-down mode allows the MAX12555 to efficiently use power by transitioning to a low-power state
when conversions are not required. Additionally, the
MAX12555 parallel output bus is high impedance in
power-down mode, allowing other devices on the bus
to be accessed.
______________________________________________________________________________________
______________________________________________________________________________________
DOR
1
0
0
0
0
0
0
0
0
0
1
BINARY
D13 D0
10 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0001
11 0000 0000 0011
11 0000 0000 0001
11 0000 0000 0000
01 0000 0000 0000
01 0000 0000 0001
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
0x0000
0x0000
0x0001
0x1001
0x1000
0x3000
0x3001
0x3003
0x2001
0x2000
0x2000
0
0
+1
+8190
+8191
+8192
+8193
+8194
+16382
+16383
+16383
DECIMAL
HEXADECIMAL
EQUIVALENT
EQUIVALENT
OF
OF
D13 D0
D13 D0
(CODE10)
GRAY-CODE
OUTPUT CODE
(G/T = 1)
10 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0001
11 1111 1111 1110
11 1111 1111 1111
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
01 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
BINARY
D13 D0
1
0
0
0
0
0
0
0
0
0
1
DOR
0x2000
0x2000
0x2001
0x3FFE
0x3FFF
0x0000
0x0001
0x0002
0x1FFE
0x1FFF
0x1FFF
-8192
-8192
-8191
-2
-1
0
+1
+2
+8190
+8191
+8191
DECIMAL
HEXADECIMAL
EQUIVALENT
EQUIVALENT
OF
OF
D13 D0
D13 D0
(CODE10)
TWO’S-COMPLEMENT
OUTPUT CODE
(G/T = 0)
(
<-1.024000V
(DATA OUT OF
RANGE)
-1.024000V
-1.023875V
-0.000250V
-0.000125V
+0.000000V
+0.000125V
+0.000250V
+1.023750V
+1.023875V
>+1.023875V
(DATA OUT OF
RANGE)
)
VINP - VINN
VREFP = 2.418V
VREFN = 0.882V
MAX12555
Table 2. Output Codes vs. Input Voltage
14-Bit, 95Msps, 3.3V ADC
19
1 LSB =
VREFP - VREFN 4
x
3
16384
(VREFP - VREFN) x 2/3
1 LSB =
(VREFP - VREFN) x 2/3
(VREFP - VREFN) x 2/3
0x2000
0x2001
0x2003
GRAY OUTPUT CODE (LSB)
0x1FFE
0x1FFD
0x0001
0x0000
0x3FFF
0x2003
0x2002
0x2001
0x2000
0x3001
0x3000
0x1000
0x0002
0x0003
0x0001
0x0000
-8191 -8189
-1
0 +1
+8189 +8191
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 7. Two’s-Complement Transfer Function (G/T = 0)
In power-down mode, all internal circuits are off, the
analog supply current reduces to 0.1mA, and the digital supply current reduces to 0.008mA. The following
list shows the state of the analog inputs and digital outputs in power-down mode:
• INP, INN analog inputs are disconnected from the
internal input amplifier (Figure 3).
• REFOUT has approximately 17kΩ to GND.
• REFP, COM, REFN go high impedance with respect
to VDD and GND, but there is an internal 4kΩ resistor
between REFP and COM, as well as an internal 4kΩ
resistor between REFN and COM.
• D13–D0, DOR, and DAV go high impedance.
• CLKP, CLKN go high impedance (Figure 5).
The wake-up time from power-down mode is dominated by the time required to charge the capacitors at
REFP, REFN, and COM. In internal reference mode and
buffered external reference mode, the wake-up time is
typically 10ms with the recommended capacitor array
(Figure 13). When operating in unbuffered external reference mode, the wake-up time is dependent on the
external reference drivers.
20
VREFP - VREFN 4
x
3
16384
(VREFP - VREFN) x 2/3
0x1FFF
TWO'S-COMPLEMENT OUTPUT CODE (LSB)
MAX12555
14-Bit, 95Msps, 3.3V ADC
-8191 -8189
-1 0 +1
+8189 +8191
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 8. Gray-Code Transfer Function (G/T = 1)
Applications Information
Using Transformer Coupling
In general, the MAX12555 provides better SFDR and
THD performance with fully differential input signals as
opposed to single-ended input drive. In differential
input mode, even-order harmonics are lower as both
inputs are balanced, and each of the ADC inputs only
requires half the signal swing compared to singleended input mode.
An RF transformer (Figure 10) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX12555
for optimum performance. Connecting the center tap of
the transformer to COM provides a VDD / 2 DC level
shift to the input. Although a 1:1 transformer is shown, a
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
overall distortion. The configuration of Figure 10 is good
for frequencies up to Nyquist (fCLK / 2).
The circuit of Figure 11 converts a single-ended input
signal to fully differential just as Figure 10. However,
Figure 11 utilizes an additional transformer to improve
the common-mode rejection, allowing high-frequency
______________________________________________________________________________________
14-Bit, 95Msps, 3.3V ADC
GRAY-TO-BINARY-CODE CONVERSION
1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME
AS THE MOST SIGNIFICANT GRAY-CODE BIT.
1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.
D13
D11
D7
D3
0 1
1 0 1 1
0 1 0 0
1 1 0 0
D0
0
BIT POSITION
BINARY
D13
D11
D7
D3
0 1
0 1 1 0
1 1 1 0
1 0 1 0
GRAY CODE
0
WHERE
IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION.
0
1
BINARY
BINARY13
BINARY12 = BINARY13
BINARY12 = 0
1
GRAY12
BINARY12 = 1
D13
1
BIT POSITION
GRAY CODE
WHERE
IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION.
GRAY12 = 1
0
D0
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
BINARYX = BINARYX+1
GRAYX
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
GRAYX = BINARYX
BINARYX+1
GRAY12 = BINARY12
GRAY12 = 1
0
MAX12555
BINARY-TO-GRAY-CODE CONVERSION
D11
D7
D3
1 0 1 1
0 1 0 0
1 1 0 0
D0
BIT POSITION
D13
BINARY
0
1
GRAY CODE
0
1
D7
D3
0 1 1 0
1 1 1 0
1 0 1 0
D0
BIT POSITION
GRAY CODE
BINARY
3) REPEAT STEP 2 UNTIL COMPLETE.
3) REPEAT STEP 2 UNTIL COMPLETE.
GRAY11 = BINARY11
GRAY11 = 1
1
D11
BINARY12
BINARY11 = BINARY12
BINARY11 = 1
0
GRAY11 = 0
GRAY11
BINARY11 = 1
D13
D11
D7
D3
0 1
1 0 1 1
0 1 0 0
1 1 0 0
0 1
0
D0
D13
D11
D7
D3
BINARY
0 1
0 1 1 0
1 1 1 0
1 0 1 0
GRAY CODE
0 1
1
BIT POSITION
D0
BIT POSITION
GRAY CODE
BINARY
4) THE FINAL GRAY-CODE CONVERSION IS:
4) THE FINAL GRAY-CODE CONVERSION IS:
BIT POSITION
D13
D11
D7
D3
1 1 0 0
BINARY
0 1
0 1 1 0
1 1 1 0
1 0 1 0
GRAY CODE
1 0 1 0
GRAY CODE
0 1
1 0 1 1
0 1 0 0
1 1 0 0
BINARY
D13
D11
D7
D3
0 1
1 0 1 1
0 1 0 0
0 1
0 1 1 0
1 1 1 0
D0
D0
BIT POSITION
EXCULSIVE OR TRUTH TABLE
A
0
0
1
1
B
0
1
0
1
Y=A
B
0
1
1
0
Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion
______________________________________________________________________________________
21
MAX12555
14-Bit, 95Msps, 3.3V ADC
MAX4108
VIN
24.9Ω
T1
N.C.
2
INP
12pF
6
1
VIN
0.1µF
INP
0.1µF
5.6pF
MAX12555
5
100Ω
24.9Ω
MAX12555
COM
COM
2.2µF
3
4
MINI-CIRCUITS
TT1-6 OR T1-1T
2.2µF
100Ω
24.9Ω
24.9Ω
INN
INN
12pF
5.6pF
Figure 12. Single-Ended, AC-Coupled Input Drive
Figure 10. Transformer-Coupled Input Drive for Input
Frequencies Up to Nyquist
0Ω*
INP
0.1µF
6
1
VIN
75Ω
0.5%
T1
N.C.
2
5
75Ω
0.5%
2
5
3
4
MINI-CIRCUITS
ADT1-1WT
5.6pF
110Ω
0.1%
T2
N.C.
3
4
MINI-CIRCUITS
ADT1-1WT
6
1
MAX12555
COM
N.C.
110Ω
0.1%
2.2µF
0Ω*
INN
5.6pF
*0Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE
RESISTORS TO LIMIT THE BANDWIDTH.
Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
signals beyond the Nyquist frequency. The two sets of
termination resistors provide an equivalent 50Ω termination to the signal source. The second set of termination resistors connects to COM, providing the correct
input common-mode voltage. Two 0Ω resistors in series
with the analog inputs allow high IF input frequencies.
These 0Ω resistors can be replaced with low-value
resistors to limit the input bandwidth.
22
Single-Ended, AC-Coupled Input Signal
Figure 12 shows an AC-coupled, single-ended input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity.
______________________________________________________________________________________
14-Bit, 95Msps, 3.3V ADC
MAX12555
+3.3V
0.1µF
2.2µF
0.1µF
+3.3V
1
2
VDD
MAX6029EUK21
38
0.1µF
5
REFP
1
REFOUT
0.1µF
1µF*
2.048V
MAX12555
NOTE: ONE FRONT-END REFERENCE
CIRCUIT IS CAPABLE OF SOURCING 15mA
AND SINKING 30mA OF OUTPUT CURRENT.
0.1µF
REFN
0.1µF
39
5
1µF
MAX4230
4
3
2
+3.3V
16.2kΩ
1
10µF
3
REFIN
GND
COM
2.2µF
2.048V
47Ω
+3.3V
2
10µF
6V
330µF
6V
0.1µF
2.2µF
0.1µF
1.47kΩ
VDD
38
*PLACE THE 1µF REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
REFP
1
REFOUT
0.1µF
1µF*
10µF
MAX12555
REFN
2
0.1µF
39
3
REFIN
GND
COM
2.2µF
Figure 13. External Buffered Reference Driving Multiple ADCs
Buffered External Reference
Drives Multiple ADCs
The buffered external reference mode allows for more
control over the MAX12555 reference voltage and
allows multiple converters to use a common reference.
The REFIN input impedance is >50MΩ.
Figure 13 uses the MAX6029EUK21 precision 2.048V
reference as a common reference for multiple converters. The 2.048V output of the MAX6029 passes through
a one-pole 10Hz lowpass filter to the MAX4230. The
MAX4230 buffers the 2.048V reference and provides
additional 10Hz lowpass filtering before its output is
applied to the REFIN input of the MAX12555.
______________________________________________________________________________________
23
MAX12555
14-Bit, 95Msps, 3.3V ADC
+3.3V
1
0.1µF
MAX6029EUK30
2
+3.3V
5
0.1µF
+3.3V
2.2µF
3.000V
0.1µF
0.1µF
1
5
20kΩ
1%
MAX4230
47Ω
4
3
20kΩ
1%
2.413V
1
REFOUT
2
10µF
6V
330µF
6V
10µF
0.1µF
1.47kΩ
+3.3V
0.1µF
MAX12555
REFN
0.1µF
52.3kΩ
1%
1
5
3
2
10µF
6V
20kΩ
1%
COM
REFIN
GND
39
2.2µF
+3.3V
330µF
6V
2.2µF
0.1µF
20kΩ
1%
20kΩ
1%
1.647V
47Ω
4
52.3kΩ
1%
3
MAX4230
38
1µF*
2
0.47µF
VDD
REFP
0.1µF
1.47kΩ
0.1µF
+3.3V
1
1
5
3
REFOUT
MAX4230
4
38
0.880V
10µF
47Ω
0.1µF
1µF*
MAX12555
2
2
VDD
REFP
10µF
6V
330µF
6V
3
1.47kΩ
*PLACE THE 1µF REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE.
REFN
0.1µF
COM
GND
REFIN
39
2.2µF
Figure 14. External Unbuffered Reference Driving Multiple ADCs
Unbuffered External
Reference Drives Multiple ADCs
The unbuffered external reference mode allows for precise control over the MAX12555 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven
directly by a set of external reference sources.
24
Figure 14 uses the MAX6029EUK30 precision 3.000V
reference as a common reference for multiple converters. A seven-component resistive divider chain follows
the MAX6029 voltage reference. The 0.47µF capacitor
along this chain creates a 10Hz lowpass filter. Three
MAX4230 operational amplifiers buffer taps along this
resistor chain providing 2.413V, 1.647V, and 0.880V to
the MAX12555’s REFP, COM, REFN reference inputs,
______________________________________________________________________________________
14-Bit, 95Msps, 3.3V ADC
Grounding, Bypassing, and
Board Layout
The MAX12555 requires high-speed board layout
design techniques. Refer to the MAX12555 evaluation
kit data sheet for a board layout reference. Locate all
bypass capacitors as close to the device as possible,
preferably on the same side of the board as the ADC,
using surface-mount devices for minimum inductance.
Bypass VDD to GND with a 0.1µF ceramic capacitor in
parallel with a 2.2µF ceramic capacitor. Bypass OVDD
to GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF ceramic capacitor.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. All
MAX12555 GNDs and the exposed back-side paddle
must be connected to the same ground plane. The
MAX12555 relies on the exposed back-side paddle
connection for a low-inductance ground connection.
Use multiple vias to connect the top-side ground to the
bottom-side ground. Isolate the ground plane from any
noisy digital system ground planes such as a DSP or
output buffer ground.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.
Ensure that the differential analog input network layout
is symmetric and that all parasitics are balanced equally. Refer to the MAX12555 evaluation kit data sheet for
an example of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For the
MAX12555, this straight line is between the end points
of the transfer function, once offset and gain errors have
been nullified. INL deviations are measured at every
step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. For
the MAX12555, DNL deviations are measured at every
step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally the midscale
MAX12555 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. The slope of the actual
transfer function is measured between two data points:
positive full scale and negative full scale. Ideally, the
positive full-scale MAX12555 transition occurs at 1.5
LSBs below positive full scale, and the negative fullscale transition occurs at 0.5 LSB above negative full
scale. The gain error is the difference of the measured
transition points minus the difference of the ideal transition points.
Small-Signal Noise Floor (SSNF)
Small-signal noise floor is the integrated noise and distortion power in the Nyquist band for small-signal
inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a
single tone with an amplitude less than -35dBFS. This
parameter captures the thermal and quantization noise
characteristics of the converter and is used to help calculate the overall noise figure of a receive channel. Go
to www.maxim-ic.com for application notes on thermal
+ quantization noise floor.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR[max] = 6.02 x N + 1.76
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the
______________________________________________________________________________________
25
MAX12555
respectively. The feedback around the MAX4230 op
amps provides additional 10Hz lowpass filtering. The
2.413V and 0.880V reference voltages set the full-scale
analog input range to ±1.022V = ±(VREFP - VREFN) x 2/3.
A common power source for all active components
removes any concern regarding power-supply
sequencing when powering up or down.
MAX12555
14-Bit, 95Msps, 3.3V ADC
fundamental, the first six harmonics (HD2–HD7), and
the DC offset:
⎛ SIGNALRMS ⎞
SNR = 20 × log ⎜
⎟
⎝ NOISERMS ⎠
⎛
VIM12 + VIM22 + ....... + VIM132 + VIM14 2
IMD = 20 × log ⎜
⎜
V12 + V22
⎝
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus the RMS distortion. RMS
noise includes all spectral components to the Nyquist
frequency excluding the fundamental, the first six harmonics (HD2–HD7), and the DC offset. RMS distortion
includes the first six harmonics (HD2–HD7):
⎛
SIGNALRMS
SINAD = 20 × log ⎜
⎜
2
2
⎝ NOISERMS + DISTORTIONRMS
⎞
⎟
⎟
⎠
ENOB specifies the dynamic performance of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
The fundamental input tone amplitudes (V1 and V2) are
at -7dBFS. Fourteen intermodulation products (VIM_)
are used in the MAX12555 IMD calculation. The intermodulation products are the amplitudes of the output
spectrum at the following frequencies, where fIN1 and
fIN2 are the fundamental input tone frequencies:
• Second-order intermodulation products:
fIN1 + fIN2, fIN2 - fIN1
• Fourth-order intermodulation products:
3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1
• Fifth-order intermodulation products:
3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x
fIN2, 3 x fIN2 + 2 x fIN1
Third-Order Intermodulation (IM3)
⎛ SINAD − 1.76 ⎞
ENOB = ⎜
⎟
⎝
⎠
6.02
Single-Tone Spurious-Free
Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next-largest spurious
component, excluding DC offset.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is
expressed as:
⎞
⎟
⎟
⎟⎟
⎠
where V1 is the fundamental amplitude, and V2 through
V7 are the amplitudes of the 2nd- through 7th-order
harmonics (HD2–HD7).
26
⎞
⎟
⎟
⎠
• Third-order intermodulation products:
2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1
Effective Number of Bits (ENOB)
⎛
2
2
2
2
2
2
⎜ V2 + V3 + V4 + V5 + V6 + V7
THD = 20 × log ⎜
V1
⎜⎜
⎝
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
IM3 is the total power of the third-order intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones fIN1 and fIN2. The
individual input tone levels are at -7dBFS. The thirdorder intermodulation products are 2 x fIN1 - fIN2, 2 x
fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1.
Two-Tone Spurious-Free Dynamic Range
(SFDRTT)
SFDRTT represents the ratio, expressed in decibels, of
the RMS amplitude of either input tone to the RMS
amplitude of the next-largest spurious component in the
spectrum, excluding DC offset. This spurious component can occur anywhere in the spectrum up to Nyquist
and is usually an intermodulation product or a harmonic.
Aperture Delay
The MAX12555 samples data on the falling edge of its
sampling clock. In actuality, there is a small delay
between the falling edge of the sampling clock and the
actual sampling instant. Aperture delay (tAD) is the
time defined between the falling edge of the sampling
clock and the instant when an actual sample is taken
(Figure 4).
______________________________________________________________________________________
14-Bit, 95Msps, 3.3V ADC
D1
D0
DAV
OVDD
GND
VDD
PD
REFIN
REFP
1
30
D2
REFN
2
29
D3
COM
3
28
D4
GND
4
27
D5
INP
5
26
D6
MAX12555
INN
6
25
D7
GND
7
24
D8
DCE
8
23
D9
CLKN
9
22
D10
CLKP
10
21
D11
EXPOSED PADDLE (GND)
D12
D13
DOR
OVDD
GND
VDD
VDD
11 12 13 14 15 16 17 18 19 20
CLKTYP
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX12555 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by ±10%.
40 39 38 37 36 35 34 33 32 31
VDD
Overdrive Recovery Time
G/T
The output noise (nOUT) parameter is similar to the thermal + quantization noise parameter and is an indication
of the ADC’s overall noise performance.
No fundamental input tone is used to test for nOUT;
INP, INN, and COM are connected together and 1024k
data points collected. nOUT is computed by taking the
RMS value of the collected data points after the mean
is removed.
TOP VIEW
VDD
Output Noise (nOUT)
REFOUT
Pin Configuration
THIN QFN
6mm x 6mm x 0.8mm
______________________________________________________________________________________
27
MAX12555
Aperture Jitter
Figure 4 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN 6x6x0.8.EPS
MAX12555
14-Bit, 95Msps, 3.3V ADC
D2
D
CL
D/2
b
D2/2
k
E/2
E2/2
(NE-1) X e
E
CL
E2
k
e
L
(ND-1) X e
e
L
CL
CL
L1
L
L
e
A1
A2
e
A
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
1
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.