MAXIM MAX5048BAUTTG16

MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
General Description
The MAX5048A/MAX5048B are high-speed MOSFET
drivers capable of sinking/sourcing 7.6A/1.3A peak currents. These devices take logic input signals and drive
a large external MOSFET. The MAX5048A/MAX5048B
have inverting and noninverting inputs that give the
user greater flexibility in controlling the MOSFET. They
feature two separate outputs working in complementary
mode, offering flexibility in controlling both turn-on and
turn-off switching speeds.
The MAX5048A/MAX5048B have internal logic circuitry,
which prevents shoot-through during output state
changes. The logic inputs are protected against voltage spikes up to +14V, regardless of V+ voltage.
Propagation delay time is minimized and matched
between the inverting and noninverting inputs. The
MAX5048A/MAX5048B have very fast switching times
combined with very short propagation delays (12ns
typ), making them ideal for high-frequency circuits.
The MAX5048A/MAX5048B operate from a +4V to +12.6V
single power supply and typically consume 0.95mA of
supply current. The MAX5048A has CMOS input logic
levels, while the MAX5048B has standard TTL input logic
levels. These devices are available in space-saving
6-pin SOT23 and TDFN packages.
Applications
Features
o Independent Source-and-Sink Outputs for
Controllable Rise and Fall Times
o +4V to +12.6V Single Power Supply
o 7.6A/1.3A Peak Sink/Source Drive Current
o 0.23Ω Open-Drain n-Channel Sink Output
o 2Ω Open-Drain p-Channel Source Output
o 12ns (typ) Propagation Delay
o Matching Delay Time Between Inverting and
Noninverting Inputs
o VCC/2 CMOS (MAX5048A)/TTL (MAX5048B) Logic
Inputs
o 1.6V Input Hysteresis
o Up to +14V Logic Inputs (Regardless of V+
Voltage)
o Low Input Capacitance: 2.5pF (typ)
o -40°C to +125°C Operating Temperature Range
o 6-Pin SOT23 and TDFN Packages
Ordering Information
PART
TEMP RANGE
PINLOGIC TOP
PACKAGE INPUT MARK
Power MOSFET Switching
VCC/2
ABEC
CMOS
MAX5048AAUT-T -40°C to +125°C 6 SOT23
Switch-Mode Power Supplies
MAX5048BAUT-T -40°C to +125°C 6 SOT23
TTL ABED
VCC/2
MAX5048AATT-T -40°C to +125°C 6 TDFN-EP*
AKV
CMOS
MAX5048BATT-T -40°C to +125°C 6 TDFN-EP* TTL AKW
Ordering Information continued at end of data sheet.
DC-DC Converters
Motor Control
Power-Supply Modules
Pin Configurations
Typical Operating Circuit
TOP VIEW
V+
+
P_OUT
V+
V+ 1
MAX5048A
MAX5048B
N_OUT
IN+
P_OUT 2
N
MAX5048A
MAX5048B
N_OUT 3
IN-
6
IN+
5
IN-
4
GND
GND
SOT23
Pin Configurations continued at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-2419; Rev 5; 11/12
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND
V+ ...........................................................................-0.3V to +13V
IN+, IN-...................................................................-0.3V to +14V
N_OUT, P_OUT ............................................-0.3V to (V+ + 0.3V)
N_OUT Continuous Output Current (Note 1) ....................390mA
P_OUT Continuous Output Current (Note 1).....................100mA
Continuous Power Dissipation* (TA = +70°C)
6-Pin SOT23 (derate 9.1mW/°C above +70°C)............727mW
6-Pin TDFN (derate 18.2mW/°C above +70°C) .........1454mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: Continuous output current is limited by the power dissipation of the package.
*As per JEDEC51 standard.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 2)
SOT23
Junction-to-Case Thermal Resistance (θJC)......................75°C/W
TDFN
Junction-to-Case Thermal Resistance (θJC).......................8.5°C/W
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V+ = +12V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12.6
V
3.6
4.00
V
POWER SUPPLY
V+ Operating Range
V+ Undervoltage Lockout
V+
UVLO
4.0
V+ rising
3.25
V+ Undervoltage Lockout
Hysteresis
V+ Undervoltage Lockout to
Output Delay Time
V+ Supply Current
I+
400
mV
V+ rising
300
ns
IN+ = IN- = V+
0.95
1.5
TA = +25°C
0.23
0.26
TA = +125°C
0.38
0.43
TA = +25°C
0.24
0.28
TA = +125°C
0.40
0.47
VV+ = +10V,
IN-OUT = -100mA
TA = +25°C
0.31
0.34
TA = +125°C
0.46
0.51
VV+ = +4.5V,
IN-OUT = -100mA
TA = +25°C
0.32
0.36
TA = +125°C
0.48
0.55
mA
n-CHANNEL OUTPUT
Driver Output Resistance—
Pulling Down (MAX5048AAUT/
MAX5048BAUT)
Driver Output Resistance—
Pulling Down (MAX5048AATT/
MAX5048BATT)
2
RON-N
RON-N
VV+ = +10V,
IN-OUT = -100mA
VV+ = +4.5V,
IN-OUT = -100mA
Ω
Ω
Maxim Integrated
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power-Off Pulldown Resistance
V+ = 0 or unconnected, IN-OUT = -10mA,
TA = +25°C
3.3
10
Ω
Power-Off Pulldown Clamp
Voltage
V+ = 0 or unconnected, IN-OUT = -10mA,
TA = +25°C
0.85
1.0
V
20
µA
Output Leakage Current
ILK-N
N_OUT = V+
6.85
Peak Output Current (Sinking)
IPK-N
CL = 10,000pF
7.6
A
p-CHANNEL OUTPUT
Driver Output Resistance—
Pulling Up (MAX5048AAUT/
MAX5048BAUT)
Driver Output Resistance—
Pulling Up (MAX5048AATT/
MAX5048BATT)
RON-P
RON-P
VV+ = +10V,
IP-OUT = 50mA
TA = +25°C
2.00
3.00
TA = +125°C
2.85
4.30
VV+ = +4.5V,
IP-OUT = 50mA
TA = +25°C
2.20
3.30
TA = +125°C
3.10
4.70
VV+ = +10V,
IP-OUT = 50mA
TA = +25°C
2.08
3.08
TA = +125°C
2.93
4.38
VV+ = +4.5V,
IP-OUT = 50mA
TA = +25°C
2.28
3.38
TA = +125°C
3.18
4.78
0.001
10
Output Leakage Current
ILK-P
P_OUT = 0
Peak Output Current (Sourcing)
IPK-P
CL = 10,000pF
1.3
Ω
Ω
µA
A
LOGIC INPUT
Logic 1 Input Voltage
VIH
Logic 0 Input Voltage
VIL
Logic-Input Hysteresis
VHYS
Logic-Input Current
Input Capacitance
MAX5048A
MAX5048B
0.67 x V+
V
2.4
MAX5048A
0.33 x V+
MAX5048B
0.8
MAX5048A
1.6
MAX5048B
0.68
VIN_ = V+ or 0
0.001
CIN
V
V
10
2.5
µA
pF
SWITCHING CHARACTERISTICS FOR V+ = +10V
Rise Time
Fall Time
tR
tF
CL = 1000pF
8
CL = 5000pF
45
CL = 10,000pF
82
CL = 1000pF
3.2
CL = 5000pF
7.5
CL = 10,000pF
ns
ns
12.5
Turn-On Propagation Delay Time
tD-ON
Figure 1, CL = 1000pF (Note 4)
7
12
25
ns
Turn-Off Propagation Delay Time
tD-OFF
Figure 1, CL = 1000pF (Note 4)
7
12
25
ns
Break-Before-Make Time
Maxim Integrated
2.5
ns
3
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS FOR V+ = +4.5V
Rise Time
tR
Fall Time
tF
CL = 1000pF
12
CL = 5000pF
41
CL = 10,000pF
74
CL = 1000pF
3.0
CL = 5000pF
7.0
CL = 10,000pF
ns
ns
11.3
Turn-On Propagation Delay Time
tD-ON
Figure 1, CL = 1000pF (Note 4)
8
14
27
ns
Turn-Off Propagation Delay Time
tD-OFF
Figure 1, CL = 1000pF (Note 4)
8
14
27
ns
Break-Before-Make Time
4.2
ns
Note 3: All DC specifications are 100% tested at TA = +25°C. Specifications over -40°C to +125°C are guaranteed by design.
Note 4: Guaranteed by design, not production tested.
Typical Operating Characteristics
(CL = 1000pF, TA = +25°C, unless otherwise noted.)
TA = 0°C
TA = +25°C
TA = -40°C
11
4.5
4.0
TA = +25°C TA = 0°C
TA = -40°C
3.5
3.0
8
TA = +125°C
PROPAGATION DELAY (ns)
5.0
TA = +85°C
14
5.5
20
MAX5048 toc02
TA = +125°C
TA = +85°C
TA = +125°C
FALL TIME (ns)
RISE TIME (ns)
17
6.0
MAX5048 toc01
20
PROPAGATION DELAY TIME, LOW-TO-HIGH
vs. SUPPLY VOLTAGE
FALL TIME vs. SUPPLY VOLTAGE
MAX5048 toc03
RISE TIME vs. SUPPLY VOLTAGE
18
TA = +85°C
TA = +25°C
TA = -40°C
TA = 0°C
16
14
12
2.5
5
6
8
SUPPLY VOLTAGE (V)
4
10
2.0
4
10
12
4
6
8
SUPPLY VOLTAGE (V)
10
12
4
6
8
10
12
SUPPLY VOLTAGE (V)
Maxim Integrated
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Typical Operating Characteristics (continued)
(CL = 1000pF, TA = +25°C, unless otherwise noted.)
16
TA = +25°C
TA = 0°C TA = -40°C
14
1MHz
6
500kHz
4
100kHz
12
6
8
12
10
2.5
2.0
1.5
0.5
0
4
3.0
1.0
75kHz 40kHz
2
10
0
4
6
8
10
12
0
400
800
1200
1600
2000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT vs. TEMPERATURE
MAX5048A
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX5048A
SUPPLY CURRENT vs. INPUT VOLTAGE
1.5
1.4
1.3
7
6
RISING
5
4
3
FALLING
2
-25
0
25
50
75
TEMPERATURE (°C)
Maxim Integrated
100
125
INPUT
LOW-TO-HIGH
1.5
1.4
1.3
1.2
1.1
0.9
0.8
0
-50
INPUT
HIGH-TO-LOW
1.6
1.0
1
1.2
1.7
SUPPLY CURRENT (mA)
1.6
1.8
MAX5048 toc08
1.7
8
INPUT THRESHOLD VOLTAGE (V)
V+ = +10V
f = 100kHz, CL = 0
DUTY CYCLE = 50%
MAX5048 toc09
SUPPLY VOLTAGE (V)
MAX5048 toc07
SUPPLY VOLTAGE (V)
1.8
SUPPLY CURRENT (mA)
8
V+ = +10V
f = 100kHz
DUTY CYCLE = 50%
3.5
SUPPLY CURRENT (mA)
TA = +85°C
DUTY CYCLE = 50%
V+ = +10V, CL = 0
10
SUPPLY CURRENT vs. LOAD CAPACITANCE
4.0
MAX5048 toc05
MAX5048 toc04
TA = +125°C
18
SUPPLY CURRENT vs. SUPPLY VOLTAGE
12
SUPPLY CURRENT (mA)
PROPAGATION DELAY (ns)
20
MAX5048 toc06
PROPAGATION DELAY TIME, HIGH-TO-LOW
vs. SUPPLY VOLTAGE
4
6
8
SUPPLY VOLTAGE (V)
10
12
0
2
4
6
8
10
12
INPUT VOLTAGE (V)
5
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Typical Operating Characteristics (continued)
(CL = 1000pF, TA = +25°C, unless otherwise noted.)
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 5000pF)
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 10,000pF)
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 5000pF)
MAX5048 toc10
MAX5048 toc11
MAX5048 toc12
IN+
2V/div
IN+
2V/div
IN+
2V/div
OUTPUT
2V/div
OUTPUT
2V/div
OUTPUT
2V/div
20ns/div
20ns/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, CL = 10,000pF)
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +12V, CL = 5000pF)
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +12V, CL = 10,000pF)
MAX5048 toc13
MAX5048 toc15
MAX5048 toc14
IN+
5V/div
IN+
5V/div
OUTPUT
5V/div
OUTPUT
5V/div
IN+
2V/div
OUTPUT
2V/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +12V, CL = 5000pF)
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +12V, CL = 10,000pF)
MAX5048 toc16
MAX5048 toc17
20ns/div
6
20ns/div
20ns/div
IN+
5V/div
IN+
5V/div
OUTPUT
5V/div
OUTPUT
5V/div
20ns/div
Maxim Integrated
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Pin Description
PIN
NAME
1
V+
2
P_OUT
p-Channel Open-Drain Output. Sources
current for MOSFET turn-on.
3
N_OUT
n-Channel Open-Drain Output. Sinks
current for MOSFET turn-off.
4
GND
5
IN-
Inverting Logic Input Terminal. Connect
to GND when not used.
6
IN+
Noninverting Logic Input Terminal.
Connect to V+ when not used.
EP
Exposed paddle. Connect to GND.
Solder EP to the GND plane for
improved thermal performance.
—
FUNCTION
Power Supply. Bypass to GND with a
0.1µF ceramic capacitor.
Ground
Detailed Description
Logic Inputs
The MAX5048A/MAX5048Bs’ logic inputs are protected
against voltage spikes up to +14V, regardless of the V+
voltage. The low 2.5pF input capacitance of the inputs
reduces loading and increases switching speed. These
devices have two inputs that give the user greater flexibility in controlling the MOSFET. Table 1 shows all possible input combinations.
The difference between the MAX5048A and the
MAX5048B is the input threshold voltage. The
MAX5048A has VCC/2 CMOS logic-level thresholds,
while the MAX5048B has TTL logic-level thresholds (see
the Electrical Characteristics). For V+ above 5.5V, VIH
(typ) = 0.5x(V+) + 0.8V and VIL (typ) = 0.5x(V+) - 0.8V.
As V+ is reduced from 5.5V to 4V, VIH and VIL gradually
approach VIH (typ) = 0.5x(V+) + 0.65V and VIL (typ) =
0.5x(V+) - 0.65V. Connect IN+ to V+ or IN- to GND
when not used. Alternatively, the unused input can be
used as an ON/OFF pin (see Table 1).
Table 1. Truth Table
IN+
IN-
p-CHANNEL
n-CHANNEL
L
L
OFF
ON
L
H
OFF
ON
H
L
ON
OFF
H
H
OFF
ON
L = Logic low
H = Logic high
Maxim Integrated
Undervoltage Lockout (UVLO)
When V+ is below the UVLO threshold, the N-channel
is ON and the P-channel is OFF, independent of the
state of the inputs. The UVLO is typically 3.6V with
400mV typical hysteresis to avoid chattering.
Driver Outputs
The MAX5048A/MAX5048B provide two separate outputs. One is an open-drain P-channel, the other an
open-drain N-channel. They have distinct current sourcing/sinking capabilities to independently control the rise
and fall times of the MOSFET gate. Add a resistor in
series with P_OUT/N_OUT to slow the corresponding
rise/fall time of the MOSFET gate.
Applications Information
Supply Bypassing, Device Grounding,
and Placement
Ample supply bypassing and device grounding are
extremely important because when large external
capacitive loads are driven, the peak current at the V+
pin can approach 1.3A, while at the GND pin the peak
current can approach 7.6A. VCC drops and ground
shifts are forms of negative feedback for inverters and, if
excessive, can cause multiple switching when the INinput is used and the input slew rate is low. The device
driving the input should be referenced to the
MAX5048A/MAX5048B GND pin especially when the INinput is used. Ground shifts due to insufficient device
grounding may disturb other circuits sharing the same
AC ground return path. Any series inductance in the V+,
P_OUT, N_OUT and/or GND paths can cause oscillations due to the very high di/dt that results when the
MAX5048A/MAX5048B are switched with any capacitive
load. A 0.1µF or larger value ceramic capacitor is recommended bypassing V+ to GND and placed as close
to the pins as possible. When driving very large loads
(e.g., 10nF) at minimum rise time, 10µF or more of parallel storage capacitance is recommended. A ground
plane is highly recommended to minimize ground return
resistance and series inductance. Care should be taken
to place the MAX5048A/MAX5048B as close as possible to the external MOSFET being driven to further minimize board inductance and AC path resistance.
Power Dissipation
Power dissipation of the MAX5048A/MAX5048B consists of three components, caused by the quiescent
current, capacitive charge and discharge of internal
nodes, and the output current (either capacitive or
resistive load). The sum of these components must be
kept below the maximum power-dissipation limit.
7
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
IN+
VIH
VIL
P_OUT AND
N_OUT
TIED
TOGETHER
90%
10%
tD–OFF
tF
tD–ON
tR
TIMING DIAGRAM
V+
V+
MAX5048A
MAX5048B
INPUT
P_OUT
IN+
OUTPUT
N_OUT
IN-
GND
CL
TEST CIRCUIT
Figure 1. Timing Diagram and Test Circuit
The quiescent current is 0.95mA typical. The current
required to charge and discharge the internal nodes is
frequency dependent (see the Typical Operating
Characteristics). The MAX5048A/MAX5048B power dissipation when driving a ground referenced resistive
load is:
P = D x RON(MAX) x ILOAD2
where D is the fraction of the period the MAX5048A/
MAX5048Bs’ output pulls high, RON (MAX) is the maximum on-resistance of the device with the output high
(P-channel), and ILOAD is the output load current of the
MAX5048A/MAX5048B.
For capacitive loads, the power dissipation is:
P = CLOAD x (V+)2 x FREQ
where CLOAD is the capacitive load, V+ is the supply
voltage, and FREQ is the switching frequency.
Layout Information
The MOSFET drivers MAX5048A/MAX5048B sourceand-sink large currents to create very fast rise and fall
edges at the gate of the switching MOSFET. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. The
following PCB layout guidelines are recommended
when designing with the MAX5048A/MAX5048B:
8
• Place one or more 0.1µF decoupling ceramic capacitor(s) from V+ to GND as close to the device as possible. At least one storage capacitor of 10µF (min)
should be located on the PC board with a low resistance path to the V+ pin of the MAX5048A/MAX5048B.
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from
gate to source when the gate is being pulled low.
The active current loop is from N_OUT of the
MAX5048A/MAX5048B to the MOSFET gate to the
MOSFET source and to GND of the MAX5048A/
MAX5048B. When the gate of the MOSFET is being
pulled high, the active current loop is from P_OUT of
the MAX5048A/MAX5048B to the MOSFET gate to
the MOSFET source to the GND terminal of the
decoupling capacitor to the V+ terminal of the
decoupling capacitor and to the V+ terminal of the
MAX5048A/MAX5048B. While the charging current
loop is important, the discharging current loop is critical. It is important to minimize the physical distance
and the impedance in these AC current paths.
• In a multilayer PCB, the component surface layer
surrounding the MAX5048A/MAX5048B should consist of a GND plane containing the discharging and
charging current loops.
Maxim Integrated
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
VS
V+
MAX5048A
MAX5048B
V+
(4V TO 12.6V)
P
BREAKBEFOREMAKE
CONTROL
IN-
P_OUT
MAX5048A
MAX5048B
N_OUT
N_OUT
IN+
N
IN+
P_OUT
V+
IN-
GND
Figure 2. MAX5048A/MAX5048B Functional Diagram
GND
Figure 3. Noninverting Application
4V TO 12V
VS
IN+
V+
P_OUT
P
MAX5048A/
MAX5048B
V+
(4V TO 12.6V)
N_OUT
P_OUT
V+
MAX5048A
MAX5048B
FROM PWM
CONTROLLER
(BOOST)
N_OUT
IN+
IN-
VOUT
GND
FROM PWM
CONTROLLER
(BUCK)
VOUT
IN+
V+
P_OUT
MAX5048A
MAX5048B
INGND
N_OUT
N
INGND
Figure 4. Boost Converter
Maxim Integrated
Figure 5. MAX5048A/MAX5048B in High-Power Synchronous
Buck Converter
9
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Pin Configurations (continued)
Ordering Information (continued)
PART
TOP VIEW
TEMP RANGE
+
V+
1
P_OUT
2
N_OUT
3
MAX5048A
MAX5048B
6
IN+
5
IN-
4
GND
MAX5048AAUT+T-40°C to +125°C 6 SOT23
TDFN-EP
(3mm x 3mm)
TTL ABED
VCC/2
AKV
MAX5048AATT+T -40°C to +125°C 6 TDFN-EP*
CMOS
MAX5048BATT+T -40°C to +125°C 6 TDFN-EP* TTL AKW
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
VCC/2
ABEC
CMOS
MAX5048BAUT+T-40°C to +125°C 6 SOT23
EXPOSED PAD
10
PINLOGIC TOP
PACKAGE INPUT MARK
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
6 SOT23
U6F+6
21-0058
90-0175
6 TDFN
—
21-0137
90-0058
Maxim Integrated
MAX5048
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Revision History
REVISION
NUMBER
REVISION
DATE
5
11/12
DESCRIPTION
Added “+” lead(Pb)-free/RoHS-compliant designations to Ordering Information
PAGES
CHANGED
1, 9
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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