ONSEMI MC100LVEP111FA

MC100LVEP111
Low-Voltage 1:10 Differential
LVECL/LVPECL/LVEPECL/HSTL
Clock Driver
The MC100LVEP111 is a low skew 1–to–10 differential driver,
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The LVECL/LVPECL input signals can be either
differential or single–ended (if the VBB output is used). HSTL inputs can
be used when the LVEP111 is operating under LVPECL conditions.
The LVEP111 specifically guarantees low output–to–output skew.
Optimal design, layout, and processing minimize skew within a device and
from lot to lot.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated identically into 50W even
if only one side is being used. When fewer than all ten pairs are used,
identically terminate all the output pairs on the same package side
whether used or unused. If no outputs on a single side are used, then
leave these outputs open (unterminated). This will maintain minimum
output skew. Failure to do this will result in a 10–20ps loss of skew
margin (propagation delay) in the output(s) in use.
The MC100LVEP111, as with most other LVECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP111 to be used for high performance clock distribution in
+3.3V or +2.5V systems. Single ended input operation is limited to a
VCC ≥ 3.0V in LVPECL mode, or VEE ≤ –3.0V in LVECL mode.
Designers can take advantage of the LVEP111’s performance to
distribute low skew clocks across the backplane or the board. In a
PECL environment, series or Thevenin line terminations are typically
used as they require no additional power supplies. For more
information on using LVPECL, designers should refer to Application
Note AN1406/D.
•
•
•
•
•
•
•
•
•
•
•
•
•
100ps Part–to–Part Skew
25ps Output–to–Output Skew
Differential Design
VBB Output
430ps Typical Propagation Delay
High Bandwidth to 1.5 Ghz Typical
LVPECL and HSTL mode: +2.375V to +3.8V VCC with VEE = 0V
LVECL mode: 0V VCC with VEE = –2.375V to –3.8V
75kΩ Internal Input Pulldown Resistors on CLKs, Pull up &
Pulldown resistors on CLKs
ESD Protection: >2KV HBM; >100V MM
Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34
Transistor Count = 602 devices
 Semiconductor Components Industries, LLC, 1999
March, 2000 – Rev. 2
1
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32–LEAD TQFP
FA SUFFIX
CASE 873A
MARKING DIAGRAM*
MC100
LVEP111
AWLYYWW
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
32
1
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100LVEP111FA
TQFP
250 Units/Tray
MC100LVEP111FAR2
TQFP
2000 Tape & Reel
Publication Order Number:
MC100LVEP111/D
MC100LVEP111
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
24
23
22
21
20
19
18
17
PIN DESCRIPTION
VCC
25
16
VCC
Q2
26
15
Q7
Q2
27
14
Q7
Q1
28
13
Q8
MC100LVEP111
29
12
Q8
Q0
30
11
Q9
Q0
31
10
Q9
VCC
32
9
1
2
VCC
CLK_SEL
Q1
3
4
5
6
7
Pins
Function
CLK0, CLK0
CLK1, CLK1
Q0:9, Q0:9
CLK_SEL
VBB
VCC
VEE
LVECL/LVPECL/HSTL CLK Input
LVECL/LVPECL/HSTL CLK Input
LVECL/LVPECL Outputs
LVECL/LVPECL Active Clock Select Input
Reference Voltage Output
Positive Supply
Negative, 0 Supply
FUNCTION TABLE
CLK_SEL
Active Input
0
1
CLK0, CLK0
CLK1, CLK1
VCC
8
CLK0 CLK0 VBB CLK1 CLK1 VEE
Figure 1. 32–Lead TQFP Pinout
(Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
CLK0
CLK0
CLK1
0
Q5
Q5
1
CLK1
CLK_SEL
Q6
Q6
VBB
Q7
Q7
Q8
Q8
Q9
Q9
Figure 2. Logic Symbol
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2
MC100LVEP111
MAXIMUM RATINGS*
Value
Unit
VEE
Symbol
Power Supply (VCC = 0V)
Parameter
–6.0 to 0
VDC
VCC
Power Supply (VEE = 0V)
6.0 to 0
VDC
VI
Input Voltage (VCC = 0V, VI not more negative than VEE)
–6.0 to 0
VDC
VI
Input Voltage (VEE = 0V, VI not more positive than VCC)
6.0 to 0
VDC
Iout
Output Current
50
100
mA
IBB
VBB Sink/Source Current{
± 0.5
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature
θJA
Thermal Resistance (Junction–to–Ambient)
θJC
Thermal Resistance (Junction–to–Case)
Tsol
Solder Temperature (<2 to 3 Seconds: 245°C desired)
Continuous
Surge
–65 to +150
°C
80
55
°C/W
12 to 17
°C/W
265
°C
Still Air
500lfpm
* Maximum Ratings are those values beyond which damage to the device may occur.
{ Use for inputs of same package only.
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V, VEE = –3.3(+0.925, –0.5)V) (Note 5.)
–40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current (Note 1.)
70
100
120
70
100
120
70
100
120
mA
Output HIGH Voltage (Note 2.)
–1145
–1020
–0895
–1145
–1020
–0895
–1145
–1020
–0895
mV
VOL
VIH
Output LOW Voltage (Note 2.)
–1995
–1820
–1650
–1995
–1820
–1650
–1995
–1820
–1650
mV
Input HIGH Voltage
–1165
–0880
–1165
–0880
–1165
–0880
mV
VIL
VBB
Input LOW Voltage
–1810
–1625
–1810
–1625
–1810
–1625
mV
Output Reference Voltage
(Note 3.)
–1525
–1325
–1525
–1325
–1525
–1325
mV
VIHCMR
Input HIGH Voltage Common
Mode Range (Note 4.)
0.0
V
IIH
IIL
Input HIGH Current
150
µA
150
µA
Max
Unit
1.
2.
3.
4.
5.
Input LOW Current
–1425
VEE + 1.2
0.0
–1425
VEE + 1.2
150
0.5
–150
0.0
–1425
VEE + 1.2
150
0.5
–150
0.5
–150
VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating.
All loading with 50 ohms to VCC–2.0 volts.
Single ended input operation is limited VEE ≤ –3.0V in ECL/LVECL mode.
VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, HSTL (VCC = 2.5(–0.125, +1.3)V, VEE = 0V)
–40°C
Symbol
Characteristic
VIH
VIL
Input HIGH Voltage
VX
Input Crossover Voltage
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
1200
mV
Input LOW Voltage
400
680
ICC
Power Supply Current (Note 6.)
70
100
6. VCC = 2.375V to 3.8V, VEE = 0V, all other pins floating.
120
70
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3
mV
900
100
120
mV
70
100
120
mA
MC100LVEP111
DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.5V, VEE = 0V) (Note 11.)
–40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current (Note 7.)
70
100
120
70
100
120
70
100
120
mA
Output HIGH Voltage (Note 8.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 8.)
1305
1480
1650
1305
1480
1650
1305
1480
1650
mV
Input HIGH Voltage
2135
2420
2135
2420
2135
2420
mV
VIL
VBB
Input LOW Voltage
1490
1675
1490
1675
1490
1675
mV
Output Reference Voltage
(Note 9.)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common
Mode Range (Note 10.)
3.3
1.2
3.3
1.2
3.3
V
IIH
IIL
Input HIGH Current
150
µA
150
µA
Input LOW Current
1875
1.2
1875
150
0.5
–150
1875
150
0.5
–150
0.5
–150
7. VCCmin to VCCmax.
8. All loading with 50 ohms to VCC–2.0 volts.
9. Single ended input operation is limited VCC ≥ 3.0V in PECL mode.
10. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
11. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, LVEPECL (VCC = 2.5V ± 0.125V, VEE = 0V) (Note 15.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current (Note 12.)
70
100
120
70
100
120
70
100
120
mA
Output HIGH Voltage (Note 13.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
VIH
Output LOW Voltage (Note 13.)
505
680
850
505
680
850
505
680
850
mV
Input HIGH Voltage
1335
1620
1335
1620
1335
1620
mV
VIL
VIHCMR
Input LOW Voltage
690
875
690
875
690
875
mV
Input HIGH Voltage Common
Mode Range (Note 14.)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
IIL
Input HIGH Current
150
µA
150
µA
Input LOW Current
150
0.5
–150
150
0.5
–150
0.5
–150
12. VCCmin to VCCmax.
13. All loading with 50 ohms to VEE.
14. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
15. Input and output parameters vary 1:1 with VCC.
AC CHARACTERISTICS (VCC = 0V; VEE = –2.5(+0.125, –1.3)V)
–40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
fmaxLVPECL
Maximum Input Frequency
for LVECL and LVPECL
1.5
1.5
1.5
GHz
fmaxHSTL
Maximum Input Frequency
for HSTL
250
250
250
MHz
tPLH
tPHL
tskew
Propagation Delay to Output
IN (differential)
VPP
tr/tf
Minimum Input Swing
150
800
1200
Output Rise/Fall Time
(20%–80%)
100
180
300
300
Within–Device Skew (17.)
Part–to–Part Skew (Diff) (18.)
400
500
310
430
550
20
100
25
150
800
1200
150
800
1200
mV
120
200
320
130
230
375
ps
20
100
16. Fmax guaranteed for functionality only.
17. Skew is measured between outputs under identical transitions and conditions on any one device.
18. Part–to–part skew for identical transitions at identical VCC levels.
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4
350
510
625
20
100
ps
ps
MC100LVEP111
PACKAGE DIMENSIONS
FA SUFFIX
PLASTIC TQFP PACKAGE
CASE 873A–02
ISSUE A
A
4X
A1
AC T–U Z
0.20 (0.008) AB T–U Z
25
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
1
B
V
B1
DETAIL Y
V1
17
8
9
J
4X
–Z–
9
F
M
N
–U–
–T–
D
0.20 (0.008)
32
SECTION AE–AE
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
–T–, –U–, –Z–
G
–AB–
SEATING
PLANE
–AC–
0.10 (0.004) AC
8X
M_
R
AE
P
C E
AE
K
X
DETAIL AD
GAUGE PLANE
H
Q_
0.250 (0.010)
DETAIL Y
W
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5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE
DETERMINED AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL
BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MC100LVEP111
Notes
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6
MC100LVEP111
Notes
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7
MC100LVEP111
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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MC100LVEP111/D