MC100LVEP14
Low-Voltage 1:5 Differential
LVECL/LVPECL/LVEPECL/HSTL
Clock Driver
The MC100LVEP14 is a low skew 1–to–5 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The LVECL/LVPECL input signals can be either differential
or single–ended (if the VBB output is used). HSTL inputs can be used
when the LVEP14 is operating under LVPECL conditions.
The LVEP14 specifically guarantees low output–to–output skew.
Optimal design, layout, and processing minimize skew within a device and
from lot to lot.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated identically into 50W even
if only one side is being used. When fewer than all five pairs are used,
identically terminate all the output pairs on the same package side
whether used or unused. If no outputs on a single side are used, then
leave these outputs open (unterminated). This will maintain minimum
output skew. Failure to do this will result in a 10–20ps loss of skew
margin (propagation delay) in the output(s) in use.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.
The MC100LVEP14, as with most other LVECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP14 to be used for high performance clock distribution in
+3.3V or +2.5V systems. Single ended input operation is limited to a
VCC ≥ 3.0V in LVPECL mode, or VEE ≤ –3.0V in LVECL mode.
Designers can take advantage of the LVEP14’s performance to
distribute low skew clocks across the backplane or the board. For more
information, refer to Application Note AN1406/D.
•
•
•
•
•
•
•
•
•
•
•
•
100ps Part–to–Part Skew
25ps Output–to–Output Skew
Differential Design
400ps Typical Propagation Delay
High Bandwidth to 1.5 Ghz Typical
LVPECL and HSTL mode: +2.375V to +3.8V VCC with VEE = 0V
LVECL mode: 0V VCC with VEE = –2.375V to –3.8V
75kΩ Internal Pulldown CLKs, Pull up & Pulldown CLKs
ESD Protection: >2KV HBM; >100V MM
Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34
Transistor Count = 357 devices
Semiconductor Components Industries, LLC, 2000
May, 2000 – Rev. 1
1
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20
1
TSSOP–20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
VP = LVEP
100
VP14
ALYW
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
MC100LVEP14DT
Package
Shipping
TSSOP
75 Units/Tray
MC100LVEP14DTR2 TSSOP
2500 Tape & Reel
Publication Order Number:
MC100LVEP14/D
MC100LVEP14
VCC
EN
VCC
20
19
18
CLK1 CLK1
17
VBB CLK0 CLK0 CLK_SEL VEE
16
15
1
14
13
12
11
0
D Q
1
2
3
4
5
6
7
8
9
10
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Figure 1. 20–Lead TSSOP and Logic Diagram
(Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
PIN DESCRIPTION
Pins
Function
CLK0, CLK0
CLK1, CLK1
Q0:4, Q0:4
CLK_SEL
EN
VBB
VCC
VEE
LVECL/LVPECL/HSTL CLK Input
LVECL/LVPECL/HSTL CLK Input
LVECL/LVPECL Outputs
LVECL/LVPECL Active Clock Select Input
Sync Enable
Reference Voltage Output
Positive Supply
Negative, 0 Supply
FUNCTION TABLE
CLK0
CLK1
CLK_SEL
EN
Q
L
H
X
X
X
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L*
* On next negative transition of CLK0 or CLK1
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2
MC100LVEP14
MAXIMUM RATINGS*
Value
Unit
VEE
Symbol
Power Supply (VCC = 0V)
Parameter
–6.0 to 0
VDC
VCC
Power Supply (VEE = 0V)
6.0 to 0
VDC
VI
Input Voltage (VCC = 0V, VI not more negative than VEE)
–6.0 to 0
VDC
VI
Input Voltage (VEE = 0V, VI not more positive than VCC)
6.0 to 0
VDC
Iout
Output Current
50
100
mA
IBB
VBB Sink/Source Current{
± 0.5
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature
θJA
Thermal Resistance (Junction–to–Ambient)
θJC
Thermal Resistance (Junction–to–Case)
Tsol
Solder Temperature (<2 to 3 Seconds: 245°C desired)
Continuous
Surge
–65 to +150
°C
90
60
°C/W
30 to 35
°C/W
265
°C
Still Air
500lfpm
* Maximum Ratings are those values beyond which damage to the device may occur.
{ Use for inputs of same package only.
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V, VEE = –3.3(+0.925, –0.5)V) (Note 5.)
–40°C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current (Note 1.)
45
60
75
45
60
75
45
60
95
mA
Output HIGH Voltage (Note 2.)
–1145
–1020
–0895
–1145
–1020
–0895
–1145
–1020
–0895
mV
VOL
VIH
Output LOW Voltage (Note 2.)
–1995
–1820
–1650
–1995
–1820
–1650
–1995
–1820
–1650
mV
Input HIGH Voltage
–1165
–0880
–1165
–0880
–1165
–0880
mV
VIL
VBB
Input LOW Voltage
–1810
–1625
–1810
–1625
–1810
–1625
mV
Output Reference Voltage (Note 3.)
–1525
–1325
–1525
–1325
–1525
–1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 4.)
0.0
V
IIH
IIL
Input HIGH Current
150
µA
150
µA
Max
Unit
1.
2.
3.
4.
5.
Input LOW Current
–1425
VEE + 1.2
0.0
–1425
VEE + 1.2
150
0.5
–150
0.0
–1425
VEE + 1.2
150
0.5
–150
0.5
–150
VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating.
All loading with 50 ohms to VCC–2.0 volts.
Single ended input operation is limited VEE ≤ –3.0V in ECL/LVECL mode.
VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, HSTL (VCC = 2.5(–0.125, +1.3)V, VEE = 0V)
–40°C
Symbol
Characteristic
VIH
VIL
Input HIGH Voltage
VX
Input Crossover Voltage
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
1200
mV
Input LOW Voltage
400
680
ICC
Power Supply Current (Note 6.)
6. VCC = 2.375V to 3.8V, VEE = 0V, all other pins floating.
100
100
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3
mV
900
mV
100
mA
MC100LVEP14
DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.5V, VEE = 0V) (Note 11.)
–40°C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current (Note 7.)
45
60
75
45
60
75
45
60
75
mA
Output HIGH Voltage (Note 8.)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
VIH
Output LOW Voltage (Note 8.)
1305
1480
1650
1305
1480
1650
1305
1480
1650
mV
Input HIGH Voltage
2135
2420
2135
2420
2135
2420
mV
VIL
VBB
Input LOW Voltage
1490
1675
1490
1675
1490
1675
mV
Output Reference Voltage (Note 9.)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 10.)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
IIL
Input HIGH Current
150
µA
150
µA
Input LOW Current
1875
1875
150
0.5
–150
1875
150
0.5
–150
0.5
–150
7. VCCmin to VCCmax.
8. All loading with 50 ohms to VCC–2.0 volts.
9. Single ended input operation is limited VCC ≥ 3.0V in PECL mode.
10. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
11. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, LVEPECL (VCC = 2.5V ± 0.125V, VEE = 0V) (Note 15.)
–40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
VOH
Power Supply Current (Note 12.)
45
60
75
45
60
75
45
60
75
mA
Output HIGH Voltage (Note 13.)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
VIH
Output LOW Voltage (Note 13.)
505
680
850
505
680
850
505
680
850
mV
Input HIGH Voltage
1335
1620
1335
1620
1335
1620
mV
VIL
VIHCMR
Input LOW Voltage
690
875
690
875
690
875
mV
Input HIGH Voltage Common
Mode Range (Note 14.)
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
IIL
Input HIGH Current
150
µA
150
µA
Input LOW Current
150
0.5
–150
150
0.5
–150
0.5
–150
12. VCCmin to VCCmax.
13. All loading with 50 ohms to VEE.
14. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
15. Input and output parameters vary 1:1 with VCC.
AC CHARACTERISTICS (VCC = 0V; VEE = –2.5(+0.125, –1.3)V)
–40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
fmaxLVPECL
Maximum Input Frequency
for LVECL and LVPECL
1.5
1.5
1.5
GHz
fmaxHSTL
Maximum Input Frequency
for HSTL
250
250
250
MHz
tPLH
tPHL
Propagation Delay to Output
IN (differential)
IN (single–ended)
tskew
Within–Device Skew
Part–to–Part Skew (Diff)
tJITTER
VPP
Cycle–to–Cycle Jitter
Minimum Input Swing
150
800
1200
150
800
1200
150
800
1200
mV
tr/tf
Output Rise/Fall Time
(20%–80%)
100
165
250
110
180
275
110
200
290
ps
ps
275
400
400
500
TBD
TBD
25
100
35
TBD
TBD
375
475
300
16. Fmax guaranteed for functionality only.
17. Skew is measured between outputs under identical transitions.
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4
300
430
550
TBD
TBD
ps
TBD
ps
MC100LVEP14
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X
0.15 (0.006) T U
K REF
0.10 (0.004)
S
M
T U
S
V
S
K
K1
2X
20
L/2
11
B
–U–
L
PIN 1
IDENT
J J1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
M
A
–V–
N
F
DETAIL E
–W–
C
D
G
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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5
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC100LVEP14
Notes
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MC100LVEP14
Notes
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MC100LVEP14
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MC100LVEP14/D