MOTOROLA MC1670L

SEMICONDUCTOR TECHNICAL DATA
Master slave construction renders the MC1670 relatively insensitive to the
shape of the clock waveform, since only the voltage levels at the clock inputs
control the transfer of information from data input (D) to output.
When both clock inputs (C1 and C2) are in the low state, the data input
affects only the “Master” portion of the flip-flop. The data present in the “Master”
is transferred to the “Slave” when clock inputs (C1 “OR” C2) are taken from a
low to a high level. In other words, the output state of the flip-flop changes on the
positive transition of the clock pulse.
While either C1 “OR” C2 is in the high state, the “Master” (and data input) is
disabled.
Asynchronous Set (S) and Reset (R) override Clock (C) and Data (D) inputs.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
Power Dissipation = 220 mW typ (No Load)
fTog = 350 MHz typ
TRUTH TABLE
R
S
D
C
Qn+1
L
H
H
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
X
X
X
L
L
L
H
H
H
X
X
X
L
H
L
N.D.
Qn
L
Qn
Qn
H
Qn
H
L
H
LOGIC DIAGRAM
5
S
7 C1
Q 2
9 C2
ND = Not Defined
C = C1 + C2
11
D
4
R
ELECTRICAL CHARACTERISTICS
–30°C
+ 25°C
Ch
Characteristic
i i
S b l
Symbol
Min
Max
Min
Max
Min
Max
U i
Unit
IE
—
—
—
48
—
—
mAdc
—
—
—
—
—
—
—
—
—
550
250
270
—
—
—
—
—
—
Switching Times
Propagation Delay
VCC1 = Pin 1
VCC2 = Pin 16
VEE = Pin 8
+ 85°C
Power Supply Drain Current
Input Current
Set, Reset
Clock
Data
Q 3
µAdc
IinH
PIN ASSIGNMENT
ns
VCC1
1
16
VCC2
Q
2
15
NC
1.0
2.7
1.1
2.5
1.1
2.9
Rise Time (10% to 90%)
tpd
t+
0.9
2.7
1.0
2.5
1.0
2.9
ns
Q
3
14
NC
Fall Time (10% to 90%)
t–
0.5
2.1
0.6
1.9
0.6
2.3
ns
RESET
4
13
NC
tS“1”
tS“0”
tH“1”
tH“0”
—
—
—
—
0.4
0.5
—
—
—
—
—
—
ns
SET
5
12
NC
—
—
—
—
0.3
0.5
—
—
—
—
—
—
ns
NC
6
11
DATA
fTog
270
—
300
—
270
—
MHz
CLOCK 1
7
10
NC
VEE
8
9
Setup Time
Hold Time
Toggle Frequency
3/93
 Motorola, Inc. 1996
4–356
REV 5
CLOCK 2
MC1670
FIGURE 1 — TOGGLE FREQUENCY WAVEFORMS
TA = 25°C
+1.11 V
CLOCK INPUT
300
MHZ-MAX
+0.71 VBIAS
+0.31 V
Q OR Q
OUTPUT
600 MV MIN
The maximum toggle frequency of the MC1670 has been exceeded
when either:
1. The output peak-to-peak voltage swing falls below 600
millivolts,
OR
2. The device ceases to toggle (divide by two).
VBias
FIGURE 2 — MAXIMUM TOGGLE FREQUENCY (TYPICAL)
+1.05
+1.0
+0.95
+0.9
+0.85
+0.8
+0.75
+0.7
+0.65
+0.5
+0.45
+0.4
+0.35
+0.3
+0.25
175
TA = 25°C
VCC = +2.0 VDC
VEE = –3.2 VDC
Figure 2 illustrates the variation in toggle frequency
with the dc offset voltage (V Bias ) of the input clock signal.
Figures 4 and 5 illustrate minimum clock pulse width
recommended for reliable operation of the MC1670.
225
275
325
375
425
FTOG
(MHZ)
fTog max , MAXIMUM TOGGLE
FREQUENCY (MHz)
FIGURE 3 — TYPICAL MAXIMUM TOGGLE FREQUENCY
versus TEMPERATURE
400
350
300
250
–30
0
25
50
85
TA, AMBIENT TEMPERATURE (°C)
Temperature
–30°C
+25°C
+85°C
VBias
+0.66 Vdc
+0.71 Vdc
+0.765 Vdc
Note: All power supply and logic levels are shown shifted 2.0 volts positive.
MECL Data
DL122 — Rev 6
4–357
MOTOROLA
MC1670
FIGURE 4 — MINIMUM “DOWN TIME” TO CLOCK
OUTPUT LOAD = 50 Ω
SCALE
250 mV/DIV
CLOCK
Q OR
Q
1.0 NS/DIV.
FIGURE 5 — MINIMUM “UP TIME” TO CLOCK
OUTPUT LOAD = 50 Ω
SCALE
250 mV/DIV
Q OR
Q
CLOCK
1.0 NS/DIV.
MOTOROLA
4–358
MECL Data
DL122 — Rev 6
MC1670
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
M
T B
S
DIM
A
B
C
D
E
F
G
H
K
L
M
N
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
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◊
MECL Data
DL122 — Rev 6
4–359
*MC1670/D*
MC1670/D
MOTOROLA