MOTOROLA MC74HC597D

SEMICONDUCTOR TECHNICAL DATA
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High–Performance Silicon–Gate CMOS
The MC54/74HC597 is identical in pinout to the LS597. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of an 8–bit input latch which feeds parallel data to an
8–bit shift register. Data can also be loaded serially (see Function Table).
The HC597 is similar in function to the HC589, which is a 3–state device.
•
•
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•
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Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 516 FETs or 129 Equivalent Gates
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
LOGIC DIAGRAM
SERIAL
DATA
INPUT
SA
A
B
PARALLEL
DATA
INPUTS
C
D
E
F
G
H
LATCH CLOCK
SHIFT CLOCK
SERIAL SHIFT/
PARALLEL LOAD
RESET
14
PIN ASSIGNMENT
B
1
16
VCC
15
C
2
15
A
1
D
3
14
E
4
13
F
5
12
SA
SERIAL SHIFT/
PARALLEL LOAD
LATCH CLOCK
G
6
11
SHIFT CLOCK
H
7
10
RESET
GND
8
9
2
3
4
5
INPUT
LATCH
SHIFT
REGISTER
6
7
12
SERIAL
9
DATA
QH
OUTPUT
11
13
PIN 16 = VCC
PIN 8 = GND
10
10/95
 Motorola, Inc. 1995
1
REV 6
QH
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MC54/74HC597
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
— Ceramic DIP: – 10 mW/_C from 100_ to 125_C
— SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
44
5.9
1.9
44
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
ICC
4.0 mA
5.2 mA
4.0 mA
5.2 mA
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HC597
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 8)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QH
(Figures 1 and 8)
2.0
4.5
6.0
210
42
36
265
53
45
315
63
54
ns
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to QH
(Figures 2 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPHL
Maximum Propagation Delay, Reset to QH
(Figures 3 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH,
tPHL
Maximum Propagation Delay, Serial Shift/Parallel Load to QH
(Figures 4 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Cin
Parameter
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
50
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
DATA INPUTS
Reset (Pin 10)
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Asynchronous, Active–low shift register reset. A low level
applied to this input resets the shift register to a low level, but
does not change the data in the input latch.
Parallel data inputs. Data on these inputs is stored in the
input latch on the rising edge of the Latch Clock input.
Shift Clock (Pin 11)
SA (Pin 14)
Serial shift register clock. A low–to–high transition on this
input shifts data on the Serial Data Input into the shift register
and data in stage H is shifted out QH, being replaced by the
data previously stored in stage G.
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input it Serial
Shift/Parallel Load is high. Data on this input is ignored when
Serial Shift/Parallel Load is low.
Latch Clock (Pin 12)
CONTROL INPUTS
Latch clock. A low–to–high transition on this input loads
the parallel data on inputs A–H into the input latch.
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied to
this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the input latch, and serial shifting
is inhibited.
High–Speed CMOS Logic Data
DL129 — Rev 6
OUTPUT
QH (Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register.
3
MOTOROLA
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MC54/74HC597
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to
25_C
85_C
125_C
Unit
tsu
Minimum Setup Time, Parallel Data inputs A–H to Latch Clock
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Serial Data Input SA to Shift Clock
(Figure 6)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock
(Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Latch Clock to Parallel Data Inputs A–H
(Figure 5)
2.0
4.5
6.0
25
5
5
30
6
6
40
8
7
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input SA
(Figure 6)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
trec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 3)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tw
Minimum Pulse Width, Latch Clock and Shift Clock
(Figures 1 and 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset
(Figure 3)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Serial Shift/Parallel Load
(Figure 4)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
1000
1000
1000
ns
4.5
500
500
500
6.0
400
400
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
FUNCTION TABLE
Inputs
Resulting Function
Reset
Serial Shift/
Parallel Load
Reset shift register
L
X
X
Serial
Input
SA
X
X
U
L
Output
QH
L
Reset shift register; load
parallel data into data latch
L
X
X
X
a–h
a–h
L
L
Load parallel data into data
latch
H
H
L,H,
X
a–h
a–h
U
U
Transfer latch contents to
shift register
H
L
L, H,
X
X
X
U
LRN → SRN
LRH
Contents of data latch and
shift register are
unchanged
H
H
L, H,
L,H,
X
X
U
U
U
Load parallel data into data
latch and shift register
H
L
X
X
a–h
a–h
a–h
h
Shift serial data into shift
register
H
H
D
X
*
SRA = D;
SRN → SRN + 1
SRG → SRH
Load parallel data into data
latch and shift serial data
into shift register
H
H
D
a–h
a–h
SRA = D;
SRN → SRN + 1
SRG → SRH
Operation
LR = latch register contents
SR = shift register contents
* = depends on latch clock input
MOTOROLA
Latch
Clock
L, H,
Shift
Clock
X
Parallel
Inputs
A–H
a–h = data at parallel data inputs A–H
D = data (L, H) at serial data input SA
4
Latch
Contents
Shift
Register
Contents
U = remains unchanged
X = don’t care
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC597
SWITCHING WAVEFORMS
tw
tr
LATCH CLOCK
1/fmax
tf
tw
VCC
90%
50%
10%
SHIFT CLOCK
GND
tPLH
GND
tPHL
tPLH
90%
50%
10%
QH
VCC
50%
QH
tTLH
tPHL
50%
tTHL
Figure 1. (Serial Shift/Parallel Load = L)
tw
Figure 2. (Serial Shift/Parallel Load = H)
VCC
50%
RESET
GND
tPHL
tw
SERIAL SHIFT/
PARALLEL LOAD
50%
QH
trec
VCC
50%
50%
tPLH
tPHL
GND
QH
50%
SHIFT CLOCK
Figure 3.
Figure 4.
VALID
PARALLEL DATA
A/H
VALID
VCC
SERIAL DATA
INPUT SA
50%
GND
tsu
VCC
50%
GND
th
tsu
th
VCC
LATCH CLOCK
VCC
50%
SHIFT CLOCK
50%
GND
GND
Figure 5.
Figure 6.
TEST POINT
SERIAL SHIFT/
PARALLEL LOAD
VCC
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tsu
SHIFT CLOCK
VCC
CL*
50%
GND
* Includes all probe and jig capacitance
Figure 8. Test Circuit
Figure 7.
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
MC54/74HC597
EXPANDED LOGIC DIAGRAM
SERIAL DATA 14
INPUT, SA
SHIFT CLOCK
RESET
11
10
SERIAL SHIFT/ 13
PARALLEL LOAD
LATCH CLOCK
A
12
15
STAGE A
D
Q
C
D
S
C Q
R
STAGE B
B
1
D
Q
C
D
S
C Q
R
PARALLEL
DATA
INPUTS
C
D
E
F
G
2
STAGE C*
3
STAGE D*
4
STAGE E*
5
STAGE F*
6
STAGE G*
STAGE H
H
7
D
Q
C
D
S
C Q
R
9
QH
*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.
MOTOROLA
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC597
TIMING DIAGRAM
SHIFT CLOCK
SERIAL DATA
INPUT, SA
RESET
SERIAL SHIFT
PARALLEL LOAD
LATCH CLOCK
PARALLEL
DATA
INPUTS
A
H
L
L
B
L
L
L
C
H
L
L
D
L
L
L
E
H
L
H
F
H
L
H
G
L
L
L
H
H
H
H
L
QH
RESET
L H
L
H
SERIAL
SHIFT
SHIFT
REGISTER
H
L
H
H
LOAD LATCH
7
L
H
L
L
SERIAL
SHIFT
SERIAL SHIFT
LOAD LATCH PARALLEL LOAD
SHIFT REGISTER
High–Speed CMOS Logic Data
DL129 — Rev 6
L
PARALLEL LOAD
SHIFT REGISTER
L
H
L
H
H
SERIAL
SHIFT
PARALLEL LOAD LATCH
AND SHIFT REGISTER
MOTOROLA
MC54/74HC597
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
–B
–
L
C
DIM
A
B
C
D
E
F
G
J
K
L
M
N
–T
K
N
SEATING
–
PLANE
E
M
F
J 16 PL
0.25 (0.010)
G
D 16 PL
0.25 (0.010)
T A
M
9
1
8
T B
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
M
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
MOTOROLA
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
8
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
MILLIMETERS
MIN
MAX
19.05 19.93
6.10
7.49
—
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
15°
0°
1.01
0.51
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
S
S
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
—
0.200
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
15°
0°
0.020 0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC597
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
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*MC54/74HC597/D*
MC54/74HC597/D
MOTOROLA