MOTOROLA MC74HCT157A

SEMICONDUCTOR TECHNICAL DATA
$ $# #
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High–Performance Silicon–Gate CMOS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
The MC74HCT157A is identical in pinout to the LS157. This device may
be used as a level converter for interfacing TTL or NMOS outputs to High
Speed CMOS inputs.
This device routes 2 nibbles (A or B) to a single port (Y) as determined by
the Select input. The data is presented at the outputs in noninverted form. A
high level on the Output Enable input sets all four Y outputs to a low level.
The HCT157A is similar in function to the HC257 which has 3–state
outputs.
1
ORDERING INFORMATION
MC74HCTXXXAN
MC74HCTXXXAD
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 102 FETs or 25.5 Equivalent Gates
NIBBLE
A INPUTS
A1
A2
A3
B0
NIBBLE
B INPUTS
B1
B2
B3
16
A0
2
15
B0
3
14
4
13
B3
A1
5
12
Y3
B1
6
11
A2
11
Y1
7
10
B2
14
GND
8
9
Y2
2
5
4
3
7
6
9
10
12
Y0
Y1
Y2
DATA
OUTPUTS
FUNCTION TABLE
Y3
Inputs
13
1
15
Design Criteria
Value
Unit
Internal Gate Count*
25.5
ea
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
0.005
µW
Speed Power Product
0.0075
pJ
2/97
1
Output
Enable
Select
Outputs
Y0 – Y3
H
L
L
X
L
H
L
A0 – A3
B0 – B3
X = don’t care
A0 – A3, B0 – B3 = the levels
of the respective Data–Word
Inputs.
* Equivalent to a two input NAND gate.
 Motorola, Inc. 1997
1
Y0
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OUTPUT ENABLE
SELECT
VCC
OUTPUT
ENABLE
A3
PIN 16 = VCC
PIN 8 = GND
SELECT
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
A0
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
REV 7
MC74HCT157A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
S b l
Symbol
P
Parameter
T
Test
C
Conditions
di i
VCC
V
– 55 to
25_C
85_C
125_C
U i
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low–Level Input
Voltage
Vout 0.1 V or VCC – 0.1 V
|Iout|
20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 mA
4.5
5.5
44
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout|
4.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout|
4.0 mA
4.5
0.26
0.33
0.4
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
5.5
4.0
40
160
µA
∆ICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 µA
VOH
VOL
Iin
Maximum Low–Level Output
Voltage
55
5.5
≥ – 55_C
25_C to 125_C
2.9
2.4
V
mA
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HCT157A
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AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to
25_C
85_C
125_C
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 4)
27
34
41
ns
tPLH,
tPHL
Maximum Propagation Delay, Select to Output Y
(Figures 2 and 4)
37
46
56
ns
tPLH,
tPHL
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 4)
30
38
45
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
15
19
22
ns
Maximum Input Rise and Fall Time
500
500
500
ns
S b l
Symbol
tr, tf
P
Parameter
U i
Unit
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
P
Power
Di
Dissipation
i i C
Capacitance
i
(P
(Per T
Transceiver
i
Ch
Channel)*
l)*
64
pF
F
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
these outputs when the Output Enable input is at a low level.
The data is presented to the outputs in noninverted form. For
the Output Enable input at a high level, the outputs are at a
low level.
A0, A1, A2, A3 (Pins 2, 5, 11, 14)
Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level
and the Output Enable input is at a low level. The data is
presented to the outputs in noninverted form.
CONTROL INPUTS
B0, B1, B2, B3 (Pins 3, 6, 10, 13)
Select (Pin 1)
Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level
and the Output Enable input is at a low level. The data is
presented to the outputs in noninverted form.
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects
the A inputs and a high level selects the B inputs.
Output Enable (Pin 15)
OUTPUTS
Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
level on this input sets all outputs to a low level.
Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
Data outputs. The selected input Nibble is presented at
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC74HCT157A
EXPANDED LOGIC DIAGRAM
A0
B0
A1
B1
NIBBLE
INPUTS
A2
B2
A3
B3
2
4
3
Y0
5
7
6
Y1
11
DATA
OUTPUTS
9
10
Y2
14
12 Y3
13
OUTPUT ENABLE
SELECT
SWITCHING WAVEFORMS
tr
tr
tf
2.7 V
1.3 V
0.3 V
INPUT A OR B
GND
GND
tPLH
tPHL
90%
1.3 V
10%
OUTPUT Y
tTLH
3V
2.7 V
1.3 V
0.3 V
SELECT
tPLH
OUTPUT Y
tf
3V
tPHL
90%
1.3 V
10%
tTHL
tTLH
tTHL
Figure 1.
Figure 2.
TEST POINT
tr
tf
OUTPUT ENABLE
tPHL
OUTPUT
VCC
2.7 V
1.3 V
0.3 V
DEVICE
UNDER
TEST
GND
tPLH
90%
1.3 V
10%
OUTPUT Y
tTHL
tTLH
* Includes all probe and jig capacitance
Figure 3.
MOTOROLA
CL*
Figure 4. Test Circuit
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HCT157A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.229 0.244
0.010 0.019
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
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INTERNET: http://www.mot.com/SPS/
High–Speed CMOS Logic Data
DL129 — Rev 6
◊
5
MC74HCT157A/D
MOTOROLA