MICRON MT4LDT832HG-5X

ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
SMALL-OUTLINE
DRAM MODULE
MT2LDT432H (X)(S), MT4LDT832H (X)(S)
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/datasheets/datasheet.html
FEATURES
PIN ASSIGNMENT (Front View)
• JEDEC pinout in a 72-pin, small-outline, dual inline memory module (SODIMM)
• 16MB (4 Meg x 32) and 32MB (8 Meg x 32)
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Optional self refresh (S) for low-power data retention
72-Pin Small-Outline DIMM
1
OPTIONS
MARKING
• Package
72-pin SODIMM (gold)
G
• Timing
50ns access
60ns access
-5
-6
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
None
X
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
None
S
PIN
FRONT
PIN
1
VSS
2
3
DQ1
4
5
DQ3
6
7
DQ5
8
9
DQ7
10
11
PRD1
12
13
A1
14
15
A3
16
17
A5
18
19
A10
20
21
DQ8
22
23
DQ10
24
25
DQ12
26
27
DQ14
28
29
A11
30
31
A8
32
33 NC/RAS3#* 34
35
DQ15
36
PART NUMBERS
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
BACK
DQ17
CAS0#
CAS3#
RAS0#
NC (A12)
NC (A13)
DQ19
DQ21
DQ23
DQ24
DQ26
DQ27
DQ29
DQ31
PRD2
PRD4
PRD6
VSS
CONFIGURATION
4 Meg x 32
4 Meg x 32
8 Meg x 32
8 Meg x 32
NOTE: Symbols in parentheses are not used on these modules but may
be used for other modules in this product family. They are for
reference only.
REFRESH
Standard
Self
Standard
Self
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-5
-6
FPM Operating Mode
PART NUMBER
MT2LDT432HG-x
MT2LDT432HG-x S
MT4LDT832HG-x
MT4LDT832HG-x S
x = speed
PIN
FRONT
PIN
37
DQ16
38
39
VSS
40
41
CAS2#
42
43
CAS1#
44
45 NC/RAS1#* 46
47
WE#
48
49
DQ18
50
51
DQ20
52
53
DQ22
54
55
NC
56
57
DQ25
58
59
DQ28
60
61
VDD
62
63
DQ30
64
65
NC
66
67
PRD3
68
69
PRD5
70
71
PRD7
72
*32MB version only
EDO Operating Mode
PART NUMBER
MT2LDT432HG-x X
MT2LDT432HG-x XS
MT4LDT832HG-x X
MT4LDT832HG-x XS
x = speed
BACK
DQ0
DQ2
DQ4
DQ6
VDD
A0
A2
A4
A6
NC
DQ9
DQ11
DQ13
A7
VDD
A9
RAS2#
NC
CONFIGURATION
4 Meg x 32
4 Meg x 32
8 Meg x 32
8 Meg x 32
REFRESH
Standard
Self
Standard
Self
tRC
84ns
104ns
tRAC
50ns
60ns
tPC
20ns
25ns
tAA
25ns
30ns
tCAC
tCAS
13ns
15ns
8ns
10ns
FPM Operating Mode
SPEED
-5
-6
1
tRC
tRAC
tPC
tAA
tCAC
tRP
90ns
110ns
50ns
60ns
30ns
35ns
25ns
30ns
13ns
15ns
30ns
40ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
GENERAL DESCRIPTION
The MT2LDT432H (X)(S) and MT4LDT832H (X)(S)
are randomly accessed 16MB and 32MB memories
organized in a small-outline x32 configuration. They
are specially processed to operate from 3V to 3.6V for
low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the address bits, which are entered
12 bits (A0-A11) at a time. RAS# is used to latch the first
12 bits and CAS# the latter 10 bits.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. If WE# goes
LOW prior to CAS# going LOW, the output pin(s)
remain open (High-Z) until the next CAS# cycle.
FAST-PAGE-MODE READ, except data will be held
valid or become valid after CAS# goes HIGH, as long as
RAS# and OE# are held LOW. (Refer to the 4 Meg x 16
[MT4LC4M16R6] DRAM data sheet for additional
information on EDO functionality.)
REFRESH
Memory cell data is retained in its correct state by
maintaining power and executing any RAS# cycle
(READ, WRITE) or RAS# refresh cycle (RAS#-ONLY,
CBR or HIDDEN) so that all combinations of RAS#
addresses are executed at least every tREF, regardless of
sequence. The CBR REFRESH cycle will invoke the
internal refresh counter for automatic RAS# addressing.
An optional self refresh mode is also available. The
“S” option allows the user the choice of a fully static,
low-power data retention mode or a dynamic refresh
mode at the extended refresh period of 128ms. The
optional self refresh feature is initiated by performing
a CBR REFRESH cycle and holding RAS# LOW for the
specified tRASS.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of tRPS. This delay allows
for the completion of any internal refresh cycles that
may be in process at the time of the RAS# LOW-toHIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM controller utilizes a RAS#-ONLY or burst refresh sequence,
all rows must be refreshed within the average internal
refresh rate, prior to the resumption of normal operation.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data
operations (READ or WRITE) within a row-addressdefined page boundary. The FAST-PAGE-MODE cycle
is always initiated with a row address strobed in by
RAS#, followed by a column address strobed in by
CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles.
Returning RAS# HIGH terminates the FAST-PAGEMODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version,
is an accelerated FAST-PAGE-MODE cycle. The primary advantage of EDO is the availability of data-out
even after CAS# goes back HIGH. EDO provides for
CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS#
output control provides for pipelined READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO operates as any DRAM READ or
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM
MT2LDT432H (X)(S) (16MB)
12
A0-A11
U1
WE#
CAS0#
CASL#
CAS1#
CASH#
RAS0#
RAS#
DQ0DQ15
16
OE#
A0-A11
12
WE#
32
12
DQ0-DQ31
A0-A11
WE#
U2
CAS2#
CASL#
CAS3#
CASH#
RAS2#
RAS#
DQ16DQ31
16
OE#
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
VDD
U1-U2
U1-U2 = MT4LC4M16R6TG (S) EDO PAGE MODE
VSS
U1-U2
U1-U2 = MT4LC4M16F5TG (S) FAST PAGE MODE
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM
MT4LDT832H (X)(S) (32MB)
12
A0-A11
U1
WE#
DQ0DQ15
CAS0#
CASL#
CAS1#
CASH#
RAS0#
RAS#
16
OE#
12
DQ0-DQ31
32
DQ0-DQ31
A0-A11
WE#
WE#
U2
DQ16DQ31
CAS2#
CASL#
CAS3#
CASH#
RAS2#
RAS#
A0-A11
32
16
OE#
12
12
A0-A11
U3
WE#
CASL#
DQ0DQ15
16
CASH#
RAS1#
RAS#
OE#
12
A0-A11
WE#
U4
CASL#
DQ16DQ31
16
CASH#
RAS3#
RAS#
OE#
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
VDD
U1-U4
VSS
U1-U4
U1-U4 = MT4LC4M16R6TG (S) EDO PAGE MODE
U1-U4 = MT4LC4M16F5TG (S) FAST PAGE MODE
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
JEDEC-DEFINED
PRESENCE-DETECT – MT2LDT432H (X)(S) (16MB)
SYMBOL
PIN
-5
-6
PRD1
11
NC
NC
PRD2
66
NC
NC
PRD3
67
V SS
VSS
PRD4
68
NC
NC
PRD5
69
V SS
NC
PRD6
70
V SS
NC
PRD7
71
X*
X*
JEDEC-DEFINED
PRESENCE-DETECT – MT4LDT832H (X)(S) (32MB)
SYMBOL
PIN
-5
-6
PRD1
11
NC
NC
PRD2
66
NC
NC
PRD3
67
V SS
VSS
PRD4
68
V SS
VSS
PRD5
69
V SS
NC
PRD6
70
V SS
NC
PRD7
71
X*
X*
*X = NC (Normal Refresh) or VSS (Self Refresh)
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Voltage on VDD Supply
Relative to VSS ..................................... -1V to +4.6V
Voltage on Inputs or I/O Pins
Relative to VSS ................................. -1V to +4.6V
Operating Temperature, TA (ambient) .. 0°C to +70°C
Storage Temperature (plastic) ........... -55°C to +125°C
Power Dissipation ................................................... 4W
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
SIZE
MIN
MAX
SUPPLY VOLTAGE
VDD
ALL
3
3.6
V
INPUT HIGH VOLTAGE: Valid Logic 1; All inputs
VIH
ALL
2
VDD + 0.3
V
26
INPUT LOW VOLTAGE: Valid Logic 0; All inputs
VIL
ALL
-0.3
0.8
V
26
INPUT LEAKAGE CURRENT:
Any input at VIN (0V £ VIN £ VDD + 0.3V);
All other pins not under test = 0V
CAS0#-CAS3#
IIL1
16MB
32MB
-2
-4
2
4
µA
A0-A11, WE#
II2
16MB
32MB
-4
-8
4
8
µA
RAS0#-RAS3#
II3
16MB
32MB
-2
-2
2
2
µA
DQ0-DQ31
IOZ
16MB
32MB
-5
-10
5
10
µA
VOH
ALL
2.4
–
V
VOL
ALL
–
0.4
V
OUTPUT LEAKAGE CURRENT:
DQ is disabled; 0V £ VOUT £ VDD + 0.3V
OUTPUT LEVELS:
Output High Voltage (IOUT = -2mA)
Output Low Voltage (IOUT = 2mA)
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
6
UNITS NOTES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 5, 6) (VDD = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION
SYMBOL
SIZE
-5
-6
STANDBY CURRENT: TTL
(RAS# = CAS# = VIH)
IDD1
16MB
32MB
2
4
2
4
UNITS NOTES
mA
STANDBY CURRENT: CMOS
(RAS# = CAS# • VDD - 0.2V; DQs may be left open;
Other inputs: VIN • VDD - 0.2V or VIN £ 0.2V)
16MB
32MB
1
2
1
2
mA
IDD2
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
16MB
32MB
350
352
330
332
mA
3, 22
IDD3
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])
16MB
32MB
210
212
190
192
mA
3, 22
IDD4
IDD5
16MB
(X only) 32MB
310
312
250
252
mA
3, 22
OPERATING CURRENT: EDO PAGE MODE (“X” version only)
Average power supply current
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
16MB
32MB
350
352
330
332
mA
3, 22
IDD6
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
16MB
32MB
350
352
330
332
mA
3, 4
IDD7
IDD8
16MB
(S only) 32MB
0.8
1.6
0.8
1.6
mA
3, 4
REFRESH CURRENT: SELF (“S” version only)
Average power supply current: CBR with RAS# • tRASS
(MIN) and CAS# held LOW; WE# = VDD - 0.2V; A0-A11,
OE# and DIN = VDD - 0.2V or 0.2V (DIN may be left open)
CAPACITANCE
MAX
PARAMETER
SYMBOL 16MB
32MB UNITS NOTES
Input Capacitance: A0-A11
CI1
14
24
pF
2
Input Capacitance: WE#
CI2
18
32
pF
2
Input Capacitance: RAS0#-RAS3#
CI3
10
10
pF
2
Input Capacitance: CAS0#-CAS3#
CI4
10
18
pF
2
Input/Output Capacitance: DQ0-DQ31
CIO
10
18
pF
2
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 19) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
Access time from column address
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# LOW to “Don’t Care” during Self Refresh
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
CAS# precharge time (FAST PAGE MODE)
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output buffer turn-off delay
OE# setup prior to RAS# during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
-5
SYMBOL
tAA
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCHD
tCHR
tCLZ
tCP
tCPA
tCRP
tCSH
tCSR
tCWL
tDH
tDS
tOFF
tORD
tPC
tRAC
tRAD
8
MIN
-6
MAX
25
40
0
0
MIN
45
0
0
13
8
13
15
15
3
8
10,000
15
10
15
15
15
3
10
30
5
50
5
13
8
0
3
0
30
13
10,000
35
5
60
5
15
10
0
3
0
35
50
13
MAX
30
15
60
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
25
4
21
13
4
18
18
17, 21, 23
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 19) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
Row-address hold time
RAS# pulse width
RAS# pulse width (Self Refresh)
RAS# pulse width (FAST PAGE MODE)
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS#)
READ command setup time
Refresh period (4,096 cycles)
Refresh period “S” version
RAS# precharge time
RAS# to CAS# precharge time
RAS# precharge time (Self Refresh)
READ command hold time (referenced to RAS#)
RAS# hold time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
WRITE command pulse width
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
-5
SYMBOL
tRAH
tRAS
tRASS
tRASP
tRC
tRCD
tRCH
tRCS
tREF
tREF
tRP
tRPC
tRPS
tRRH
tRSH
tRWL
tT
tWCH
tWCR
tWCS
tWP
tWRH
tWRP
9
MIN
8
50
100
50
90
18
0
0
-6
MAX
10,000
125,000
MIN
10
60
100
60
110
20
0
0
64
128
30
0
90
0
13
13
2
8
40
0
8
10
10
50
MAX
10,000
125,000
64
128
40
0
105
0
15
15
2
10
45
0
10
10
10
50
UNITS
ns
ns
µs
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
25
14
16
25
25
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 19) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION
PARAMETER
Access time from column address
Column-address setup to CAS# precharge
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# LOW to “Don’t Care” during Self Refresh
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
Data output hold after next CAS# LOW
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output buffer turn-off delay
EDO-PAGE-MODE READ or WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (EDO PAGE MODE)
RAS# pulse width during Self Refresh
Random READ or WRITE cycle time
RAS# to CAS# delay time
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
-5
SYMBOL
tAA
tACH
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCHD
tCHR
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tCSR
tCWL
tDH
tDS
tOFF
tPC
tRAC
tRAD
tRAH
tRAS
tRASP
tRASS
tRC
tRCD
10
MIN
-6
MAX
25
12
38
0
0
MIN
15
45
0
0
13
8
8
15
8
0
3
8
10,000
15
10
10
15
10
0
3
10
28
5
38
5
8
8
0
0
20
12
10,000
125,000
10,000
35
5
45
5
10
10
0
0
25
50
9
9
50
50
100
84
11
MAX
30
15
60
12
10
60
60
100
104
14
10,000
125,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
NOTES
25
4
13
4
18
18
17, 23
15
25
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 19) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION
PARAMETER
READ command hold time (referenced to CAS#)
READ command setup time
Refresh period (4,096 cycles)
Refresh period “S” version
RAS# precharge time
RAS# to CAS# precharge time
RAS# precharge time exiting Self Refresh
READ command hold time (referenced to RAS#)
RAS# hold time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
Output disable delay from WE#
WRITE command pulse width
WE# pulse to disable at CAS# HIGH
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
-5
SYMBOL
tRCH
tRCS
tREF
tREF
tRP
tRPC
tRPS
tRRH
tRSH
tRWL
tT
tWCH
tWCR
tWCS
tWHZ
tWP
tWPZ
tWRH
tWRP
11
MIN
0
0
-6
MAX
MIN
0
0
64
128
30
5
90
0
13
13
2
8
38
0
0
5
10
8
8
50
12
MAX
64
128
40
5
105
0
15
15
2
10
45
0
0
5
10
10
10
50
15
UNITS
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
16
25
25
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
NOTES
by tCAC (tRAC [MIN] no longer applied). With or
without the tRCD (MAX) limit, tAA and tCAC
must always be met.
15.The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
tRAD was greater than the specified tRAD (MAX)
limit, then access time was controlled exclusively
by tAA (tRAC and tCAC no longer applied). With
or without the tRAD (MAX) limit, tAA, tRAC and
tCAC must always be met.
16.Either tRCH or tRRH must be satisfied for a READ
cycle.
17. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
18.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles.
19.OE# is tied permanently LOW; LATE WRITE or
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
20.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and OE#
= HIGH.
21.The 3ns minimum is a parameter guaranteed by
design.
22.Column address changed once each cycle.
23.With the FPM option, tOFF is determined by the
first RAS# or CAS# signal to transition HIGH. In
comparison, tOFF on an EDO option is determined by the latter of the RAS# and CAS# signals
to transition HIGH.
24.Applies to both FPM and EDO operating modes.
25.“S” version only.
26.VIH overshoot: VIH (MAX) = VDD + 2V for a pulse
width £ 10ns, and the pulse width cannot be
greater than one third of the cycle rate. VIL
undershoot: VIL (MIN) = -2V for a pulse width £
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD = +3.3V; f = 1 MHz.
3. IDD is dependent on output loading and cycle
rates. Specified values are obtained with minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range is ensured.
6. An initial pause of 100µs is required after powerup, followed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR with WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle wake-ups should be repeated any time the
tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 5ns for FPM and
tT = 2.5ns for EDO.
8. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
9. In addition to meeting the transition rate
specification, all input signals must transit between
VIH and VIL (or between VIL and VIH) in a monotonic manner.
10.For FPM: If CAS# = VIH, data output is High-Z.
For EDO: If CAS# and RAS# = VIH, data output is
High-Z.
11.If CAS# = VIL, data output may contain data from
the last valid READ cycle.
12.Measured with a load equivalent to two TTL gates
and 100pF, VOL = 0.8V and VOH = 2V.
13.If CAS# is LOW at the falling edge of RAS#, Q will
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for tCP.
14.The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
tRCD was greater than the specified tRCD (MAX)
limit, then access time was controlled exclusively
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
READ CYCLE 24
tRC
tRP
tRAS
RAS#
V IH
V IL
tCSH
tRSH
tRRH
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;; ; ;
; ;
;
;; ;;;
tCRP
CAS#
tCAS
tAR
tASC
tCAH
V IH
V IL
tRAD
tRAH
tASR
ADDR
tRCD
V IH
V IL
tACH
ROW
ROW
COLUMN
tRCH
tRCS
WE#
V IH
V IL
tAA
tRAC
NOTE 1
tOFF
tCAC
tCLZ
DQ
V OH
V OL
OPEN
OPEN
VALID DATA
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH (EDO)
tAR (EDO)
tAR (FPM)
tASC
tASR
MIN
-6
MIN
12
38
40
15
45
45
0
0
0
0
ns
ns
tRAH
ns
ns
ns
tRAS
ns
ns
tRCD
13
tCAH
-5
UNITS
ns
ns
ns
ns
tCAC
MAX
25
MAX
30
15
tRAH
(EDO)
(FPM)
tCLZ (EDO)
13
0
tCLZ (FPM)
3
5
45
ns
ns
ns
tRCH
(EDO)
3
5
38
(FPM)
tOFF (EDO)
50
0
60
0
ns
ns
tRRH
tCAS
tCRP
tCSH
tCSH
10,000
10,000
12
15
0
10,000
10,000
15
(EDO)
(FPM)
tRC
(FPM)
tRCD
tRCS
tRP
tRSH
MIN
3
(EDO)
(FPM)
-6
9
13
12
15
UNITS
ns
ns
ns
ns
9
8
10
10
ns
ns
50
84
90
tRC (EDO)
8
8
tCAS
10
10
SYMBOL
tOFF (FPM)
tRAC
tRAD (EDO)
tRAD (FPM)
MAX
13
50
10,000
MIN
3
60
104
110
MAX
15
60
10,000
ns
ns
ns
11
18
14
20
ns
ns
0
0
30
0
0
40
ns
ns
ns
0
13
0
15
ns
ns
NOTE: 1. For EDO, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM, tOFF is referenced from
rising edge of RAS# or CAS#, whichever occurs first.
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
EARLY WRITE CYCLE 24
tRC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
;
;
;
;
;
;
;
;; ; ; ; ;
;
;
;
;
;
;;;;;;;;;; ;; ;;;;;;
; ;; ; ;;;; ;;;;
;;
tCRP
CAS#
tCAS
tAR
tASC
tCAH
V IH
V IL
tRAD
tASR
ADDR
tRCD
V IH
V IL
tACH
tRAH
ROW
ROW
COLUMN
tCWL
tRWL
tWCR
tWCH
tWCS
tWP
WE#
V IH
V IL
tDS
V
DQ V IOH
IOL
tDH
VALID DATA
DON’T CARE
;;
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tACH (EDO)
tAR
(EDO)
(FPM)
tASC
tAR
tASR
tCAH
tCAS
MIN
12
-6
MAX
MIN
15
-5
MAX
UNITS
ns
SYMBOL
tRAD (EDO)
0
8
0
10
ns
ns
tRC
(FPM)
tRC (EDO)
90
84
110
104
ns
ns
ns
ns
ns
tRCD
18
11
30
20
14
40
ns
ns
ns
13
13
15
15
ns
ns
8
38
40
10
45
45
ns
ns
ns
tWP (FPM)
0
8
0
10
ns
ns
tWP (EDO)
5
5
ns
tRSH
tCWL
13
8
8
15
10
10
ns
ns
ns
tWCH
0
13
0
15
ns
ns
tWCS
tDS
tRAD
(FPM)
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
15
10
5
10,000
10,000
tRAS
ns
ns
tDH
10,000
10,000
(EDO)
(FPM)
tRAH
60
45
(FPM)
UNITS
ns
tRAH
50
38
tCWL (EDO)
MAX
ns
ns
ns
(FPM)
tCSH (EDO)
tCSH
MIN
12
45
45
0
13
8
5
tCRP
-6
MAX
38
40
0
(FPM)
(EDO)
tCAS
MIN
9
tRCD
(FPM)
(EDO)
tRP
tRWL
tWCR
(EDO)
tWCR (FPM)
14
9
8
50
10,000
10
10
60
10,000
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
FAST-PAGE-MODE READ CYCLE
tRASP
RAS#
tRP
V IH
V IL
tCSH
tPC
tCP
tRSH
tCAS
;
;
;
;
;
;
;
;;; ;; ; ;; ;; ; ;;;;
;
;
;
;
;
;; ;
;
;
; ;
; ; ;;
; ; ;;;
;
tCRP
CAS#
tRCD
tCAS
tCAS
tCP
tCP
V IH
V IL
tAR
tRAD
tRAH
tASR
ADDR
V IH
V IL
tASC
ROW
tCAH
COLUMN
tRCS
WE#
tASC
tCAH
COLUMN
tCAH
COLUMN
tRCS
tRCH
tRCH
ROW
tRCS
tRRH
tRCH
V IH
V IL
tAA
tRAC
tAA
tCPA
tCAC
tOFF
tCLZ
DQ
tASC
V IOH
V IOL
tCAC
tAA
tCPA
tOFF
tCLZ
VALID
DATA
OPEN
tCAC
tOFF
tCLZ
VALID
DATA
VALID
DATA
OPEN
DON’T CARE
UNDEFINED
FAST PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
tAR
40
0
tASR
0
tCAC
tCAS
tCLZ
tCP
8
13
3
tCSH
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
UNITS
30
ns
ns
ns
0
10,000
8
15
10
15
3
10,000
10
30
5
50
-5
MAX
45
0
13
tCPA
tCRP
MIN
25
tASC
tCAH
-6
MAX
35
5
60
SYMBOL
tOFF
tPC
MIN
3
30
tRAC
ns
ns
tRAD
ns
ns
ns
tRASP
ns
ns
tRCS
ns
ns
tRAH
tRCD
MIN
3
UNITS
ns
60
ns
ns
125,000
ns
ns
ns
35
50
13
8
50
MAX
15
125,000
15
10
60
18
0
20
0
ns
ns
tRRH
0
30
0
0
40
0
ns
ns
ns
tRSH
13
15
ns
tRCH
tRP
15
-6
MAX
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
EDO-PAGE-MODE READ CYCLE
tRASP
RAS#
tRP
V IH
V IL
tCSH
tPC
tCP
tRSH
tCAS
;; ; ;;; ;; ;;;;
;
;
; ;;
;
;
;
;;;;;
;
; ; ;;;;;
;
tCRP
CAS#
tRCD
tCAS
tCP
tCP
V IH
V IL
V IH
V IL
tAR
tACH
tRAD
tRAH
tASR
ADDR
tCAS
tASC
ROW
tACH
tASC
tCAH
COLUMN
tCAH
tACH
tASC
COLUMN
tCAH
COLUMN
ROW
tRCH
tRCS
WE#
V IH
V IL
tAA
tRAC
tAA
tCPA
tCAC
tCAC
V OH
V OL
tCAC
tCLZ
tOFF
tCOH
tCLZ
DQ
tRRH
tAA
tCPA
VALID
DATA
OPEN
VALID
DATA
VALID
DATA
OPEN
DON’T CARE
UNDEFINED
EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
tAR
tASC
tASR
MIN
tCAS
tCLZ
MIN
-5
12
38
0
15
45
0
0
0
ns
tRAD
9
12
ns
ns
ns
tRAH
9
50
11
10
60
14
13
8
8
10,000
MAX
30
15
10
10
10,000
SYMBOL
tCSH
tOFF
tPC
tRAC
tRASP
tRCD
0
3
ns
ns
tRCH
tCOH
0
3
tCP
8
10
ns
ns
ns
tRP
tCPA
tCRP
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
28
5
35
5
tRCS
tRRH
tRSH
16
MIN
38
0
20
-6
UNITS
ns
ns
ns
ns
tCAC
tCAH
-6
MAX
25
MAX
12
MIN
45
0
25
50
125,000
MAX
15
60
UNITS
ns
ns
ns
ns
ns
125,000
ns
ns
ns
0
0
0
0
ns
ns
30
0
13
40
0
15
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
FAST/EDO-PAGE-MODE EARLY WRITE CYCLE 24
tRP
tRASP
RAS#
V IH
V IL
tCSH
tCRP
CAS#
tRCD
tPC
tCP
tCAS
tCAS
tRSH
tCAS
tCP
V IH
V IL
tACH
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tACH
tASC
ROW
tACH
tASC
tCAH
COLUMN
tCAH
tASC
COLUMN
tCWL
tWCH
tWCS
tWCS
tCAH
COLUMN
tCWL
tWCH
tWP
WE#
tCP
ROW
tCWL
tWCH
tWCS
tWP
tWP
V IH
V IL
tWCR
tDS
V
DQ V IOH
IOL
tRWL
tDH
tDS
VALID DATA
tDH
tDS
VALID DATA
tDH
VALID DATA
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tACH (EDO)
tAR
(EDO)
(FPM)
tASC
tAR
tASR
tCAH
tCAS
MIN
12
-6
MAX
MIN
15
-5
MAX
UNITS
ns
SYMBOL
tPC (FPM)
tRAD (EDO)
tRAD (FPM)
tRAH
(EDO)
9
10
ns
0
10
ns
ns
tRAH
(FPM)
ns
ns
ns
tRCD
(EDO)
8
50
11
10
60
14
ns
ns
ns
tRCD
(FPM)
ns
ns
tRSH
50
8
13
60
10
15
ns
ns
ns
tWCH
8
0
10
0
ns
ns
tWCS
20
25
ns
tWP (FPM)
tCWL
(FPM)
tDH
tDS
tPC (EDO)
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
10,000
10,000
10
15
10
10,000
10,000
tRASP
5
45
(FPM)
UNITS
ns
ns
ns
0
8
5
38
tCWL (EDO)
MAX
ns
ns
ns
tCRP
tCSH
MIN
35
12
15
45
45
0
8
13
8
(EDO)
-6
MAX
38
40
0
(EDO)
tCAS (FPM)
tCP
tCSH
MIN
30
9
13
tRP
tRWL
tWCR
tWCR
(EDO)
(FPM)
tWP (EDO)
17
125,000
125,000
18
30
20
40
ns
ns
13
13
8
15
15
10
ns
ns
ns
38
40
45
45
ns
ns
0
5
8
0
5
10
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t RP
t RASP
RAS#
V IH
V IL
t CSH
tPC
tCRP
CAS#
t RCD
tRSH
tPC
t CP
t CAS
t CP
t CAS
t CP
t CAS
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
t ACH
tRAH
tASC
ROW
tCAH
t ASC
COLUMN (A)
t CAH
COLUMN (B)
V IH
V IL
ROW
tWCS
tWCH
tAA
tAA
tCPA
tRAC
tCAC
tCAC
tCOH
DQ V IOH
V IOL
t CAH
COLUMN (N)
tRCH
tRCS
WE#
tASC
OPEN
VALID DATA (A)
t DS
t DH
t WHZ
VALID
DATA (B)
VALID DATA
IN
DON’T CARE
UNDEFINED
EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
-6
12
15
45
0
ns
ns
tRAC
tASC
38
0
tRAD
9
tASR
0
ns
ns
ns
tRAH
9
50
11
ns
ns
tRCH
tRP
tCAC
MAX
25
MIN
-5
UNITS
ns
ns
tAR
MIN
0
13
tCAH
8
tCAS
tCOH
8
3
tCP
8
MAX
30
15
10
10,000
10
3
10,000
tRASP
tRCD
tRCS
MIN
0
20
125,000
10
60
14
125,000
ns
ns
ns
ns
ns
ns
38
45
ns
tWCS
0
8
10
ns
tWHZ
0
18
ns
ns
40
15
10
tDH
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
60
12
30
13
8
5
tWCH
UNITS
ns
ns
ns
ns
5
tRSH
MAX
0
0
tCSH
35
MIN
0
25
0
0
tCRP
28
-6
MAX
50
ns
ns
ns
tCPA
10
SYMBOL
tDS
tPC
0
12
0
ns
15
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
FAST-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
tRASP
tRP
V IH
V IL
RAS#
tRSH
tCSH
tCRP
tPC
tRCD
tCAS
tCP
tCAS
tCP
V IH
V IL
CAS#
tAR
tRAD
tASR
V IH
V IL
ADDR
ROW
tASC
tCAH
tASC
tRAH
COLUMN
ROW
COLUMN
tCWL
tRWL
tRCS
tWCS
tWP
tWCH
V IH
V IL
WE#
tCAC
NOTE 1
t OFF
tDS
t CLZ
DQ
tCAH
V OH
V OL
VALID
DATA
OPEN
tDH
VALID DATA
tAA
tRAC
DON’T CARE
UNDEFINED
FAST PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
tAR
tASC
tASR
40
0
0
8
tCAS
13
3
8
tCRP
tCSH
tCWL
tDH
tDS
-5
MAX
UNITS
30
ns
tOFF
ns
ns
ns
tPC
15
ns
ns
tRAH
10,000
ns
ns
ns
tRCD
45
0
0
13
tCAH
tCP
MIN
25
tCAC
tCLZ
-6
MAX
10
10,000
15
3
10
SYMBOL
MAX
MIN
MAX
UNITS
3
13
3
15
ns
60
ns
ns
125,000
ns
ns
ns
30
tRAC
tRAD
tRASP
tRCS
tRP
-6
MIN
35
50
13
8
50
125,000
15
10
60
18
0
20
0
ns
ns
40
15
15
ns
ns
ns
5
50
5
60
ns
ns
tRSH
tRWL
30
13
13
13
8
0
15
10
0
ns
ns
ns
tWCH
8
10
ns
tWCS
0
8
0
10
ns
ns
tWP
NOTE: 1. Do not drive input data prior to output data going High-Z.
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
EDO READ CYCLE
(with WE#-controlled disable)
RAS#
V IH
V IL
CAS#
tCSH
tCAS
tRCD
tCRP
tCP
V IH
V IL
tAR
tRAD
tRAH
tASR
ADDR
V IH
V IL
tASC
ROW
tCAH
tASC
COLUMN
COLUMN
tRCH
tRCS
WE#
tWPZ
tRCS
V IH
V IL
tAA
tRAC
tCAC
tCLZ
DQ
V OH
V OL
tWHZ
OPEN
tCLZ
OPEN
VALID DATA
DON’T CARE
UNDEFINED
EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
MIN
-6
MAX
25
MIN
-5
MAX
30
UNITS
ns
SYMBOL
tCSH
MIN
38
-6
MAX
MIN
45
MAX
UNITS
ns
60
38
0
45
0
ns
ns
tRAC
tASC
tRAD
9
12
ns
ns
tASR
0
0
ns
ns
ns
tRAH
9
11
0
10
14
0
ns
ns
ns
ns
ns
tRCS
tWHZ
0
0
ns
ns
tWPZ
10
tCAC
13
tCAH
8
tCAS
8
0
tCLZ
tCP
tCRP
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
8
5
15
10
10,000
10
0
10
5
10,000
tRCD
tRCH
20
50
12
0
0
10
15
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
RAS#-ONLY REFRESH CYCLE24
(OE# and WE# = DON’T CARE)
tRC
tRAS
RAS#
tRP
V IH
V IL
tRPC
tCRP
CAS#
V IH
V IL
tASR
ADDR
V IH
V IL
tRAH
ROW
ROW
V
DQ V OH
OL
OPEN
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tASR
tCRP
tCSR
tRAH (EDO)
tRAH (FPM)
tRAS
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
MIN
0
5
5
9
8
50
-6
MAX
10,000
MIN
0
5
5
10
10
60
-5
MAX
10,000
UNITS
ns
ns
ns
ns
ns
ns
SYMBOL
tRC (FPM)
tRC (EDO)
tRP
tRPC (FPM)
tRPC (EDO)
21
MIN
90
84
30
0
5
-6
MAX
MIN
110
104
40
0
5
MAX
UNITS
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
SELF REFRESH CYCLE 24, 25
(Addresses = DON’T CARE)
RAS#
V IH
V IL
tRPS
((
))
tRPC
tCP
CAS#
NOTE 1
tRASS
tRP
tRPC
((
))
tCSR
NOTE 2
((
))
tCP
tCHD
((
))
((
))
V IH
V IL
V
DQ V OH
OL
((
))
tWRP
OPEN
tWRP
tWRH
tWRH
((
))
((
))
V
WE# V IH
IL
CBR REFRESH CYCLE 24
(Addresses = DON’T CARE)
tRP
RAS#
tRAS
tRP
tRAS
V IH
V IL
tRPC
tCP
CAS#
tRPC
tCHR
tCSR
tCHR
V IH
V IL
V OH
DQ V OL
OPEN
tWRP
WE#
tCSR
tWRH
tWRP
tWRH
V IH
V IL
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tCHD
tCHR
(FPM)
tCHR
(EDO)
tCP
tCSR
tRAS
tRASS
tRP
MIN
-6
MAX
MIN
-5
MAX
UNITS
SYMBOL
MIN
-6
MAX
MIN
MAX
UNITS
15
15
15
15
ns
ns
tRPC
0
5
0
5
ns
ns
8
8
5
10
10
5
ns
ns
ns
tRPS
90
10
8
105
10
10
ns
ns
ns
ns
µs
tWRP (FPM)
10
8
10
10
ns
ns
50
100
30
10,000
60
100
40
10,000
(FPM)
tRPC (EDO)
tWRH
(FPM)
tWRH (EDO)
tWRP (EDO)
ns
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
HIDDEN REFRESH CYCLE 20, 24
(WE# = HIGH)
tRC
tRAS
RAS#
tRAS
V IH
V IL
tCRP
CAS#
tRP
tRSH
tRCD
tCHR
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
COLUMN
tAA
tRAC
tOFF
tCAC
tCLZ
V
DQ V OH
OL
OPEN
VALID DATA
OPEN
DON’T CARE
UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR (EDO)
tAR
(FPM)
tASC
tASR
MIN
MIN
45
45
ns
0
0
0
0
ns
ns
ns
(EDO)
tCHR
(FPM)
tCLZ (EDO)
tCLZ (FPM)
tCRP
tOFF (EDO)
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
15
SYMBOL
tOFF (FPM)
tRAC
tRAD (EDO)
tRAD (FPM)
UNITS
ns
ns
40
13
tCHR
MAX
30
38
tCAC
tCAH
-5
-6
MAX
25
tRAH
tRAH
8
8
10
10
ns
ns
tRAS
15
0
3
15
0
3
ns
ns
ns
tRC
5
0
5
0
ns
ns
tRP
12
15
(EDO)
(FPM)
(FPM)
tRCD
tRSH
23
(EDO)
(FPM)
-6
9
13
12
15
UNITS
ns
ns
ns
ns
9
8
10
10
ns
ns
50
84
90
tRC (EDO)
tRCD
MIN
3
MAX
13
50
10,000
MIN
3
60
104
110
MAX
15
60
10,000
ns
ns
ns
11
18
14
20
ns
ns
30
13
40
15
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
72-PIN SODIMM
(4 Meg x 32)
FRONT VIEW
2.355 (59.82)
2.345 (59.56)
.100 (2.54)
MAX
.079 (2.00) R
(3X)
.071 (1.80)
(2X)
.700 (17.78)
TYP
1.005 (25.53)
.995 (25.27)
.125 (3.18)
.043 (1.10)
.035 (0.90)
.071 (1.80) TYP
.079 (2.00)
.197 (5.00)
PIN 1
.040 (1.02)
TYP
.050 (1.27)
TYP
PIN 71 (PIN 72 on backside)
1.750 (44.45)
2.034 (51.66)
72-PIN SODIMM
(8 Meg x 32)
FRONT VIEW
2.355 (59.82)
2.345 (59.56)
.150 (3.80)
MAX
.079 (2.00) R
(3X)
.071 (1.80)
(2X)
.700 (17.78)
TYP
1.005 (25.53)
.995 (25.27)
.125 (3.18)
.043 (1.10)
.035 (0.90)
.071 (1.80) TYP
.079 (2.00)
.197 (5.00)
PIN 1
.040 (1.02)
TYP
.050 (1.27)
TYP
PIN 71 (PIN 72 on backside)
1.750 (44.45)
2.034 (51.66)
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.