ONSEMI NCP1612

NCP1612
Enhanced, High-Efficiency
Power Factor Controller
The NCP1612 is designed to drive PFC boost stages based on an
innovative Current Controlled Frequency Fold−back (CCFF)
method. In this mode, the circuit classically operates in Critical
conduction Mode (CrM) when the inductor current exceeds a
programmable value. When the current is below this preset level, the
NCP1612 linearly decays the frequency down to about 20 kHz when
the current is null. CCFF maximizes the efficiency at both nominal
and light load. In particular, the stand−by losses are reduced to a
minimum.
Like in FCCrM controllers, an internal circuitry allows near−unity
power factor even when the switching frequency is reduced. Housed in
a SO−10 package, the circuit also incorporates the features necessary
for robust and compact PFC stages, with few external components.
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MARKING
DIAGRAM
10
SOIC−10
CASE 751BQ
10
1
1
1612x
General Features
A
L
Y
W
G
• Near−Unity Power Factor
• Critical Conduction Mode (CrM)
• Current Controlled Frequency Fold−back (CCFF): Low Frequency
1612x
ALYW
G
= Specific Device Code
x = A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Operation is Forced at Low Current Levels
• On−time Modulation to Maintain a Proper Current Shaping in CCFF
•
•
•
•
•
•
•
•
•
•
Mode
Skip Mode Near the Line Zero Crossing
Fast Line / Load Transient Compensation (Dynamic Response
Enhancer)
Valley Turn On
High Drive Capability: −500 mA/+800 mA
VCC Range: from 9.5 V to 35 V
Low Start−up Consumption
A Version: Low VCC Start−up Level (10.5 V), B Version: High VCC
Start−up Level (17.0 V)
Line Range Detection
pfcOK Signal
This is a Pb−Free Device
Safety Features
• Separate Pin for Fast Over−Voltage Protection (FOVP)
•
•
•
•
•
•
June, 2012 − Rev. 1
FOVP/BUV
Feedback
1
pfcOK
VCC
Vcontrol
DRV
Vsense
GND
CS/ZCD
FFcontrol
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 29 of this data sheet.
• Latched Off Capability
• Low Duty−Cycle Operation if the Bypass Diode is
and Bulk Under−Voltage Detection (BUV)
Soft Over−Voltage Protection
Brown−Out Detection
Soft−Start for Smooth Start−up Operation (A version)
Over Current Limitation
Disable Protection if the Feedback and FOVP/BUV
pins are not connected
Thermal Shutdown
© Semiconductor Components Industries, LLC, 2012
PIN CONNECTIONS
shorted
• Open Ground Pin Fault Monitoring
Typical Applications
• PC Power Supplies
• All Off Line Appliances Requiring Power Factor
Correction
1
Publication Order Number:
NCP1612/D
NCP1612
Figure 1. Typical Application Schematic
MAXIMUM RATINGS TABLE
Symbol
Pin
Rating
Value
Unit
VCC
9
Power Supply Input
−0.3, + 35
V
Vi
1, 2, 4,
5, 10
Input Voltage (Note 1)
−0.3, +9
V
Vi(CS/ZCD)
6
Input Voltage
−0.3, VCL(pos)*
V
VCONTROL
3
VCONTROL pin
−0.3, VCONTROLMAX*
V
DRV
8
Driver Voltage
Driver Current
−0.3, VDRV*
−500, +800
V
mA
PD
RqJA
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance Junction−to−Air
550
145
mW
°C/W
TJ
Operating Junction Temperature Range
−40 to +125
°C
TJmax
Maximum Junction Temperature
150
°C
TSmax
Storage Temperature Range
−65 to 150
°C
TLmax
Lead Temperature (Soldering, 10s)
300
°C
MSL
Moisture Sensitivity Level
1
−
ESD Capability, Human Body Model (Note 2)
> 2000
V
ESD Capability, Machine Model (Note 2)
> 200
V
ESD Capability, Charged Device Model (Note 2)
2000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*“VCL(pos)“ is the CS/ZCD pin positive clamp voltage. “VCONTROLMAX” is the VCONTROL pin clamp voltage. “VDRV” is the DRV clamp voltage
(VDRVhigh) if this clamp voltage is below VCC. “VDRV” is VCC otherwise.
1. When the applied voltage exceeds 5 V, these pins sink about
V1 * 5 V
4 kW
that is about 1.25 mA if VI = 9 V
2. This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
Charged Device Model Method 200 V per JEDEC Standard JESD22−C101E
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1612
TYPICAL ELECTRICAL CHARACTERISTICS (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified)
Symbol
Rating
Min
Typ
Max
VCC(on)
Start−Up Threshold, VCC increasing:
A version
B version
9.75
15.80
10.50
17.00
11.25
18.20
Unit
START−UP AND SUPPLY CIRCUIT
V
VCC(off)
Minimum Operating Voltage, VCC falling
8.5
9.0
9.5
VCC(HYST)
Hysteresis (VCC (on ) − VCC (off ))
A version
B version
V
0.75
6.00
1.50
8.00
−
−
VCC(reset)
VCC level below which the circuit resets
2.5
4.0
6.0
V
ICC(start)
Start−Up Current, VCC = 9.4 V
−
20
50
mA
ICC(op)1
Operating Consumption, no switching (VSENSE pin being grounded)
−
0.5
1.0
mA
ICC(op)2
Operating Consumption, 50 kHz switching, no load on DRV pin
−
2.0
3.0
mA
V
CURRENT CONTROLLED FREQUENCY FOLD−BACK
TDT1
Dead−Time, VFFcontrol = 2.60 V (Note 4)
−
−
0
ms
TDT2
Dead−Time, VFFcontrol = 1.75 V
14
18
22
ms
TDT3
Dead−Time, VFFcontrol = 1.00 V
32
38
44
ms
IDT1
FFcontrol Pin current, Vsense = 1.4 V and Vcontrol maximum
180
200
220
mA
IDT2
FFcontrol Pin current, Vsense = 2.8 V and Vcontrol maximum
110
135
160
mA
VSKIP−H
FFcontrol pin Skip Level, VFFcontrol rising
−
0.75
0.85
V
VSKIP−L
FFcontrol pin Skip Level, VFFcontrol falling
0.55
0.65
−
V
VSKIP−L
FFcontrol pin Skip Hysteresis
50
−
−
mV
TR
Output voltage rise−time @ CL = 1 nF, 10−90% of output signal
−
30
−
ns
TF
Output voltage fall−time @ CL = 1 nF, 10−90% of output signal
−
20
−
ns
ROH
Source resistance
−
10
−
W
ROL
Sink resistance
−
7.0
−
W
ISOURCE
Peak source current, VDRV = 0 V (guaranteed by design)
−
500
−
mA
ISINK
Peak sink current, VDRV = 12 V (guaranteed by design)
−
800
−
mA
VDRVlow
DRV pin level at VCC close to VCC (off ) with a 10 kW resistor to GND
8.0
−
−
V
VDRVhigh
DRV pin level at VCC = 35 V (RL = 33 kW, CL = 220 pF)
10
12
14
V
VREF
Feedback Voltage Reference:
@ 25°C
Over the temperature range
2.44
2.42
2.50
2.50
2.54
2.54
GATE DRIVE
REGULATION BLOCK
V
IEA
Error Amplifier Current Capability
−
±20
−
mA
GEA
Error Amplifier Gain
110
220
290
mS
VCONTROL
−VCONTROLMAX
−VCONTROLMIN
VCONTROL Pin Voltage:
− @ VFB = 2 V
− @ VFB = 3 V
−
−
4.5
0.5
−
−
V
VOUTL / VREF
Ratio (VOUT Low Detect Threshold / VREF ) (guaranteed by design)
95.0
95.5
96.0
%
HOUTL / VREF
Ratio (VOUT Low Detect Hysteresis / VREF ) (guaranteed by design)
−
−
0.5
%
IBOOST
VCONTROL Pin Source Current when (VOUT Low Detect) is activated
180
220
250
mA
4. There is actually a minimum dead−time that is the delay between the core reset detection and the DRV turning on (TZCD parameter of the
“Current Sense and Zero Current Detection Blocks” section).
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NCP1612
TYPICAL ELECTRICAL CHARACTERISTICS (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified)
Symbol
Rating
Min
Typ
Max
Unit
CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS
VCS(th)
Current Sense Voltage Reference
450
500
550
mV
TLEB,OCP
Over−Current Protection Leading Edge Blanking Time (guaranteed by design)
100
200
350
ns
TLEB,OVS
“OverStress” Leading Edge Blanking Time (guaranteed by design)
50
100
170
ns
TOCP
Over−Current Protection Delay from VCS/ZCD > VCS(th) to DRV low
(dVCS/ZCD / dt = 10 V/ms)
−
40
200
ns
VZCD(th)H
Zero Current Detection, VCS/ZCD rising
675
750
825
mV
VZCD(th)L
Zero Current Detection, VCS/ZCD falling
200
250
300
mV
VZCD(hyst)
Hysteresis of the Zero Current Detection Comparator
375
500
−
mV
RZCD/CS
VZCD(th)H over VCS(th) Ratio
1.4
1.5
1.6
−
VCL(pos)
CS/ZCD Positive Clamp @ ICS/ZCD = 5 mA
−
15.6
−
V
IZCD(bias)
Current Sourced by the CS/ZCD Pin, VCS/ZCD = VZCD (th )H
0.5
−
2.0
mA
IZCD(bias)
Current Sourced by the CS/ZCD Pin, VCS/ZCD = VZCD (th )L
0.5
−
2.0
mA
TZCD
(VCS/ZCD < VZCD (th )L ) to (DRV high)
−
60
200
ns
TSYNC
Minimum ZCD Pulse Width
−
110
200
ns
TWDG
Watch Dog Timer
80
200
320
ms
TWDG(OS)
Watch Dog Timer in “Overstress” Situation
400
800
1200
ms
TTMO
Time−Out Timer
20
30
50
ms
IZCD(gnd)
Source Current for CS/ZCD pin impedance Testing
−
250
−
mA
Duty Cycle, VFB = 3 V, Vcontrol pin open
−
−
0
%
TON(LL)
Maximum On Time, Vsense = 1.4 V and Vcontrol maximum (CrM)
22.0
25.0
29.0
ms
TON(LL)2
On Time, Vsense = 1.4 V and Vcontrol = 2.5 V (CrM)
10.5
12.5
14.0
ms
TON(HL)
Maximum On Time, Vsense = 2.8 V and Vcontrol maximum (CrM)
7.3
8.5
9.6
ms
TON(LL)(MIN)
Minimum On Time, Vsense = 1.4 V (not tested, guaranteed by characterization)
−
−
200
ns
TON(HL)(MIN)
Minimum On Time, Vsense = 2.8 V (not tested, guaranteed by characterization)
−
−
100
ns
Ratio (soft OVP Threshold, VFB rising) over VREF (VsoftOVP /VREF ) (guaranteed
by design)
104
105
106
%
RsoftOVP(HYST)
Ratio (Soft OVP Hysteresis) over VREF (guaranteed by design)
1.5
2.0
2.5
%
RUVP
Ratio (UVP Threshold, VFB rising) over VREF (VUVP /VREF ) (guaranteed by
design)
8
12
16
%
RUVP(HYST)
Ratio (UVP Hysteresis) over VREF (guaranteed by design)
−
−
1
%
(IB)FB
FB Pin Bias Current @ VFB = VsoftOV P and VFB = VUVP
50
200
450
nA
STATIC OVP
DMIN
ON−TIME CONTROL
FEED−BACK OVER AND UNDER−VOLTAGE PROTECTION (SOFT OVP AND UVP)
RsoftOVP
FAST OVER VOLTAGE PROTECTION AND BULK UNDER−VOLTAGE PROTECTION (FAST OVP AND BUV)
VfastOVP
Latching Fast OVP Threshold, VFOVP/BUV rising
−
2.7
−
V
RfastOVP1
Ratio (Fast OVP Threshold, VFOVP /BUV rising) over (soft OVP Threshold,
VFB rising) (VfastOVP /VsoftOVP ) (guaranteed by design)
101.5
102.0
102.5
%
RfastOVP2
Ratio (Fast OVP Threshold, VFOVP /BUV rising) over VREF (VfastOVP /VREF )
(guaranteed by design)
106
107
108
%
VBUV
BUV Threshold, VFOVP /BUV falling
−
1.9
−
V
4. There is actually a minimum dead−time that is the delay between the core reset detection and the DRV turning on (TZCD parameter of the
“Current Sense and Zero Current Detection Blocks” section).
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NCP1612
TYPICAL ELECTRICAL CHARACTERISTICS (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified)
Symbol
Rating
Min
Typ
Max
Unit
FAST OVER VOLTAGE PROTECTION AND BULK UNDER−VOLTAGE PROTECTION (FAST OVP AND BUV)
RBUV
Ratio (BUV Threshold, VFOVP /BUV falling) over VREF (VBUV /VREF )
(guaranteed by design)
74
76
78
%
(IB)FOVP/BUV
FOVP/BUV Pin Bias Current @ VFOVP /BUV = VfastOVP and VFOVP /BUV = VBUV
50
200
450
nA
VUVP2
Threshold for Floating Pin Detection
0.2
0.3
0.4
V
BROWN−OUT PROTECTION AND FEED−FORWARD
VBOH
Brown−Out Threshold, Vsense rising
0.96
1.00
1.04
V
VBOL
Brown−Out Threshold, Vsense falling
0.86
0.90
0.94
V
VBO(HYST)
Brown−Out Comparator Hysteresis
60
100
−
mV
TBO(blank)
Brown−Out Blanking Time
35
50
65
ms
ICONTROL(BO)
VCONTROL Pin Sink Current, Vsense < VBOL
40
50
60
mA
VHL
High−Line Detection Comparator Threshold, Vsense rising
2.1
2.2
2.3
V
VLL
High−Line Detection Comparator Threshold, Vsense falling
1.6
1.7
1.8
V
VHL(hyst)
High−Line Detection Comparator Hysteresis
400
500
600
mV
THL(blank)
Blanking Time for Line Range Detection
15
25
35
ms
IBO(bias)
Brown−Out Pin Bias Current, Vsense = VBO
−250
−
250
nA
(VpfcOK)L
pfcOK low state voltage @ IpfcOK = 5 mA
−
−
250
mV
VSTDWN
Shutdown Threshold Voltage
7.0
7.5
8.0
V
RpfcOK
Impedance of the pfcOK pin
150
300
−
kW
TLIMIT
Thermal Shutdown Threshold
−
150
−
°C
HTEMP
Thermal Shutdown Hysteresis
−
50
−
°C
pfcOK SIGNAL
THERMAL SHUTDOWN
4. There is actually a minimum dead−time that is the delay between the core reset detection and the DRV turning on (TZCD parameter of the
“Current Sense and Zero Current Detection Blocks” section).
DETAILED PIN DESCRIPTION
Pin Number
1
2
Name
Function
FOVP / BUV
Vpin1 is the input signal for the Fast Over−Voltage (FOVP) and Bulk Under−Voltage (BUV)
comparators. The circuit disables the driver if Vpin1 exceeds the FOVP threshold which is set
2% higher than the reference for the soft OVP comparator (that monitors the feedback pin) so
that pins 1 and 2 can receive the same portion of the output voltage.
The BUV comparator trips when Vpin 1 drops below 76% of the 2.5 V reference voltage to
disable the driver and ground the pfcOK pin. The BUV function has no action whenever the
pfcOK pin is in low state. As a matter of fact, pin1 monitors the output voltage and checks if it
is high enough for proper operation of the downstream converter.
A 250 nA sink current is built−in to ground the pin and disable the driver if the pin is
accidentally open.
Feedback
This pin receives a portion of the PFC output voltage for the regulation and the Dynamic
Response Enhancer (DRE) that drastically speeds−up the loop response when the output
voltage drops below 95.5% of the desired output level.
Vpin2 is also the input signal for the Over−Voltage (OVP) and Under−Voltage (UVP)
comparators. The UVP comparator prevents operation as long as Vpin2 is lower than 12% of
the reference voltage (VREF). A soft OVP comparator gradually reduces the duty−ratio to zero
when Vpin2 exceeds 105% of VREF (soft OVP).
A 250 A sink current is built−in to trigger the UVP protection and disable the part if the
feedback pin is accidentally open.
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NCP1612
DETAILED PIN DESCRIPTION
Pin Number
3
4
5
Name
Function
VCONTROL
The error amplifier output is available on this pin. The network connected between this pin and
ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high
Power Factor ratios.
Pin 3 is grounded when the circuit is off so that when it starts operation, the power increases
slowly to provide a soft−start function.
VSENSE
A portion of the instantaneous input voltage is to be applied to pin4 in order to detect
brown−out conditions. If Vpin 4 is lower than 1 V for more than 50 ms, the circuit stops pulsing
until the pin voltage rises again and exceeds 1 V.
This pin also detects the line range. By default, the circuit operates the “low−line gain” mode. If
Vpin 4 exceeds 1.8 V, the circuit detects a high−line condition and reduces the loop gain by 3.
Conversely, if the pin voltage remains lower than 1.8 V for more than 25 ms, the low−line gain
is set.
Connecting the pin 4 to ground disables the part.
FFCONTROL
This pin sources a current representative to the line current. Connect a resistor between pin5
and ground to generate a voltage representative of the line current. When this voltage exceeds
the internal 2.5 V reference (VREF ), the circuit operates in critical conduction mode. If the pin
voltage is below 2.5 V, a dead−time is generated that approximately equates [83 ms • (1 −
(Vpin5/VREF))]. By this means, the circuit forces a longer dead−time when the current is small
and a shorter one as the current increases.
The circuit skips cycles whenever Vpin 5 is below 0.65 V to prevent the PFC stage from
operating near the line zero crossing where the power transfer is particularly inefficient. This
does result in a slightly increased distortion of the current. If superior power factor is required,
offset pin 5 by more than 0.75 V offset to inhibit the skip function.
This pin monitors the MOSFET current to limit its maximum current.
This pin is also connected to an internal comparator for Zero Current Detection (ZCD). This
comparator is designed to monitor a signal from an auxiliary winding and to detect the core
reset when this voltage drops to zero. The auxiliary winding voltage is to be applied through a
diode to avoid altering the current sense information for the on−time (see application
schematic).
6
CS / ZCD
7
Ground
8
Drive
The high−current capability of the totem pole gate drive (−0.5/+0.8 A) makes it suitable to
effectively drive high gate charge power MOSFETs.
9
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 10.5 V
(A version, 17.0 V for the B version) and turns off when VCC goes below 9.0 V (typical values).
After start−up, the operating range is 9.5 V up to 35 V.
10
pfcOK
Connect this pin to the PFC stage ground.
This pin is grounded until the PFC output has reached its nominal level. It is also grounded if
the NCP1612 detects a fault. For the rest of the time, i.e., when the PFC stage outputs the
nominal bulk voltage, pin10 is in high−impedance state.
This circuit latches off if pin10 exceeds 7.5 V.
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NCP1612
Figure 2. Block Diagram
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NCP1612
TYPICAL CHARACTERISTICS
17.6
12.0
17.4
11.5
VCC(on) (V)
VCC(on) (V)
17.2
11.0
10.5
10.0
17.0
16.8
16.6
16.4
9.5
16.2
9.0
−50 −30
−10
10
30
50
70
90
110
16.0
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Start−Up Threshold, VCC Increasing
(VCC(on)) vs. Temperature (A Version)
Figure 4. Start−Up Threshold, VCC Increasing
(VCC(on)) vs. Temperature (B Version)
10.00
2.00
9.75
1.75
9.25
VCC(hysr) (V)
VCC(off) (V)
9.50
9.00
8.75
1.50
1.25
1.00
8.50
0.75
8.25
8.00
−50 −30
−10
10
30
50
70
90
110
0.50
−50 −30
130
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. VCC Minimum Operating Voltage, VCC
Falling (VCC(off)) vs. Temperature
Figure 6. Hysteresis (VCC(on) − VCC(off)) vs.
Temperature (A Version)
70
1.50
60
1.25
ICC(0p)1 (mA)
50
ICC(start) (mA)
−10
40
30
20
1.00
0.75
0.50
0.25
10
0
−50 −30
−10
10
30
50
70
90
110
0
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Start−Up Current @ VCC = 9.4 V vs.
Temperature
Figure 8. Operating Current, No Switching
(VSENSE Grounded) vs. Temperature
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NCP1612
TYPICAL CHARACTERISTICS
300
200
275
175
150
225
IDT2 (mA)
IDT1 (mA)
250
200
175
125
100
150
75
125
−10
10
30
50
70
90
110
50
−50 −30
130
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. FFcontrol Pin Current, VSENSE =
1.4 V and VCONTROL Maximum vs. Temperature
Figure 10. FFcontrol Pin Current, VSENSE =
2.8 V and VCONTROL Maximum vs. Temperature
22.5
40
20.5
39
18.5
38
16.5
37
36
14.5
12.5
−50 −30
−10
10
30
50
70
90
110
35
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Dead−Time, VFFcontrol = 1.75 V vs.
Temperature
Figure 12. Dead−Time, VFFcontrol = 1.00 V vs.
Temperature
0.85
0.85
0.75
0.75
VSKIP−L (V)
VSKIP−H (V)
−10
TJ, JUNCTION TEMPERATURE (°C)
TDT3 (ms)
TDT2 (ms)
100
−50 −30
0.65
0.55
0.65
0.55
0.45
−50 −30
−10
10
30
50
70
90
110
0.45
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. FFcontrol Pin Skip Level (VFFcontrol
Rising) vs. Temperature
Figure 14. FFcontrol Pin Skip Level (VFFcontrol
Falling) vs. Temperature
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NCP1612
TYPICAL CHARACTERISTICS
70
25
60
20
15
Trise (ns)
ROH (W)
50
10
40
30
20
5
10
0
−50 −30
−10
10
30
50
70
90
110
0
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. DRV Source Resistance vs.
Temperature
Figure 16. DRV Voltage Rise−Time (CL = 1 nF,
10−90% of Output Signal) vs. Temperature
70
25
60
20
15
Tfall (ns)
ROL (W)
50
10
40
30
20
5
10
0
−50 −30
−10
10
30
50
70
90
110
0
−50 −30
130
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. DRV Sink Resistance vs.
Temperature
Figure 18. DRV Voltage Fall−Time (CL = 1 nF,
10−90% of Output Signal) vs. Temperature
20
2.65
2.60
16
2.55
12
VREF (V)
VDRVhigh (V)
−10
8
2.50
2.45
4
2.40
0
−50 −30
−10
10
30
50
70
90
110
130
2.35
−50 −30
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. DRV Pin Level @ VCC = 35 V (RL =
33 kW, CL = 1 nF) vs. Temperature
Figure 20. Feedback Reference Voltage vs.
Temperature
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NCP1612
TYPICAL CHARACTERISTICS
250
98
97
VOUTL / VREF (%)
GEA (mS)
225
200
175
−10
10
30
50
70
90
110
93
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Error Amplifier Transconductance
Gain vs. Temperature
Figure 22. Ratio (VOUT Low Detect Threshold /
VREF) vs. Temperature
0.5
280
260
0.4
240
IBOOST (mA)
HOUTL / VREF (%)
95
94
150
−50 −30
0.3
0.2
220
200
180
0.1
160
0
−50 −30
−10
10
30
50
70
90
110
140
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. Ratio (VOUT Low Detect Hysteresis /
VREF) vs. Temperature
Figure 24. VCONTROL Source Current when
(VOUT Low Detect) is Activated for Dynamic
Response Enhancer (DRE) vs. Temperature
520
280
515
260
510
240
TLEB−OCP (ns)
VBCS(th) (mV)
96
505
500
495
220
200
180
490
160
485
140
480
−50 −30
−10
10
30
50
70
90
110
130
120
−50 −30
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. Current Sense Voltage Threshold
vs. Temperature
Figure 26. Over−Current Protection Leading
Edge Blanking vs. Temperature
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NCP1612
TYPICAL CHARACTERISTICS
140
100
130
80
110
TOCP (ns)
TLEB−OVS (ns)
120
100
90
80
60
40
20
70
60
−50 −30
−10
10
30
50
70
90
0
−50 −30
110 130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. “Overstress” Protection Leading
Edge Blanking vs. Temperature
Figure 28. Over−Current Protection Delay from
VCS/ZCD > VCS(th) to DRV Low (dVCS/ZCD / dt =
10 V/ms) vs. Temperature
850
270
265
260
VZCD(th)L (mV)
VZCD(th)H (mV)
800
750
255
250
245
240
700
235
−10
10
30
50
70
90
110
230
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 29. Zero Current Detection, VCS/ZCD
Rising vs. Temperature
Figure 30. Zero Current Detection, VCS/ZCD
Falling vs. Temperature
560
1.8
540
1.7
520
RZCD/CS (−)
VZCD(hyst) (mV)
650
−50 −30
500
480
460
1.6
1.5
1.4
1.3
440
420
−50 −30
−10
10
30
50
70
90
1.2
−50 −30
110 130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 31. Hysteresis of the Zero Current
Detection Comparator vs. Temperature
Figure 32. VZCD(th) over VCS(th) Ratio vs.
Temperature
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NCP1612
TYPICAL CHARACTERISTICS
1.5
240
1.4
230
220
1.2
1.1
TWTG (ms)
IZCD/(bias) (mA)
1.3
1.0
0.9
0.8
210
200
190
180
0.7
0.6
0.5
−50 −30
170
−10
10
30
50
70
90
110
160
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 33. CS/ZCD Pin Bias Current @ VCS/ZCD
= 0.75 V vs. Temperature
Figure 34. Watchdog Timer vs. Temperature
960
140
920
130
840
TSYNC (ns)
TWTG(OS) (ms)
880
800
760
120
110
100
720
90
680
640
−50 −30
−10
10
30
50
70
90
110
80
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 35. Watchdog Timer in “Overstress”
Situation vs. Temperature
Figure 36. Minimum ZCD Pulse Width for ZCD
Detection vs. Temperature
32
110
100
31
TTMO (ms)
TZCD (ns)
90
80
70
60
30
29
50
40
−50 −30
−10
10
30
50
70
90
28
−50 −30
110 130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 37. ((VCS/ZCD < VZCD(th)) to DRV High)
Delay vs. Temperature
Figure 38. Timeout Timer vs. Temperature
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NCP1612
27.0
8.8
26.5
8.7
26.0
8.6
TON(HL) (ms)
TON(LL) (ms)
TYPICAL CHARACTERISTICS
25.5
25.0
8.4
8.3
24.5
24.0
−50 −30
−10
10
30
50
70
90
110
8.2
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 39. Maximum On Time @ VSENSE =
1.4 V vs. Temperature
Figure 40. Maximum On Time @ VSENSE =
2.8 V vs. Temperature
100
100
90
90
80
80
TON(HL)(MIN) (ns)
TON(LL)(MIN) (ns)
8.5
70
60
50
70
60
50
40
40
30
30
20
−50 −30
−10
10
30
50
70
90
110
20
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 41. Minimum On Time @ VSENSE = 1.4 V
vs. Temperature
Figure 42. Minimum On Time @ VSENSE = 2.8 V
vs. Temperature
105.4
2.2
105.3
RsoftOVP(HYST) (%)
RsoftOVP (%)
105.2
105.1
105.0
104.9
104.8
2.1
2.0
1.9
104.7
104.6
−50 −30
−10
10
30
50
70
90
110
130
1.8
−50 −30
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 43. Ratio (Soft OVP Threshold, VFB
Rising) over VREF vs. Temperature
Figure 44. Ratio (Soft OVP Hysteresis) over
VREF vs. Temperature
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NCP1612
TYPICAL CHARACTERISTICS
107.4
290
107.3
270
250
107.1
IB(FB) (nA)
RfastOVP2 (%)
107.2
107.0
106.9
210
190
106.8
170
106.7
106.6
−50 −30
−10
10
30
50
70
90
150
−50 −30
110 130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 45. Ratio (fastOVP Threshold,
VFOVP/BUV Rising) over VREF vs. Temperature
Figure 46. Feedback Pin Bias Current @ VFB =
VOVP vs. Temperature
290
15
270
14
250
13
RfUVP (%)
IB(FB)2 (nA)
230
230
210
12
11
190
10
170
150
−50 −30
−10
10
30
50
70
90
110
9
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 47. Feedback Pin Bias Current @ VFB =
VUVP vs. Temperature
Figure 48. Ratio (UVP Threshold, VFB Rising)
over VREF vs. Temperature
0.8
1.10
0.7
VBOH (V)
RfUVP(HYST) (%)
1.05
0.6
0.5
1.00
0.4
0.95
0.3
0.2
−50 −30
−10
10
30
50
70
90
0.90
−50 −30
110 130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 49. Ratio (UVP Hysteresis) over VREF
vs. Temperature
Figure 50. Brown−Out Threshold, VSENSE
Rising vs. Temperature
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NCP1612
1.00
110
0.95
105
VBO(HYST) (mV)
VBOL (V)
TYPICAL CHARACTERISTICS
0.90
0.85
95
−10
10
30
50
70
90
110
90
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 51. Brown−Out Threshold, VSENSE
Falling vs. Temperature
Figure 52. Brown−Out Comparator Hysteresis
vs. Temperature
60
60
55
55
ICONTROL(BO) (mA)
TBO(blank) (ms)
0.80
−50 −30
50
45
40
−50 −30
−10
10
30
50
70
90
110
50
45
40
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 53. Brown−Out Blanking Time vs.
Temperature
Figure 54. VCONTROL Pin Sink Current when a
Brown−Out Situation is Detected vs.
Temperature
2.4
1.9
2.3
1.8
2.2
VLL (V)
VHL (V)
100
2.1
1.7
1.6
2.0
1.9
−50 −30
−10
10
30
50
70
90
1.5
−50 −30
110 130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 55. Comparator Threshold for Line
Range Detection, VSENSE Rising vs.
Temperature
Figure 56. Comparator Threshold for Line
Range Detection, VSENSE Falling vs.
Temperature
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NCP1612
TYPICAL CHARACTERISTICS
30
8
7
6
5
IBO(bias) (nA)
THL(blank) (ms)
28
26
24
4
3
2
1
0
−1
−2
22
20
−50 −30
−10
10
30
50
70
90
110
−3
−4
−50 −30
130
−10
10
30
50
70
90
110 130
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 57. Blanking Time for Line Range
Detection vs. Temperature
Figure 58. Brown−Out Pin Bias Current,
(VSENSE = VBOH) vs. Temperature
DETAILED OPERATING DESCRIPTION
Introduction
The NCP1612 is designed to optimize the efficiency of
your PFC stage throughout the load range. In addition, it
incorporates protection features for rugged operation. More
generally, the NCP1612 is ideal in systems where
cost−effectiveness, reliability, low stand−by power and high
efficiency are the key requirements:
• Current Controlled Frequency Fold−back: the
NCP1612 is designed to drive PFC boost stages in
so−called Current Controlled Frequency Fold−back
(CCFF). In this mode, the circuit classically operates in
Critical conduction Mode (CrM) when the inductor
current exceeds a programmable value. When the
current is below this preset level, the NCP1612 linearly
reduces the frequency down to about 20 kHz when the
current is zero. CCFF maximizes the efficiency at both
nominal and light load. In particular, stand−by losses
are reduced to a minimum. Similarly to FCCrM
controllers, an internal circuitry allows near−unity
power factor even when the switching frequency is
reduced.
• Skip Mode: to further optimize the efficiency, the
circuit skips cycles near the line zero crossing when the
current is very low. This is to avoid circuit operation
when the power transfer is particularly inefficient at the
cost of current distortion. When superior power factor
is required, this function can be inhibited by offsetting
the “FFcontrol” pin by 0.75 V.
• Low Start−up Current and large VCC range (B version):
The consumption of the circuit is minimized to allow
the use of high−impedance start−up resistors to
pre−charge the VCC capacitor. Also, the minimum value
of the UVLO hysteresis is 6 V to avoid the need for
large VCC capacitors and help shorten the start−up time
•
•
•
without the need for too dissipative start−up elements.
The A version is preferred in applications where the
circuit is fed by an external power source (from an
auxiliary power supply or from a downstream
converter). Its maximum start−up level (11.25 V) is set
low enough so that the circuit can be powered from a
12 V rail. After start−up, the high VCC maximum rating
allows a large operating range from 9.5 V up to 35 V.
pfcOK signal: the pfcOK pin is to disable/enable the
downstream converter. Grounded until the PFC output
has reached its nominal level and whenever the
NCP1612 detects a fault, it is in high−impedance when
the PFC stage outputs the nominal bulk voltage. In
addition, the circuit latches off if a voltage exceeding
7.5 V is applied to pin 10.
Fast Line / Load Transient Compensation (Dynamic
Response Enhancer): since PFC stages exhibit low loop
bandwidth, abrupt changes in the load or input voltage
(e.g. at start−up) may cause excessive over or
under−shoot. This circuit limits possible deviations
from the regulation level as follows:
− The soft and fast Over Voltage Protections firmly
contains the output voltage when it tends to become
excessive.
− The NCP1612 dramatically speeds−up the regulation
loop when the output voltage goes below 95.5 % of
its regulation level. This function is enabled only
after the PFC stage has started−up not to eliminate
the soft−start effect.
Safety Protections: the NCP1612 permanently monitors
the input and output voltages, the MOSFET current and
the die temperature to protect the system from possible
over−stress making the PFC stage extremely robust and
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NCP1612
reliable. In addition to the OVP protection, these
methods of protection are provided:
− Maximum Current Limit: the circuit senses the
MOSFET current and turns off the power switch if
the set current limit is exceeded. In addition, the
circuit enters a low duty−cycle operation mode when
the current reaches 150% of the current limit as a
result of the inductor saturation or a short of the
bypass diode.
− Under−Voltage Protection: this circuit turns off when
it detects that the output voltage is below 12% of the
voltage reference (typically). This feature protects
the PFC stage if the ac line is too low or if there is a
failure in the feedback network (e.g., bad
connection).
− Detection of the output voltage improper level: the
“FOVP/BUV” monitors the output voltage.
Typically, the same portion of the output voltage is
applied as to the feedback pin. The circuit disables
the driver if the pin 1 voltage exceeds 102% of the
soft OVP threshold. The circuit also monitors the
output voltage to detect when the PFC stage cannot
maintain the bulk voltage at a high enough level
(BUV situation). When the BUV function trips, the
•
“pfcOK” pin is grounded, to disable the downstream
converter.
− Brown−Out Detection: the circuit detects low ac line
conditions and stops operation thus protecting the
PFC stage from excessive stress.
− Thermal Shutdown: an internal thermal circuitry
disables the gate drive when the junction
temperature exceeds 150°C (typically). The circuit
resumes operation once the temperature drops below
approximately 100°C (50°C hysteresis).
Output Stage Totem Pole: the NCP1612 incorporates a
−0.5 A / +0.8 A gate driver to efficiently drive most
TO220 or TO247 power MOSFETs.
NCP1612 Operation Modes
As mentioned, the NCP1612 PFC controller implements
a Current Controlled Frequency Fold−back (CCFF) where:
− The circuit operates in classical Critical conduction
Mode (CrM) when the inductor current exceeds a
programmable value.
− When the current is below this preset level, the
NCP1612 linearly reduces the operating frequency
down to about 20 kHz when the current is zero.
High Current
No delay è CrM
Low Current
The next cycle is
delayed
Timer delay
Lower Current
Longer dead−time
Timer delay
Figure 59. CCFF Operation
ramp to reach 2.5 V from the current information floor.
Hence, the lower the current information is, the longer the
dead−time. When the current information is 0.75 V, the
dead−time is 50 ms.
To further reduce the losses, the MOSFET turns on is
stretched until its drain−source voltage is at its valley. As
illustrated in Figure 60, the ramp is synchronized to the
drain−source ringing. If the ramp exceeds the 2.5 V
threshold while the drain−source voltage is below Vin , the
ramp is extended until it oscillates above Vin so that the drive
will turn on at the next valley.
As illustrated in Figure 59, under high load conditions, the
boost stage is operating in CrM but as the load is reduced, the
controller enters controlled frequency discontinuous
operation.
Figure 60 details the operation. A voltage representative
of the input current (“current information”) is generated. If
this signal is higher than a 2.5 V internal reference (named
“Dead−Time Ramp Threshold” in Figure 60), there is no
dead−time and the circuit operates in CrM. If the current
information is lower than the 2.5 V threshold, a dead−time
is inserted that lasts for the time necessary for the internal
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NCP1612
Top: CrM operation when the current information exceeds the preset level during the demagnetization phase
Middle: the circuit re−starts at the next valley if the sum (ramp + current information) exceeds the preset level during the dead−time, while
the drain−source voltage is high
Bottom: the sum (ramp + current information) exceeds the preset level while during the dead−time, the drain−source voltage is low. The
circuit skips the current valley and re−starts at the following one.
Figure 60. Dead−Time generation
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NCP1612
Current Information Generation
multiplier gain (Km of Figure 61) is three times less in
high−line conditions (that is when the “”LLine” signal from
the brown−out block is in low state) so that Ipin5 provides a
voltage representative of the input current across resistor
RFF placed between pin 5 and ground. Pin 5 voltage is the
current information.
The “FFcontrol” pin sources a current that is
representative of the input current. In practice, Ipin5 is built
by multiplying the internal control signal (VREGUL , i.e., the
internal signal that controls the on−time) by the sense
voltage (pin 4) that is proportional to the input voltage. The
BO pinpin
VSENSE
IREGUL
IBO
V to I
converter
IBO
Vcontrol pin
VCONTROL
pin
LLine
Multiplier
IREGUL
V to I
converter
Km . IREGUL . IBO
IREGUL= K .VREGUL
+
FFcontrol pin
FFcontrol
pin
SUM
SUM
RAMP
RAMP
RFF
skip2
SKIP
0.75 V / 0.651V
V
pfcOK
pfcOK
Figure 61. Generation of the current information
Skip Mode
by 0.75 V. The skip mode capability is disabled whenever
the PFC stage is not in nominal operation (as dictated by the
“pfcOK” signal − see block diagram and “pfcOK Internal
Signal” Section).
The circuit does not abruptly interrupt the switching when
Vpin5 goes below 0.65 V. Instead, the signal VTON that
controls the on−time is gradually decreased by grounding
the VREGUL signal applied to the VTON processing block (see
Figure 66). Doing so, the on−time smoothly decays to zero
in 3 to 4 switching periods typically. Figure 62 shows the
practical implementation.
As illustrated in Figure 61, the circuit also skips cycles
near the line zero crossing where the current is very low. A
comparator monitors the pin 5 voltage (“FFcontrol”
voltage) and inhibits the switching operation when Vpin5 is
lower than a 0.65 V internal reference. Switching resumes
when Vpin5 exceeds 0.75 V (0.1 V hysteresis). This function
prevents circuit operation when the power transfer is
particularly inefficient at the expense of slightly increased
current distortion. When superior power factor is needed,
this function can be inhibited offsetting the “FFcontrol” pin
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NCP1612
Figure 62. CCFF Practical Implementation
stage transitions from the n valley to (n + 1) valley or vice
versa from the n valley to (n − 1) cleanly as illustrated by
Figure 63.
CCFF maximizes the efficiency at both nominal and light
load. In particular, the stand−by losses are reduced to a
minimum. Also, this method avoids that the system stalls
between valleys. Instead, the circuit acts so that the PFC
Figure 63. Clean Transition Without Hesitation Between Valleys
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NCP1612
NCP1612 On−time Modulation
One can show that the ac line current is given by:
ƪ
Let’s analyze the ac line current absorbed by the PFC
boost stage. The initial inductor current at the beginning of
each switching cycle is always zero. The coil current ramps
up when the MOSFET is on. The slope is (VIN /L) where L
is the coil inductance. At the end of the on−time (t1), the
inductor starts to demagnetize. The inductor current ramps
down until it reaches zero. The duration of this phase is (t2).
In some cases, the system enters then the dead−time (t3) that
lasts until the next clock is generated.
t 1ǒt 1 ) t 2Ǔ
I in + V in
2TL
ƫ
(eq. 1)
Where T = (t1 + t2 + t3) is the switching period and Vin is the
ac line rectified voltage.
In light of this equation, we immediately note that Iin is
proportional to Vin if [t1 (t1 + t2) / T] is a constant.
Figure 64. PFC Boost Converter (left) and Inductor Current in DCM (right)
The NCP1612 operates in voltage mode. As portrayed by
Figure 65, the MOSFET on−time t1 is controlled by the
signal Vton generated by the regulation block and an internal
ramp as follows:
t1 +
C ramp @ V ton
I ch
I in + k @ V in
where : k + constant +
T @ V REGUL
t1 ) t2
I in +
V in @ T ON(LL)
V ton @
T
@
2@L
@ t on,max
REGUL max
ƫ
V REGUL
ǒVREGULǓ max
at low line.
I in +
V in @ T ON(HL)
2@L
@
V REGUL
ǒVREGULǓ max
at high line.
From these equations, we can deduce the expression of the
average input power:
(eq. 3)
or
t1 ) t2
V REGUL
1
@
2L ǒV
Ǔ
Where ton ,max is the maximum on−time obtained when
VREGUL is at its (VREGUL )max maximum level. The
parametric table shows that ton ,max is equal to 25 ms
(TON(LL)) at low line and to 8.5 ms (TON(HL)) at high line
(when pin4 happens to exceeds 1.8 V with a pace higher than
40 Hz − see BO 25 ms blanking time).
Hence, we can re−write the above equation as follows:
(eq. 2)
The charge current is constant at a given input voltage (as
mentioned, it is three times higher at high line compared to
its value at low line). Cramp is an internal capacitor.
The output of the regulation block (VCONTROL) is linearly
transformed into a signal (VREGUL) varying between 0 and
1 V. (VREGUL) is the voltage that is injected into the PWM
section to modulate the MOSFET duty−cycle. The
NCP1612 includes some circuitry that processes (VREGUL )
to form the signal (Vton) that is used in the PWM section (see
Figure 66). (Vton) is modulated in response to the dead−time
sensed during the precedent current cycles, that is, for a
proper shaping of the ac line current. This modulation leads
to:
V ton +
ƪ
P in,avg +
+ V REGUL
Given the low regulation bandwidth of the PFC systems,
(VCONTROL ) and then (VREGUL ) are slow varying signals.
Hence, the (Vton • (t1 + t2)/T) term is substantially constant.
Provided that in addition, (t1) is proportional to (Vton ),
Equation 1 leads to: , where k is a constant. More exactly:
at low line
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ǒV in,rmsǓ
2
@ V REGUL @ T ON(LL)
2 @ L @ ǒV REGULǓ
max
NCP1612
P in,avg +
ǒV in,rmsǓ
2
functioning where (t3 = 0), which leads to (t1 + t2 = T) and
(VTON = VREGUL). That is why the NCP1612 automatically
adapts to the conditions and transitions from DCM and CrM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
@ V REGUL @ T ON(HL)
2 @ L @ ǒV REGULǓ
max
at high line
Where (VREGUL)max is the VREGUL maximum value.
Hence, the maximum power that can be delivered by the
PFC stage is:
ǒPin,avgǓ
max
+
ǒVin,rmsǓ
2
@ T ON(LL)
2@L
at low line
ǒPin,avgǓ
max
+
ǒVin,rmsǓ
2
@ T ON(HL)
2@L
at high line
The input current is then proportional to the input voltage.
Hence, the ac line current is properly shaped.
One can note that this analysis is also valid in the CrM
case. This condition is just a particular case of this
Figure 65. PWM circuit and timing diagram.
Figure 66. VTON Processing Circuit. The integrator OA1 amplifies the error between VREGUL and IN1 so that on
average, (VTON * (t1+t2)/T) equates VREGUL.
Remark:
phase and Vton would inappropriately over−dimension Vton
to compensate it. Instead, as illustrated in Figure 66, the Vton
signal is grounded leading to a short soft−start when the
circuit recovers.
The “Vton processing circuit” is “informed” when a
condition possibly leading to a long interruption of the drive
activity (functions generating the STOP signal that disables
the drive − see block diagram − except OCP, i.e., BUV_fault,
OVP, OverStress, SKIP, staticOVP and OFF). Otherwise,
such situations would be viewed as a normal dead−time
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NCP1612
Regulation Block and Low Output Voltage Detection
The swing of the error amplifier output is limited within
an accurate range:
− It is forced above a voltage drop (VF ) by some
circuitry.
− It is clamped not to exceed 4.0 V + the same VF
voltage drop.
Hence, Vpin3 features a 4 V voltage swing. Vpin3 is then
offset down by (VF ) and scaled down by a resistors divider
before it connects to the “VTON processing block” and the
PWM section. Finally, the output of the regulation block is
a signal (“VREGUL ” of the block diagram) that varies
between 0 and a top value corresponding to the maximum
on−time.
The VF value is 0.5 V typically.
A trans−conductance error amplifier (OTA) with access to
the inverting input and output is provided. It features a
typical trans−conductance gain of 200 mS and a maximum
capability of ±20 mA. The output voltage of the PFC stage
is typically scaled down by a resistors divider and monitored
by the inverting input (pin 2). Bias current is minimized
(less than 500 nA) to allow the use of a high impedance
feed−back network. However, it is high enough so that the
pin remains in low state if the pin is not connected.
The output of the error amplifier is brought to pin 3 for
external loop compensation. Typically a type−2 network is
applied between pin 3 and ground, to set the regulation
bandwidth below about 20 Hz and to provide a decent phase
boost.
VREGUL
(VREGUL)max
VCONTROL
Figure 67. a) Regulation Block Figure (left), b) Correspondence between VCONTROL and VREGUL (right)
Given the low bandwidth of the regulation loop, abrupt
variations of the load, may result in excessive over or
under−shoots. Over−shoot is limited by the soft
Over−Voltage Protection (OVP) connected to the feedback
pin or the fast OVP of pin1.
The NCP1612 embeds a “dynamic response enhancer”
circuitry (DRE) that contains under−shoots. An internal
comparator monitors the feed−back (Vpin1) and when Vpin2
is lower than 95.5% of its nominal value, it connects a
200 mA current source to speed−up the charge of the
compensation network. Effectively this appears as a 10x
increase in the loop gain.
In A version, DRE is disabled during the start−up
sequence until the PFC stage has stabilized (that is when the
“pfcOK” signal of the block diagram, is high). The resulting
slow and gradual charge of the pin 3 voltage (VCONTROL )
softens the soft start−up sequence. In B version, DRE is
enabled during start−up to speed−up this phase and allow for
the use of smaller VCC capacitors.
The circuit also detects overshoot and immediately
reduces the power delivery when the output voltage exceeds
105% of its desired level. The NCP1612 does not abruptly
interrupt the switching. Instead, the signal VTON that
controls the on−time is gradually decreased by grounding
the VREGUL signal applied to the VTON processing block (see
Figure 66). Doing so, the on−time smoothly decays to zero
in 4 to 5 switching periods typically. If the output voltage
still increases, the fast OVP comparator immediately
disables the driver if the output voltage exceeds 108.5% of
its desired level.
The error amplifier OTA and the soft OVP, UVP and DRE
comparators share the same input information. Based on the
typical value of their parameters and if (Vout,nom) is the
output voltage nominal value (e.g., 390 V), we can deduce:
• Output Regulation Level: Vout,nom
• Output soft OVP Level: Vout,sovp = 105% x Vout,nom
• Output UVP Level: Vout,uvp = 12% x Vout,nom
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NCP1612
• Output DRE Level: Vout,dre = 95.5% x Vout,nom
− The BUV comparator trips when Vpin1 drops below
76% of the 2.5 V reference voltage (VBUV = 76% x
VREF). In the case, the circuit grounds the pfcOK
pin (to disable the downstream converter) and
gradually discharges the VCONTROL signal until the
SKIP level is obtained (see block diagram) so that
the next start−up sequence will be performed with a
soft−start. The drive output is disabled for the
VCONTROL discharge time. When the VCONTROL
discharge is complete, the circuit can attempt to
recover operation.
However, the BUV function has no action whenever the
pfcOK pin is in low state, not to inappropriately interrupt
start−up phases.
Fast OVP and Bulk Under−Voltage (BUV)
These functions check that the output voltage is within the
proper window:
− The fast Over−Voltage Protection trips if the bulk
voltage reaches abnormal levels. When the feedback
network is properly designed and correctly
connected, the bulk voltage cannot exceed the level
set by the soft OVP function (Vout,sovp = 105% x
Vout,nom, see precedent section). This second
protection offers some redundancy for a higher
safety level. The FOVP threshold is set 2% higher
than the soft OVP comparator reference so that the
same portion of the output voltage can be applied to
both the FOVP/BUV and feedback input pins (pins 1
and 2).
Figure 68. Bulk Under−Voltage Detection
generate a positive voltage proportional to the MOSFET
current (VCS). The VCS voltage is compared to a 500 mV
internally reference. When VCS exceeds this threshold, the
OCP signal turns high to reset the PWM latch and forces the
driver low. A 200 ns blanking time prevents the OCP
comparator from tripping because of the switching spikes
that occur when the MOSFET turns on.
The CS pin is also designed to receive a signal from an
auxiliary winding for Zero Current Detection. As illustrated
in Figure 69, an internal ZCD comparator monitors the pin6
voltage and if this voltage exceeds 750 mV, a
demagnetization phase is detected (signal ZCD is high). The
auxiliary winding voltage is applied thought a diode to
prevent this signal from distorting the current sense
information during the on−time. Thus, the OCP protection
is not impacted by the ZCD sensing circuitry. This
As a matter of fact, pin1 monitors the output voltage and
checks if it is within the window for proper operation.
Assuming that the same portion of the output voltage is
applied to FOVP/BUV and feedback pins:
− Output fast OVP Level: Vout,fovp = 107% x Vout,nom
− Output BUV Level: Vout,BUV = 76% x Vout,nom
Hence, if the output regulation voltage is 390 V, the FOVP
and BUV output voltage levels are 417 and 296 V
respectively.
A 250 nA sink current is built−in to ground the pin if the
FOVP / BUV pin is accidently open. The circuit disables the
drive as long as the pin voltage is below 300 mV (typically).
Current Sense and Zero Current Detection
The NCP1612 is designed to monitor the current flowing
through the power switch. A current sense resistor (Rsense)
is inserted between the MOSFET source and ground to
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NCP1612
current. If this diode is accidentally shorted, the MOSFET
will also see a high current when it turns on. In both cases,
the current can be large enough to trigger the ZCD
comparator. An AND gate detects that this event occurs
while the drive signal is high. In this case, a latch is set and
the “OverStress” signal goes high and disables the driver for
a 800 ms delay. This long delay leads to a very low
duty−cycle operation in case of “OverStress” fault in order
to limit the risk of overheating.
comparator incorporates a 500 mV hysteresis and is able to
detect ZCD pulses longer than 200 ns. When pin 6 voltage
drops below the lower ZCD threshold, the driver can turn
high within 200 ns.
It may happen that the MOSFET turns on while a huge
current flows through the inductor. As an example such a
situation can occur at start−up when large in−rush currents
charge the bulk capacitor to the line peak voltage.
Traditionally, a bypass diode is generally placed between the
input and output high−voltage rails to divert this inrush
Figure 69. Current Sense and Zero Current Detection Blocks
When no signal is received that triggers the ZCD
comparator during the off−time, an internal 200 ms
watchdog timer initiates the next drive pulse. At the end of
this delay, the circuit senses the CS/ZCD pin impedance to
detect a possible grounding of this pin and prevent
operation. The CS/ZCD external components must be
selected to avoid false fault detection. 3.9 kW is the
recommended minimum impedance to be applied to the
CS/ZCD pin when considering the NCP1612 parameters
tolerance over the −40°C to 125°C temperature range.
Practically, Rcs must be higher than 3.9 kW in the application
of Figure 69.
− Incorrect feeding of the circuit (“UVLO” high when
VCC < VCC(off), VCC(off) equating 9 V typically).
− Excessive die temperature detected by the thermal
shutdown.
− Under−Voltage Protection
− Latched−off of the part
− Regulation loop failure (UVP)
− Brown−out Situation (BO_fault high − see Figure 2)
The pfcOK signal is controlled as illustrated by Figure 70.
The circuit monitors the current sourced by the OTA. If there
is no current, we can deduce that the output voltage has
reached its nominal level. The start−up phase is then
complete and pfcOK remains high−impedance until a fault
is detected. Upon startup, the internal signals and the
internal supply rails need some time to stabilize. The
pfcOK latch cannot be set during this time and until a
sufficient blanking time has elapsed. For the sake of
simplicity, this blanking delay is not represented in
Figure 70.
Another mandatory condition to set pfcOK high is the low
state of the “BUVcomp” signal. This second necessary
condition ensures that the voltage applied to pin 1 is high
enough not to immediately trigger the BUV protection.
The pfcOK pin is to be used to enable the downstream
converter.
pfcOK Signal
The pfcOK pin is in high−impedance state when the PFC
stage operates nominally and is grounded in the following
cases:
• During the PFC stage start−up, that is, until the output
voltage has stabilized at the right level.
• If the output voltage is too low for proper operation of
the downstream converter, more specifically, when the
“BUV_fault” signal (see Figure 2) is in high state.
• In the case of a condition preventing the circuit from
operating properly like in a Brown−out situation or
when one of the following faults turns off the circuit:
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NCP1612
Figure 70. pfcOK Detection
moment, the circuit turns off (see Figure 2). This method
limits any risk of false triggering. The input of the PFC stage
has some impedance that leads to some sag of the input
voltage when the drawn current is large. If the PFC stage
stops while a high current is absorbed from the mains, the
abrupt decay of the current may make the input voltage rise
and the circuit detect a correct line level. Instead, the gradual
decrease of VCONTROL avoids a line current discontinuity
and limits risk of false triggering.
Pin4 is also used to sense the line for feed−forward. A similar
method is used:
− The VSENSE pin voltage is compared to a 2.2 V
reference.
− If Vpin4 exceeds 2.2 V, the circuit detects a high−line
condition and the loop gain is divided by three (the
internal PWM ramp slope is three times steeper)
− Once this occurs, if Vpin4 remains below 1.7 V for
25 ms, the circuit detects a low−line situation
(500 mV hysteresis).
At startup, the circuit is in low−line state (“LLine” high”)
until Vpin4 exceeds 2.2 V.
The line range detection circuit allows more optimal loop
gain control for universal (wide input mains) applications.
As portrayed in Figure 71, the pin 4 voltage is also utilized
to generate the current information required for the
frequency fold−back function.
The circuit also incorporates a comparator to a 7.5 V
threshold so that the part latches off if the pfcOK pin voltage
exceeds 7.5 V. This pin is to protect the part in presence of
a major fault like a die over−heating. To recover operation,
a brown−out condition must be detected (if circuit VCC is
properly fed) or VCC must drop below VCC(reset).
Brown−Out Detection
The VSENSE pin (pin4) receives a portion of the
instantaneous input voltage (Vin ). As Vin is a rectified
sinusoid, the monitored signal varies between zero or a small
voltage and a peak value.
For the brown−out block, we need to ensure that the line
magnitude is high enough for operation. This is done as
follows:
− The VSENSE pin voltage is compared to a 1 V
reference.
− If Vpin4 exceeds 1 V, the input voltage is considered
sufficient
− If Vpin4 remains below 0.9 V for 50 ms, the circuit
detects a brown−out situation (100 mV hysteresis).
By default, when the circuit starts operation, the circuit is
in a fault state (“BO_NOK” high) until Vpin4 exceeds 1 V.
When “BO_NOK” is high, the drive is not disabled.
Instead, a 50 mA current source is applied to pin3 to
gradually reduce VCONTROL . As a result, the circuit only
stops pulsing when the SKIP function is activated
(VCONTROL reaches the skip detection threshold). At that
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NCP1612
Figure 71. Input Line Sense Monitoring
Thermal Shutdown (TSD)
Reference Section
An internal thermal circuitry disables the circuit gate drive
and keeps the power switch off when the junction
temperature exceeds 150°C. The output stage is then
enabled once the temperature drops below about 100°C
(50°C hysteresis).
The temperature shutdown remains active as long as the
circuit is not reset, that is, as long as VCC is higher than
VCC(RESET). The reset action forces the TSD threshold to be
the upper one (150°C), thus ensuring that any cold start−up
will be done with the proper TSD level.
The circuit features an accurate internal 2.5 V reference
voltage (VREF ) optimized to be ±2.4% accurate over the
temperature range.
OFF Mode
As previously mentioned, the circuit turns off when one
of the following faults is detected:
• Incorrect feeding of the circuit (“UVLO” high when
VCC < VCC(off), VCC(off) equating 9 V typically).
• Excessive die temperature detected by the thermal
shutdown.
• Brown−Out Fault and SKIP (see block diagram)
• Output Under−Voltage situation (Vpin1 and/or Vpin2
lower than 12% of VREF )
• Latched off produced by pulling the pfcOK pin above
7.5 V.
Generally speaking, the circuit turns off when the
conditions are not proper for desired operation. In this mode,
the controller stops operating. The major part of the circuit
sleeps and its consumption is minimized.
Output Drive Section
The output stage contains a totem pole optimized to
minimize the cross conduction current during high
frequency operation. The gate drive is kept in a sinking
mode whenever the Under−Voltage Lockout is active or
more generally whenever the circuit is off. Its high current
capability (−500 mA/+800 mA) allows it to effectively
drive high gate charge power MOSFET. As the circuit
exhibits a large VCC range (up to 35 V), the drive pin voltage
is clamped not to provide the MOSFET gate with more than
14 V.
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NCP1612
Failure Detection
When manufacturing a power supply, elements can be
accidentally shorted or improperly soldered. Such failures
can also happen to occur later on because of the components
fatigue or excessive stress, soldering defaults or external
interactions. In particular, adjacent pins of controllers can be
shorted, a pin can be grounded or badly connected. Such
open/short situations are generally required not to cause fire,
smoke nor big noise. The NCP1612 integrates functions that
ease meeting this requirement. Among them, we can list:
• Floating feedback pins
A 250 nA sink current source pulls down the voltage on
the feedback and FOVP/BUV pin so that the UVP
protection trips and prevents the circuit from operating
if one of this pin is floating. This current source is small
(450 nA maximum) so that its impact on the output
regulation and OVP levels remain negligible with the
resistor dividers typically used to sense the bulk
voltage.
• Fault of the GND connection
If the GND pin is properly connected, the supply
current drawn from the positive terminal of the VCC
capacitor, flows out of the GND pin to return to the
negative terminal of the VCC capacitor. If the GND pin
is not connected, the circuit ESD diodes offer another
return path. The accidental non connection of the GND
pin can hence be detected by detecting that one of this
•
•
ESD diode is conducting. Practically, the CS/ZCD ESD
diode is monitored. If such a fault is detected for
200 ms, the circuit stops operating.
Detection the CS/ZCD pin improper connection
The CS/ZCD pin sources a 1 mA current to pull up the
pin voltage and hence disable the part if the pin is
floating. If the CS/ZCD pin is grounded, the circuit
cannot monitor the ZCD signal and the 200 ms
watchdog timer is activated. When the watchdog time
has elapsed, the circuit sources a 250 mA current source
to pull−up the CS/ZCD pin voltage. No drive pulse is
initiated until the CS/ZCD pin voltage exceeds the ZCD
0.75 V threshold. Hence, if the pin is grounded, the
circuit stops operating. Circuit operation requires the
pin impedance to be 3.9 kW or more, the tolerance of
the NCP1612 impedance testing function being
considered over the −40°C to 125°C temperature range.
Boost or bypass diode short
The NCP1612 addresses the short situations of the
boost and bypass diodes (a bypass diode is generally
placed between the input and output high−voltage rails
to divert this inrush current). Practically, the overstress
protection is implemented to detect such conditions and
forces a low duty−cycle operation until the fault is
gone.
Refer to application note AND9079/D for more details.
ORDERING INFORMATION
Circuit Version
Marking
Package
Shipping†
NCP1612ADR2G
NCP1612A
1612A
NCP1612BDR2G
NCP1612B
1612B
SOIC−10
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCP1612
PACKAGE DIMENSIONS
SOIC−10 NB
CASE 751BQ
ISSUE A
2X
0.10 C A-B
D
D
A
2X
F
0.10 C A-B
10
6
H
E
1
5
0.20 C
10X
B
2X 5 TIPS
L2
b
0.25
A3
L
C
DETAIL A
M
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
C A-B D
TOP VIEW
10X
h
X 45 _
0.10 C
0.10 C
M
A
A1
e
C
SIDE VIEW
DETAIL A
SEATING
PLANE
END VIEW
DIM
A
A1
A3
b
D
E
e
H
h
L
L2
M
MILLIMETERS
MIN
MAX
1.25
1.75
0.10
0.25
0.17
0.25
0.31
0.51
4.80
5.00
3.80
4.00
1.00 BSC
5.80
6.20
0.37 REF
0.40
1.27
0.25 BSC
0_
8_
RECOMMENDED
SOLDERING FOOTPRINT*
1.00
PITCH
10X 0.58
6.50
10X 1.18
1
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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NCP1612/D