For NT68667FG/ NT68667HFG/
NT68667UFG Scaler
Flat Panel Monitor Controller
V 1.5
NT68667H/ NT68667 Scaler
TABLE OF CONTENTS
1.
REVISION HISTORY ............................................................................................................... 4
2.
FEATURES.............................................................................................................................. 5
3.
GENERAL DESCRIPTION ...................................................................................................... 7
4.
BLOCK DIAGRAM .................................................................................................................. 8
5.
PINOUT INFORMATION .......................................................................................................... 9
5.1.
5.2.
5.3.
6.
PIN DIAGRAM ..................................................................................................................... 9
PIN ASSIGNMENT .............................................................................................................. 10
PIN DESCRIPTION ............................................................................................................. 15
FUNCTIONAL DESCRIPTION............................................................................................... 17
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
6.11.
6.11.1.
6.11.2.
6.12.
6.12.1.
6.13.
6.13.1.
6.14.
7.
POWER CONTROL ............................................................................................................ 17
ANALOG TO DIGITAL CONVERTER (ADC) ............................................................................ 17
DVI RECEIVER ................................................................................................................. 18
GRAPHIC PORT CAPTURE INTERFACE ................................................................................ 18
VIDEO PORT CAPTURE INTERFACE .................................................................................... 19
AUTO TUNE ...................................................................................................................... 19
VIDEO PROCESSOR .......................................................................................................... 19
SYNC PROCESSOR ........................................................................................................... 21
OSD FUNCTION ............................................................................................................... 24
DPLL CLOCK CONTROL .................................................................................................... 32
DISPLAY INTERFACE .................................................................................................... 33
Scaler Display Data .................................................................................................... 33
Single/Dual pixel LVDS Transmitter............................................................................. 34
MISCELLANEOUS .............................................................................................................. 36
PWM Output ............................................................................................................... 36
MCU INTERFACE .............................................................................................................. 37
IRQn Interrupt Sources ............................................................................................... 37
8031 ON-CHIP MICROCONTROLLER................................................................................... 38
ELECTRICAL SPECIFICATIONS .......................................................................................... 39
7.1.
7.2.
8.
DC ELECTRICAL CHARACTERISTICS ................................................................................... 39
AC ELECTRICAL CHARACTERISTICS ................................................................................... 44
REGISTERS MAPPING ......................................................................................................... 47
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
8.11.
8.12.
8.13.
8.14.
ADC INTERFACE............................................................................................................... 48
DVI INPUT CONTROL 1...................................................................................................... 51
PRE-PATTERN CONTROL ................................................................................................... 53
GRAPHIC PORT CONTROL ................................................................................................. 53
VIDEO PORT CONTROL ..................................................................................................... 61
COLOR SPACE CONVERSION CONTROL .............................................................................. 63
VIDEO PORT CAPTURE CONTROL ...................................................................................... 64
BACK END IMAGE PROCESSING ......................................................................................... 65
NOISE REDUCTION FILTER CONTROL ................................................................................. 67
GENERAL PURPOSE INPUT OUTPUT (GPIO) ....................................................................... 68
PWM OUTPUT ................................................................................................................. 69
ON SCREEN DISPLAY REGISTERS ...................................................................................... 71
SOURCE HSYNC DIGITAL PLL CONTROL............................................................................. 87
INDEX PORT ACCESS CONTROL ......................................................................................... 90
2008-05-05
2
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.
8.31.
8.32.
8.33.
8.34.
9.
AUTO GAIN/GAUGE ACCESS W INDOW CONTROL ................................................................ 91
DISPLAY DIGITAL PLL CONTROL ........................................................................................ 93
GRAPHIC INPUT GAUGE .................................................................................................... 95
PRODUCT ID .................................................................................................................... 95
POWER CONTROL ............................................................................................................ 96
AUTO TUNE ...................................................................................................................... 96
BRIGHT FRAME DISPLAY REGISTERS ............................................................................... 102
DVI INPUT CONTROL 2.................................................................................................... 104
DISPLAY PORT CONTROL ................................................................................................ 105
SYNC PROCESSOR ..........................................................................................................115
LVDS OUTPUT CONTROL ................................................................................................ 123
SRGB CONTROL ............................................................................................................ 126
HIGH-BANDWIDTH DIGITAL CONTENT PROTECTION SYSTEM .............................................. 131
DITHERING FUNCTION 2 .................................................................................................. 137
HORIZONTAL NON-LINEAR SCALING FUNCTION ................................................................. 140
BRIGHT FRAME BORDER FUNCTION ................................................................................. 141
Y/C PEAKING CONTROL .................................................................................................. 144
ACE CONTROL............................................................................................................... 145
COLOR MANAGEMENT .................................................................................................... 147
DBC.............................................................................................................................. 150
ORDERING INFORMATION ................................................................................................ 153
PACKAGE INFORMATION ............................................................................................................. 154
2008-05-05
3
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
1. Revision History
NT68667 Specification Revision History
Version
Content
Data
0.1
First version released
Oct. 2007
0.2
Delete TCON feature
Dec. 2007
1.0
Release
Feb. 2008
1.1
Register , AC/DC spec. update
Mar. 2008
1.2
Add chip surface temperature
Mar. 2008
1.3
1.4
1.5
2008-05-05
0x150~0x153 reg. update
0x13A, 0x13B remove
Block diagram update
Non-linear ACE reg. update
NR Reg. 0x068 , 0x06A update
0x338 update
Add U type spec.
4
Mar. 2008
Apr. 2008
May. 2008
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
2. Features
Analog Graphic Input
Support RGB inputs 1440x900@75hz for NT68667FG , 1680x1050@75hz for NT68667HFG ,
1920x1080@75hz for NT68667UFG or YPbPr (1080p) inputs
Triple 8bit ADCs (0.55~0.9V) with 500MHz bandwidth
166Mhz(NT68667FG)/188MHz(NT68667HFG)/190MHz(NT68667UFG) HPLL with 64 steps phase
adjust for each RGB channel
Auto offset for component video
Supports both non-interlaced and interlaced input signals
ADC bandwidth adjust : 500M,450M,400M,350M,300M,250M,150M,75M
Digital Graphic and Video Inputs
DVI receiver up to 165MHz with HDCP with HDCP 280 bytes sram
Supports ITU-R BT.656 8-bit Input format
Video Processing
Zoom and shrink engineer with non-linear scaling in horizontal direction for wide screen panels
The 3rd generation Bright Frame with adaptive contrast control, 24 color tones adjustment , sRGB
real color engine and edge enhancement functions
Adjustable sharpness setting
Support DBC to save system operation power
Fixed 10 bit dither LSB & 10-8 dither enable
Text Enahncement
Enhance ghost cancellation
Sync Processor
Support TTL Sync-On-Green (SOG) (including Sync Slicer)
Polarity detection
Frequency measurement
Fast mode change detection
Interlace or non-interlace input detection
Separate or composite sync auto switching (including Sync Separator)
Internal OSD
Programmable multi-color RAM font as well as a bitmapped graphical OSD are supported
Provide 1,2,3/4 bits/pixel RAM Fonts
Optional 10x18, 12x18, 10x16, 12x16 dot matrix
Internal SRAM allows up to 2048 characters, with programmable OSD frame size. Width is 64
column, and Height is 32 row
Programmable shadow or border control for each character by each row
Programmable blinking effects for each character
Spacing control to avoid expansion distortion
Supports simultaneous display of up to 4 OSD windows
Maximum 4 times of global zoom for horizontal and vertical axis
Separate row zoom control
Support flexible FG or BG optional transparent, translucent, and opaque effects
256 palette with 64K color selectable
Top-bottom flip, left-right mirror and 90 degree / 270 degree rotated
Flexible Fade-in, Fade-out effect
2008-05-05
5
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Splitting OSD frame supported
Gradient fade-in/fade –out
Insert variable space by row
Total provide 15K byte RAM size
Display Output
Support 8/6bit single/dual port LVDS panel up to 1440x900@75 for NT68667FG , 1680x1050@75
for NT68667HFG and 1920x1080@75 for NT68667UFG
LVDS support up to 190MHz
All of output keep “low” after power up
Built-in Dual Pixel LVDS Transmitter
Integrate the Dual Port, 4 Data Channel and Clock-Out Low-Voltage differential LVDS transmitter
to supports single or dual pixel 6/8-bit display data transmission
Suited for VGA, SVGA, XGA and dual pixel SXGA, WSXGA display transmission from controller to
display with very low EMI
Embedded Microcontroller
External SPI program memory supported
1 UART, 2 timers, 2 external Interrupts
2 x I2C master/slavers for DDC2Bi/2B+/Ci and EDID functions
I/Os: 4 x 7bits ADC, 10 x PWM, totally 35 adjustable I/Os
Support DDC 5V/3.3V compatible
Power
3.3V/1.8V power supply
Normal operate less than 1W
Embedded 3.3 to 1.8 LDO
Package
QFP 128 pin
2008-05-05
6
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
3. General Description
The NT68667 is a highly integrated flat panel display controller that interfaces analog, digital, and video
inputs. It combines a triple ADC, a DVI compliant TMDS receiver, a digital YUV receiver, a high quality
zoom and shrink engine , a multi-color on screen display (OSD) controller , an advanced color engine ,
and many other functions in a single chip. It provides the user with a simple, flexible and cost-effective
solution for various flat panel display products.
The NT68667 operates at frequencies up to 166Mhz/188MHz/190Mhz suitable for LCD monitor up to
1440x900/1680x1050/1920x1080 resolution. The NT68667 also has a built-in noise reduction function
to provide more stable video quality, spread spectrum to provide low EMI solution, sRGB for video color
space convert and post pattern for manufacture test.
The display provided single/double pixel clock LVDS interface.
In addition, NT68667 includes an integrated 8-Bit Microcontroller (MCU). It contains an 8-bit 8031
micro-controller, 3,840 –bytes internal data memory, four 7-bit resolution A/D Converter, 10-channel
8-bit resolution PWM DAC, two16-bit timer/counters, and a UART. Except those, it has two-channel
hardware DDC solution, and VESA 2Bi/2B+ master/slave I2C bus interface.
NT68667
VGA In
YUV (ITU656)
LVDS
SCALER
DVI In
S-Video In
TV
Decoder
Serial Flash Memory
CVBS In
Figure 1 NT68667 System Design Example
2008-05-05
7
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
4. Block Diagram
Post Pattern
Generator
Pre - Pattern
Generator
Digital
TMDS
Analog RGB
Graphic Capture /
Measurement
TMDS
RX
Data over
sampling
YUV
to
RGB
Scaling
BF
Gamma/
10 - 8
Dithering
sRGB
8 -6
Dithering
Display Control
Triple
ADC
OSD
Controller
Over sampling
clock
HPLL
LVDS
Transmitter
OSD
RAMs
ADC_HS
HS / VS
SOGI
SOG
Slicer
Sync
Processor
MCU
IN_ YUV_HS/
IN_ YUV_VS/
IN_ FIELD
Digital
Video
YUV
SSC Clock
Generation
DDC2Bi
*2
Reference
Crystal
Video Capture
Measurement
External Flash Memory
Figure 4-1 Functional Block Diagram
2008-05-05
8
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
5. Pinout Information
5.1. Pin Diagram
RSTB
DVDD
DGND
RX2+
RX2AVCC
RX1+
RX1AGND
RX0+
RX0AGND
RXC+
RXCAVCC
REXT
PVCC
PGND
BIN1+
BIN1SOG1I
GIN1+
GIN1RIN1+
RIN1ADC_VAA
ADC_GNDA
PC2
PD6
PB3/ADC3/INTE1
P31/TXD
P30/RXD
PB2/ADC2/INTE0
PB7*/ADDC_SDA*
PB6*/ADDC _SCL*
PA3/PWM5
PA4*/PWM6*
PA5*/PWM7*
1
2
102 PC6
101 DGND/CGND
3
100 DGND/CGND
4
99
5
98
6
97
7
96
8
95
9
94
10
11
93
92
12
91
13
90
14
89
15
88
16
87
17
86
18
85
84
19
20
21
22
83
NT68667FG
82
81
23
80
24
79
25
78
26
77
27
76
28
75
29
74
30
73
31
72
32
71
33
70
34
69
35
68
36
37
67
66
38
65
DGND/CGND
DGND/CGND
DGND/CGND
DGND/CGND
DGND/CGND
DGND/CGND
DGND/CGND
DGND/CGND
DGND/CGND
DVDD
NC
T0M
T0P
T1M
T1P
T2M
T2P
TCLK1M
TCLK1P
T3M
T3P
DGND/CGND
T4M
T4P
T5M
T5P
T6M
T6P
TCLK2M
TCLK2P
T7M
T7P
PA1/PWM3
PA2/PWM4
PA0/PWM2
Figure 5.1-1 NT68667 Pin Diagram
2008-05-05
9
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
5.2. Pin Assignment
No. Pin
1 RSTB
2
Type
I
DVDD
Power
3 DGND
4 RX2+
5 RX26 AVCC
Power
I
I
Power
7
8
9
10
11
12
13
14
15
I
I
Power
I
I
Power
I
I
Power
RX1+
RX1AGND
RX0+
RX0AGND
RXC+
RXCAVCC
16 REXT
I
17 PVCC
Power
18
19
20
21
22
23
24
25
26
PGND
BIN1+
BIN1SOGI1
GIN1+
GIN1RIN1+
RIN1ADC_VAA
Power
I
I
I
I
I
I
I
Power
27
28
29
30
ADC_GNDA
Power
PC2
PD6
PB3
ADC3
INTE1
31 P31
2008-05-05
I/O
I/O
I/O
I
I
I/O
Operate
Definition
Voltage
0 ~ 3.47V Active-Low Reset Input; with Schmitt Trigger Input
3.15V ~
Micro-controller +3.3V Power Supply Input
3.47V
0V
Micro-controller Power Ground
0.15 ~ 1.2V TMDS input channel 2+
0.15 ~ 1.2V TMDS input channel 23.15V ~
TMDS Analog VCC must be set to 3.3V.
3.47V
0.15 ~ 1.2V TMDS input channel 1+
0.15 ~ 1.2V TMDS input channel 10V
TMDS Analog GND.
0.15 ~ 1.2V TMDS input channel 0+
0.15 ~ 1.2V TMDS input channel 00V
TMDS Analog GND.
0.15 ~ 1.2V TMDS input clock pair
0.15 ~ 1.2V TMDS input clock pair
3.15V ~
TMDS Analog VCC must be set to 3.3V.
3.47V
External termination resistor. A 1% 470 Ω resistor must
be connected from this pin to AVCC.
Notes: if this resistor not 1% , the compatibility is worse
than 1% resistor .
3.15V ~
TMDS PLL Analog VCC must be set to 3.3V.
3.47V
0V
TMDS PLL Analog GND.
B channel positive analog video input
B channel negative analog video input
VGA Port Sync On Green Input with Schmitt trigger
G channel positive analog video input
G channel negative analog video input
R channel positive analog video input
R channel negative analog video input
3.15V ~
ADC Analog power supply
3.47V
0V
ADC Analog ground
0 ~ 3.47V I/O Pin; Push-Pull Structure with Schmitt Trigger Input
0 ~ 3.47V I/O Pin; Push-Pull Structure with Schmitt Trigger Input
0 ~ 3.47V I/O Pin; Push-Pull Structure with Schmitt Trigger Input
0 ~ 3.47V A/D Converter Input-3; Hi-Z input
0 ~ 3.47V External Interrupt input 1; Schmitt Trigger Input
0 ~ 3.47V GPIO Port-31 of Micro-Processor F8031
10
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
TXD
32 P30
RXD
33 PB2
ADC2
INTE0
34 PB7*
ADDC_SDA*
35 PB6*
ADDC_SCL*
36 PA3
PWM5
37 PA4*
PWM6*
38 PA5*
PWM7*
39 PA6*
PWM8*
40 PA7*
PWM9*
41 HSYNCI
42 VSYNCI
43 PLL_ GND
O
I/O
I
I/O
I
I
I/O
I/O
I/O
I/O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I
44 DGND/CGND
45 PLL_ VDD
O
Power
Power
Power
46 PB5*
I/O
DDDC_SDA*/
47 PB4*
DDDC_SCL*/
I/O
I/O
I/O
48 PD5
49 P35
I/O
I/O
T1
50 P34
T0
51 DVDD
I
I/O
I
Power
52 CVDD
Power
53 DVDD
Power
2008-05-05
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
0 ~ 5.25V
0 ~ 5.25V
UART TX Data Output of Micro-Processor F8031
GPIO Port-30 of Micro-Processor F8031
UART RX Data Input of Micro-Processor F8031
I/O Pin; Push-Pull Structure with Schmitt Trigger Input
A/D Converter Input-2; Hi-Z input
External Interrupt input 0, Schmitt Trigger Input
I/O Pin; Open-Drain with Schmitt Trigger Input
5V Open-Drain Serial Data I/O Pin for the VGA DDC Port
and the slave/master I2C-Bus Port
0 ~ 5.25V 5V I/O Pin; Open-Drain with Schmitt Trigger Input
0 ~ 5.25V 5V Open-Drain Serial Clock I/O Pin for the VGA DDC Port
and the slave/master I2C-Bus Port
0 ~ 3.47V I/O Pin; Schmitt Trigger Input
0 ~ 3.47V PWM-Type D/A Converter; 3.3V Push-Pull Structure
0 ~ 5.25V I/O Pin; Open-Drain Structure with Schmitt Trigger Input
0 ~ 5.25V PWM-Type D/A Converter; 5V Open-Drain Structure
0 ~ 5.25V I/O Pin; Open-Drain Structure with Schmitt Trigger Input
0 ~ 5.25V PWM-Type D/A Converter; 5V Open-Drain Structure
0 ~ 5.25V I/O Pin; Open-Drain Structure with Schmitt Trigger Input
0 ~ 5.25V PWM-Type D/A Converter; 5V Open-Drain Structure
0 ~ 5.25V I/O Pin; Open-Drain Structure with Schmitt Trigger Input
0 ~ 5.25V PWM-Type D/A Converter; 5V Open-Drain Structure
0 ~ 5.25V VGA Port Channel Horizontal Sync Input with Schmitt
trigger
0 ~ 5.25V VGA Port Channel Vertical Sync Input with Schmitt trigger
0V
Core Logic Ground pin for PLL.
0V
Digital Ground/ Core Logic Ground
1.6V ~ 2.0V Internal HPLL power supply (1.8V) output . External
capacitor (0.1uF and 100uF) connected is recommended.
0 ~ 5.25V 5V I/O Pin; Open-Drain with Schmitt Trigger Input
0 ~ 5.25V 5V Open-Drain Serial Data I/O Pin for the DVI DDC Port
and the slave/master I2C-Bus Port
0 ~ 5.25V 5V I/O Pin; Open-Drain with Schmitt Trigger Input
0 ~ 5.25V 5V Open-Drain Serial Clock I/O Pin for the DVI DDC Port
and the slave/master I2C-Bus Port
0 ~ 3.47V I/O Pin; Push-Pull Structure with Schmitt Trigger Input
0 ~ 3.47V GPIO Port-35 of Micro-Processor F8031
0 ~ 3.47V Counter/Timer T1 Input of Micro-Processor F8031
0 ~ 3.47V GPIO Port-34 of Micro-Processor F8031
0 ~ 3.47V Counter/Timer T0 Input of Micro-Processor F8031
3.15V ~
Display Digital Power Supply
3.47V
1.6V ~ 2.0V Core logic power supply (1.8V) pin. External capacitor
(0.1uF) connected is recommended.
3.15V ~
Display Digital Power Supply
3.47V
11
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
54
55
56
57
58
59
60
61
62
Video data input
Video data input
Video data input
Video data input
Video data input
Video data input
Video data input
/Video data input
Video Port Clock
V0
V1
V2
V3
V4
V5
V6
V7
YUV_CLK
63 NC
64 DGND/CGND
I
I
I
I
I
I
I
I
I
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
0 ~ 3.47V
Power
65 PA0
PWM4
67 PA1
PWM3
68 T7P
I/O
O
I/O
O
I/O
O
LVDSO
69 T7M
LVDSO
70 TCLK2P
LVDSO
71 TCLK2M
LVDSO
72 T6P
LVDSO
73 T6M
LVDSO
74 T5P
LVDSO
75 T5M
LVDSO
76 T4P
LVDSO
77 T4M
LVDSO
78 DGND/CGND
Power
0V
Digital Ground/ Core Logic Ground
0 ~ 3.47V I/O Pin; Schmitt Trigger Input
0 ~ 3.47V PWM-Type D/A Converter; 3.3V Push-Pull Structure
0 ~ 3.47V I/O Pin; Schmitt Trigger Input
0 ~ 3.47V PWM-Type D/A Converter; 3.3V Push-Pull Structure
0 ~ 3.47V I/O Pin; Schmitt Trigger Input
0 ~ 3.47V PWM-Type D/A Converter; 3.3V Push-Pull Structure
1.2 ± 0.10V Positive LVDS differential data output of channel 7
~
1.2 ± 0.22V
1.2 ± 0.10V Negative LVDS differential data output of channel 7
~
1.2 ± 0.22V
1.2 ± 0.10V Positive LVDS differential clock 2 output
~
1.2 ± 0.22V
1.2 ± 0.10V Negative LVDS differential clock 2 output
~
1.2 ± 0.22V
1.2 ± 0.10V Positive LVDS differential data output of channel 6
~
1.2 ± 0.22V
1.2 ± 0.10V Negative LVDS differential data output of channel 6
~
1.2 ± 0.22V
1.2 ± 0.10V Positive LVDS differential data output of channel 5
~
1.2 ± 0.22V
1.2 ± 0.10V Negative LVDS differential data output of channel 5
~
1.2 ± 0.22V
1.2 ± 0.10V Positive LVDS differential data output of channel 4
~
1.2 ± 0.22V
1.2 ± 0.10V Negative LVDS differential data output of channel 4
~
1.2 ± 0.22V
0V
Digital Ground/ Core Logic Ground
PWM2
66 PA2
2008-05-05
12
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
79 T3P
80 T3M
81 TCLK1P
82 CLK1M
83 T2P
84 T2M
85 T1P
86 T1M
87 T0P
88 T0M
89 NC
90 DVDD
91 DGND/CGND
92 DGND/CGND
93 DGND/CGND
94 DGND/CGND
95 DGND/CGND
96 DGND/CGND
97 DGND/CGND
98 DGND/CGND
99 DGND/CGND
100 DGND/CGND
101 DGND/CGND
102 PC6
103 PC7
104 SPI_CE
105 SPI_SO
106 SPI_SI
2008-05-05
LVDSO 1.2
~
1.2
LVDSO 1.2
~
1.2
LVDSO 1.2
~
1.2
LVDSO 1.2
~
1.2
LVDSO 1.2
~
1.2
LVDSO 1.2
~
1.2
LVDSO 1.2
~
1.2
LVDSO 1.2
~
1.2
LVDSO 1.2
~
1.2
LVDSO 1.2
~
1.2
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
I/O
I/O
O
I
O
± 0.10V Positive LVDS differential data output of channel 3
± 0.22V
± 0.10V Negative LVDS differential data output of channel 3
± 0.22V
± 0.10V Positive LVDS differential clock 1 output
± 0.22V
± 0.10V Negative LVDS differential clock 1 output
± 0.22V
± 0.10V Positive LVDS differential data output of channel 2
± 0.22V
± 0.10V Negative LVDS differential data output of channel 2
± 0.22V
± 0.10V Positive LVDS differential data output of channel 1
± 0.22V
± 0.10V Negative LVDS differential data output of channel 1
± 0.22V
± 0.10V Positive LVDS differential data output of channel 0
± 0.22V
± 0.10V Negative LVDS differential data output of channel 0
± 0.22V
3.15V ~
3.47V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0~ 3.47V
0~ 3.47V
0~ 3.47V
0~ 3.47V
0~ 3.47V
Display Digital Power Supply
Digital Ground/ Core Logic Ground
Digital Ground/ Core Logic Ground
Digital Ground/ Core Logic Ground
Digital Ground/ Core Logic Ground
Digital Ground/ Core Logic Ground
Digital Ground/ Core Logic Ground
Digital Ground/ Core Logic Ground
Digital Ground/ Core Logic Ground
Digital Ground/ Core Logic Ground
Digital Ground/ Core Logic Ground
Digital Ground/ Core Logic Ground
I/O Pin; Push-Pull Structure with Schmitt Trigger Input
I/O Pin; Push-Pull Structure with Schmitt Trigger Input
External flash SPI chip enable
External flash SPI chip serial data output
External flash SPI data serial data input
13
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
107 SPI_CLK
108 PD4
109 DGND
110 NC
111 AD0
112 AD1
113 INT_VSO
O
I/O
Power
0~ 3.47V
0~ 3.47V
0V
I/O
I/O
O
0~ 3.47V
0~ 3.47V
0~ 3.47V
114 INT_HSO
O
115 CVDD
Power
116 NC
117 PWMA*
118 PWMB*
119 CVDD
O
O
Power
120
121
PC0*
I/O
PC1*
I/O
122 PC3
PWM1
124 PC5
125 PB1/ADC1
I/O
O
I/O
O
I/O
I/O
126 PB0/ADC0
I/O
127 OSCI
128 OSCO
I
O
PWM0
123 PC4
External flash SPI clock
I/O Pin; Push-Pull Structure with Schmitt Trigger Input
Digital Ground
Slave address d0
Slave address d1
Internal Vertical Sync output, this signal is by-pass the
Sync-processor
0~ 3.47V Internal Horizontal Sync output, this signal is by-pass the
Sync-processor
1.6V ~ 2.0V Core logic power supply (1.8V) pin. External capacitor
(0.1uF) connected is recommended.
0~ 3.47V PWM type output Open-Drain Structure
0~ 5.25V PWM type output Open-Drain Structure
1.6V ~ 2.0V Core logic power supply (1.8V) pin. External capacitor
(0.1uF) connected is recommended.
0~ 5.25V I/O Pin; 5V Open-Drain Structure with Schmitt Trigger
Input
0~ 5.25V I/O Pin; 5V Open-Drain Structure with Schmitt Trigger
Input
0~ 3.47V I/O Pin; Push-Pull Structure with Schmitt Trigger Input
0~ 3.47V PWM-Type D/A Converter; Push-Pull Structure
0~ 3.47V I/O Pin; Push-Pull Structure with Schmitt Trigger Input
0~ 3.47V PWM-Type D/A Converter; Push-Pull Structure
0~ 3.47V I/O Pin; Push-Pull Structure with Schmitt Trigger Input
0~ 3.47V I/O Pin; Push-Pull Structure with Schmitt Trigger Input
A/D Converter Input-1; Hi-Z input
0~ 3.47V I/O Pin; Push-Pull Structure with Schmitt Trigger Input
A/D Converter Input-0; Hi-Z input
12~15MHz External Crystal OSC Output
12~15MHz External Crystal OSC Input
Table 5.2-1 Pin List
2008-05-05
14
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
5.3. Pin Description
System Interface
Pin
Type
Definition
RSTB
System Reset
I
Graphic Analog Interface
Pin
Type
Definition
ADC_GNDA
ADC_VAA
BIN1+
BIN1SOGI1
GIN1+
GIN1RIN1+
RIN1HSYNCI
VSYNCI
Power
Power
I
I
I
I
I
I
I
I
I
ADC analog ground
ADC analog power supply
B channel positive analog video input
B channel negative analog video input
VGA Port 1 Sync On Green Input with Schmitt trigger
G channel positive analog video input
G channel negative analog video input
R channel positive analog video input
R channel negative analog video input
VGA Port Horizontal Sync Input with Schmitt trigger
VGA Port Vertical Sync Input with Schmitt trigger
Graphic TMDS Interface
Pin
Type
Definition
RX2+
RX2RX1+
RX1RX0+
RX0RXC+
RXCREXT
AVCC
AGND
PVCC
PGND
2008-05-05
I
I
I
I
I
I
I
I
I
Power
Power
Power
Power
TMDS input channel 2+
TMDS input channel 2TMDS input channel 1+
TMDS input channel 1TMDS input channel 0+
TMDS input channel 0TMDS input clock pair
TMDS input clock pair
External termination resistor
TMDS Analog VCC must be set to 3.3V.
TMDS Analog GND.
TMDS PLL Analog VCC must be set to 3.3V.
TMDS PLL Analog GND.
15
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
LVDS Panel Interface
Pin
Type
T0M
T0P
T1M
T1P
T2M
T2P
TCLK1M
TCLK1P
T3M
T3P
T4M
T4P
T5M
T5P
T6M
T6P
TCLK2M
TCLK2P
T7M
T7P
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
LVDSO
Definition
Negative LVDS differential data output of channel 0
Positive LVDS differential data output of channel 0
Negative LVDS differential data output of channel 1
Positive LVDS differential data output of channel 1
Negative LVDS differential data output of channel 2
Positive LVDS differential data output of channel 2
Negative LVDS differential clock 1 output
Positive LVDS differential clock 1 output
Negative LVDS differential data output of channel 3
Positive LVDS differential data output of channel 3
Negative LVDS differential data output of channel 4
Positive LVDS differential data output of channel 4
Negative LVDS differential data output of channel 5
Positive LVDS differential data output of channel 5
Negative LVDS differential data output of channel 6
Positive LVDS differential data output of channel 6
Negative LVDS differential clock 2 output
Positive LVDS differential clock 2 output
Negative LVDS differential data output of channel 7
Positive LVDS differential data output of channel 7
Video ITU-R BT656 Interface
Pin
Type
Definition
V0~V7
VCLK
O
O
Video Port Data[7:0] input
Video Port Clock
Power Pin
Pin
Type
Definition
CVDD
Power
CGND /DVDD
PLL_VDD
Power
Power
PLL_GND
AVCC
AGND
PVCC
PGND
ADC_VAA
ADC_GNDA
Power
Power
Power
Power
Power
Power
Power
Core logic power supply (1.8V) pin. External capacitor
(0.1uF) connected is recommended.
Core Logic Ground /Display Digital Power Supply
Core logic power supply (1.8V) pin for PLL. External
capacitor (0.1uF) connected is recommended.
Core Logic Ground pin for PLL.
TMDS Analog VCC must be set to 3.3V.
TMDS Analog GND.
TMDS PLL Analog VCC must be set to 3.3V.
TMDS PLL Analog GND.
ADC analog power supply
ADC analog ground
2008-05-05
16
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6. Functional Description
6.1. Power Control
NT68667 supports the whole chip power down function except MCU logic and Sync-processor (include
SOG Slicer, and TMDS Sync Detect ) when h/w reset .
Figure 6.1-1 Power Control Block
6.2. Analog to Digital Converter (ADC)
NT68667 provides a clock-recovery circuit and an analog-to-digital converter to effectively save the
cost of needing external expensive ADC and PLL. The gain and offset circuit is used to adjust the gain
(Contrast) of input video amplitude and shift the DC offset voltage (Brightness). The clock-recovery
circuit consisting of a high-speed phase lock loop (PLL) is used to generate the clock to sample analog
RGB data. This circuit is locked to the HSYNC of the incoming video signal. The analog-to-digital
converter (ADC) transfers the input analog RGB video to digital output data with each color 8-bit
resolution.
Gain and Offset Control
RIN/GIN/BIN are high-impedance input pins that accept the RED, GREEN, and BLUE channel
graphics signals. They accommodate input signals ranging from 0.55V to 0.9V full scale. Signals
should be AC-couple to these pins.
Due to AC coupling, clamping pulse is needed to define the time during which the input signal is
clamped to ground, establishing a black reference. Typically the clamping pulse is defined during the
back porch period of the graphics signal. NT68667 generates the clamping pulse internally and the
position and duration are programmable. The simpler clamp-timing generator clamping pulse-starting
position and pulse width is defined in 0x021[7:0] and 0x022[7:0].
2008-05-05
17
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
NT68667 has three independent variable gain amplifiers for each channel with input signal range from
0.55V to 0.9V（p-p）, the full-scale range is set in three 9-bit registers.
NT68667 offset control shifts the entire input range, resulting in a change in image brightness. The
three independent variable 8-bit registers provide independent settings for each channel.
Clamp Pulse generator
This block circuit called Clamp pulse generator generates clamp pulse to ADC. There are two input
trigger sources of the clamp generator, one is signal Hin from separator and another is Row Hs from
the HSYNCI0 / HSYNCI1. The polarity and the trigger edge of the clamp can be selected by using bit
CLMP_POL and bit CLMP_EDG respectively. The trigger delay of the clamp is waiting CLMP_BEG
[5:0] x REFCLK time. The pulse width of the clamp output may be selected by CLMP_WID [5:0].
Clamp Pulse Timing
HSY NCI / H IN
Positive Polarity
HSY NCI / H IN
Negative Polarity
Leading Edge
Trailing Edge
clamp
CLMP_EDG =1
CLMP_PO L=1
clamp
CLMP_EDG =0
CLMP_PO L=1
t PW _CLM P
tD_CLM P
clamp
CLMP_EDG =1
CLMP_PO L=0
clamp
CLMP_EDG =0
CLMP_PO L=0
Clamp Pulse T iming
Figure 6.2-1 Clamp Pulse Timing
COAST
This function is used to cause the pixel clock generator to stop synchronizing with Hsync and continues
producing a clock at its current frequency and phase. This is useful when processing composite sync
that fails to produce horizontal sync pulses when in the vertical interval.
6.3. DVI Receiver
The DVI receiver uses Panel Link Digital technology to support input ranging from VGA to UXGA
(25-165 MHz), which is ideal for desktop and specialty applications.
6.4. Graphic Port Capture Interface
The function of Graphic Port Capture Interface is to provide two interfaces between NT68667 and
external input devices. It can process non-interlaced and interlaced RGB graphic input, and DVI input.
User should select the video input source from Graphic Port (VGA or DVI) and the polarity of external
control signal, and then program the H/V captures size registers to indicate the display area.
2008-05-05
18
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6.5. Video Port Capture Interface
The function of Video Port Capture Interface is to provide Digital YUV interface between NT68667 and
video decoder. It can process non-interlaced and interlaced digital YUV video ITU BT656 input. It
includes color space conversion for YUV to RGB color space conversion.
6.6. Auto Tune
The Auto Tune function consists of Auto Gain, Auto Position, and Auto Phase. With such auto
adjustment support it is possible to measure the correct phase, frequency, gain, and offset of ADC. The
horizontal and vertical back porches of input image and the horizontal and vertical active regions can
also be measured.
6.7. Video Processor
Video processor consists of Interpolation Control, RGB Gain Control, RGB Offset Control, Hue and
Saturation Control, Dithering Control, Gamma Correction Control and sRGB Support.
NT68667 enhanced interpolation method makes the zoomed display image look more smooth and
comfortable.
User can adjust the RGB Gain (Contrast) and RGB Offset (Brightness) by the registers in the ADCPLL
block, or registers in the Video processor block. But for YUV video input, it is suitable to adjust Contrast
and Brightness at here. In addition, it supports all YUV color controls including brightness, contrast, hue
and saturation.
Dithering function can provide 16.7 million colors space for 6-bit/color panel. It is recommended to open
the dithering function while a 6-bit panel is used.
NT68667 provide independently horizontal and vertical zoom scaler with adjustable zoom factor from
1/4x to 4x. Each of the zoom scaler uses variable sharpness filter to provide high quality scaling of
real-time video and still graphic images.
Interpolation
1. Flexible Sharpness Filter
NT68667 include flexible sharpness filter for horizontal and vertical sharpness adjusting. Users can use
them by register programming.
2. Vertical Spatial Interpolation
When interlaced video or images are applied, the NT68667 vertical scaling engines will de-interlace the
input fields spatially and reposition them to align the display’s line map.
3. Advanced Filter
With the aid of two selectable advanced filters when zooming up horizontally, NT68667 provides the
most undistorted image from the original one.
sRGB Support
sRGB is a standard for color exchange proposed by Microsoft and HP. The sRGB controls can be used
to make LCD monitors sRGB compliant.
R'
G'
B'
sRGB
sRGB
sRGB
A0
A1
A2
C 0 R sRGB Offset R
B1 C1 G sRGB Offset G
-----------------------------------[1]
B 2 C 2 B sRGB Offset B
B0
Gamma Correction
Provides 10-bit gamma correction function
F/W needs to define total 256 end-point value in advance
2008-05-05
19
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
1024
768
Gamma = 1.0
Gamma = 2.2
Gamma = 1/2.2
512
256
0
6
25
0
24
4
22
8
20
2
19
6
17
0
16
4
14
8
12
2
11
96
80
64
48
32
0
16
Figure 6.7-1 Gamma Correction Curve
Index Address
0
1
2
….
Gamma Table
LSB0 (2 bits)+MSB0 (8 bits)
LSB1+MSB1
LSB2+MSB2
….
254
255
2008-05-05
Value
LSB254+MSB254
LSB255+MSB255
20
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6.8. Sync Processor
The NT68667 has a Sync Processor block providing the capability of measuring the horizontal and
vertical timing parameters of the input video source. This information may be used to determine the
video format and to detect a change in the input timing. It is also capable of detecting the field type of
interlaced formats.
Hsync /Vsync Frequency and Polarity Detection
GI_HCNT, the 13 bits Hsync period counter counts the time of 32xHSYNC period, then loads the result
into the GI_HCNT latch. The output value will be [((REFCLK / 4 x 32)/Hfreq)], updated once per
VSYNC/CVSYNC period when VSYNC/CVSYNC is present or continuously updated when
VSYNC/CVSYNC is non-present.
GI_VCNT, the 13 bits Vsync period counter counts the time between two VSYNC pulses, then loads
the result into the GI_VCNT latch. The output value will be [(REFCLK/(256 x Vfreq))], updated every
VSYNC/CVSYNC period. An extra overflow bit indicates the condition of H/V counter overflow.
The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse
duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive
polarity is asserted. The INT_HPOL interrupt is set when the GI_HPOL value changes. The INT_VPOL
interrupt is set when the GI_VPOL value changes.
H/V Present Check
The Hsync present function checks the input HSYNCI pulse, GI_HPRE flag is set when HSYNCI is
over HSYNC Present High Counter Threshold (HPRE_THR_HI) or cleared when HSYNC is under
HSYNC Present Low Counter Threshold (HPRE_THR_LO). The Vsync present function checks the
input VSYNCI pulse, the GI_VPRE flag is set when VSYNCI is over VSYNC Present High Counter
Threshold (VPRE_THR_HI) or cleared when VSYNC is under VSYNC Present Low Counter Threshold
(VPRE_THR_LO). The INT_HPRE interrupt is set when the GI_HPRE value changes. The INT_VPRE
interrupt is set when the GI_VPRE /GI_CSPRE value change.
Timing Change Detection
The INT_VFREQ/INT_HFREQ interrupt is set when GI_VCNT / GI_HCNT value changes or overflows.
2008-05-05
21
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Extract Vsync from Composite/SOG Signal
Vsync
Hsync
ORed
XORed
Single
Serrated
Double
Serrated + Equal.
Pre-Equal. Pulses
Serration Pulses
Post-Equal. Pulses
Vertical Blanking Interval
Extracted VSO
textract(VSO) = fixed
Internal Coast
twiden(VSO)
PRE_COAST = 3
POS_COAST = 3
tPW(insert)
Extracted HSO from
SOGI / HSYNCI
Inserted Pulses
Internal Coast
tPW(insert)
Extracted HSO from
SOG / HSYNCI
Inserted Pulses
H/V Sync Timing
Figure 6.8-1 H/V Timing
Internal Odd/Even Field Detection
Included in the sync detector is circuitry to determine which field is currently being input for interlaced
input. To determine the field based on position of VSYNC relative to HSYNC, the GI_FLD_WINBEG
(3:0) and GI_FLD_WINEND (3:0) registers are used for Graphic Port and the VI_FLD_WINBEG (3:0)
and VI_FLD_WINEND (3:0) registers are used for Video Port. The NT68667 divides each horizontal
line into 16 equal intervals. The FLD_WINBEG bits are used to specify at which 1/16th of a line to start
looking for the leading edge of VSYNC. The FLD_WINEND bits are used to specify at which 1/16th of a
line to stop looking. If the leading edge of VSYNC occurs between during or after the 1/16 th line
specified by FLD_WINBEG, but no later than the 1/16th line specified by FLD_WINEND, the current
field is marked as odd. Otherwise, a leading edge transition outside these boundaries will cause the
current field to be marked even.
2008-05-05
22
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
FLD_WINEND
FLD_WINBEG
HSYNC
VSYNC
iFIELD
EVEN
ODD
FLD_WINBEG
FLD_WINEND
HSYNC
VSYNC
iFIELD
ODD
EVEN
Interlaced Field Detection Window
Figure 6.8-2 Interlaced Field Detection Window
Free Run Timing Generator
This Block can generate various free-running outputs to satisfy various application requirements. The
pulse width of the HFREE output is fixed 15 x REFCLK and the VFREE is 3 HFREEs. User can properly set
the content of HSO Free Run divider, HFREE_DIV, to get the need frequency of the HSO, and set the
content VSO Free Run divider, VFREE_DIV, to get the frequency of the VSO. Details refer to the
descriptions of the free-run registers HFREE_DIV and VFREE_DIV. Refer to the descriptions of the
register for details to get user’s need frequencies.
Users can disable H/V free run output by clearing GI_HRUN_EN /GI_VRUN_EN.
Sync On Green Slicer
This function is provided to assist with processing signals with embedded sync, typically on the GIN
channel. The circuit sliced the signals that with embedded sync, and apply to Sync Separator for
extracting Hsync and Vsync.
2008-05-05
23
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6.9. OSD Function
OSD Font’s Attribute and Code Format, Palette Format Definition:
OSD Palette Format
4:0
15:11 10:5
R
G
B
OSD Code Format
7:0
Font Index
OSD Attribute Format
15:8
7:4
3:2
PA_Index [7:0] BG_Index [3:0] CA_Bit
1
Mix
0
Blink
Figure 6.9-1
: 0 – No blinking
1 – Blinking (All color is blinking except background color)
Mix
: 0 – Normal
1 – Translucent ((1- TP_LEVEL_ONE) Display + (TP_LEVEL_ONE) OSD_BG)
CA_Bit [1:0] : Character attribute bits/pixel number
00: one bit/pixel color Font (0-255 font index)
01: one bit/pixel color Font (256-511 font index)
10: two bits/pixel color Font
11: three/four bits/pixel color Font
PA_Index [7:0] / BG_Index [3:0]: Attribute color palette index
Blink
Case A: Pixel is outside an active window
One Bit per pixel.
Foreground ‘1’ Pixel [7:0] <= PA_Index [7:0] + 1
Background ‘0’ Pixel [7:0] <= BG_Index [3:0]
Two Bit per pixel.
Foreground ‘11’ Pixel [7:0] <=
Foreground ‘10’ Pixel [7:0] <=
Foreground ‘01’ Pixel [7:0] <=
Background ‘00’ Pixel [7:0] <=
PA_Index [7:0] + ‘11’
PA_Index [7:0] + ‘10’
PA_Index [7:0] + ‘01’
BG_Index [3:0]
Four Bit per pixel.
Foreground ‘1111’ Pixel [7:0] <=
Foreground ‘1110’ Pixel [7:0] <=
Foreground ‘1101’ Pixel [7:0] <=
Foreground ‘1100’ Pixel [7:0] <=
Foreground ‘1011’ Pixel [7:0] <=
Foreground ‘1010’ Pixel [7:0] <=
Foreground ‘1001’ Pixel [7:0] <=
Foreground ‘1000’ Pixel [7:0] <=
Foreground ‘0111’ Pixel [7:0] <=
2008-05-05
PA_Index [7:0] + ‘1111’
PA_Index [7:0] + ‘1110’
PA_Index [7:0] + ‘1101’
PA_Index [7:0] + ‘1100’
PA_Index [7:0] + ‘1011’
PA_Index [7:0] + ‘1010’
PA_Index [7:0] + ‘1001’
PA_Index [7:0] + ‘1000’
PA_Index [7:0] + ‘0111’
24
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Foreground ‘0110’ Pixel [7:0] <=
Foreground ‘0101’ Pixel [7:0] <=
Foreground ‘0100’ Pixel [7:0] <=
Foreground ‘0011’ Pixel [7:0] <=
Foreground ‘0010’ Pixel [7:0] <=
Foreground ‘0001’ Pixel [7:0] <=
PA_Index [7:0] + ‘0110’
PA_Index [7:0] + ‘0101’
PA_Index [7:0] + ‘0100’
PA_Index [7:0] + ‘0011’
PA_Index [7:0] + ‘0010’
PA_Index [7:0] + ‘0001’
Note: If BG_Index [3:0] = ”0000”, indicates that this background color is transparent
If BG_Index [3:0] = “0001”, Background <= PA_Index [7:0]
Case B: Pixel is inside an active window
One Bit per pixel.
Foreground ‘1’ Pixel [7:0] <= PA_Index [7:0] + ‘1’
Background ‘0’ Pixel [7:0] <= WINx_ATTR [7:0]
Two Bit per pixel.
Foreground ‘11’ Pixel [7:0] <=
Foreground ‘10’ Pixel [7:0] <=
Foreground ‘01’ Pixel [7:0] <=
Background ‘00’ Pixel [7:0] <=
PA_Index [7:0] + ‘11’
PA_Index [7:0] + ‘10’
PA_Index [7:0] + ‘01’
WINx_ATTR [7:0]
Four Bit per pixel.
Foreground ‘1111’ Pixel [7:0] <=
Foreground ‘1110’ Pixel [7:0] <=
Foreground ‘1101’ Pixel [7:0] <=
Foreground ‘1100’ Pixel [7:0] <=
Foreground ‘1011’ Pixel [7:0] <=
Foreground ‘1010’ Pixel [7:0] <=
Foreground ‘1001’ Pixel [7:0] <=
Foreground ‘1000’ Pixel [7:0] <=
Foreground ‘0111’ Pixel [7:0] <=
Foreground ‘0110’ Pixel [7:0] <=
Foreground ‘0101’ Pixel [7:0] <=
Foreground ‘0100’ Pixel [7:0] <=
Foreground ‘0011’ Pixel [7:0] <=
Foreground ‘0010’ Pixel [7:0] <=
Foreground ‘0001’ Pixel [7:0] <=
Background ‘0000’ Pixel [7:0] <=
2008-05-05
PA_Index [7:0] + ‘1111’
PA_Index [7:0] + ‘1110’
PA_Index [7:0] + ‘1101’
PA_Index [7:0] + ‘1100’
PA_Index [7:0] + ‘1011’
PA_Index [7:0] + ‘1010’
PA_Index [7:0] + ‘1001’
PA_Index [7:0] + ‘1000’
PA_Index [7:0] + ‘0111’
PA_Index [7:0] + ‘0110’
PA_Index [7:0] + ‘0101’
PA_Index [7:0] + ‘0100’
PA_Index [7:0] + ‘0011’
PA_Index [7:0] + ‘0010’
PA_Index [7:0] + ‘0001’
WINx_ATTR [7:0]
25
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Palette Address and map
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P253 P254 P255
Figure 6.9-2 Palette
Palette N
Palette
Address
Bits [15:11]
Bits [10:5]
Bits [4:0]
Palette 0
0 (0x00H)
R0 [4:0]
G0 [5:0]
B0 [4:0]
Palette 1
1 (0x01H)
R1 [4:0]
G1 [5:0]
B1 [4:0]
Palette 2
2 (0x02H)
R2 [4:0]
G2 [5:0]
B2 [4:0]
…
…
Palette 15
15 (0x0FH)
R15 [4:0]
G15 [5:0]
B15 [4:0]
Palette 16
16 (0x04H)
R16 [4:0]
G16 [5:0]
B16 [4:0]
Palette 17
17 (0x05H)
R17 [4:0]
G17 [5:0]
B17 [4:0]
…
…
Palette 254
254 (0xFEH)
R254 [4:0]
G254 [5:0]
B254 [4:0]
Palette 255
255 (0xFFH)
R255 [4:0]
G255 [5:0]
B255 [4:0]
Figure 6.9-3 Palette address and map
2008-05-05
26
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
OSD Character Map
Address 1:
Character Attribute for
character upper-left
Address 25:
Character Attribute for
character upper-right
OSD_VH
OSD_HW
Figure 6.9-4 OSD Character Map
OSD Font Definitions
One Bit per pixel
One bit per pixel font definitions are arranged in Color Character Font SRAM Memory on a 12-bit by
18-address grid. The One bit per pixel OSD programmable font start address is specified in Register
0x089 ~ 0x088. Odd font definitions are stored in SRAM bits [11:0], and even font definitions are stored
in SRAM bits [23:12].
FONT_X = 12 pixels
Font BitMask
000000000000
000000000000
000000000000
000011111000
000111111100
001100001100
001100001100
000000011000
000000110000
000001100000
000011000000
000110000000
001100000000
001111111100
001111111100
000000000000
000000000000
000000000000
FONT_Y = 18 lines
1
0
Figure 6.9-5 One Bit Per Pixel Font
2008-05-05
27
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Two Bit per pixel
Two bits per pixel font definitions are arranged in Color Character Font SRAM Memory on a 24-bit by
18 addresses. The two bit per pixel OSD programmable font start address is specified in Register
0x08B ~ 0x08A. Font definitions are stored in SRAM bits [23:0].
FONT_X = 12 pixels
Font Bit Mask
000000000000000000000000
000000000000000000000000
000000000010101010000000
000000000101010101100000
000000010101010101011000
000001010000000001011000
000001010000000001011000
000000000000000101100000
000000000000010110000000
000000000001011000000000
000000000101100000000000
000000010110000000000000
000001011010101010101000
000001010101010101011000
000001010101010101011000
0000000000000000000
111111111111111111111111
000000000000000000000000
FONT_Y = 18 lines
01
00
10
11
Figure 6.9-6 Two Bit Per Pixel Font
Three Bit per pixel
Three bits per pixel font definitions are arranged in Color Character Font SRAM Memory on a 24-bit
by 36 addresses. The four bit per pixel OSD programmable font start address is specified in Register
0x08D ~ 0x08C. Each pixel row of a font contains up 12 pixels, with the font row broken up across two
consecutive Color Character Font SRAM Memory addresses.
FONT_X = 12 pixels
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
FONT_Y = 18 lines
0
1
2
3
4
5
6
7
2008-05-05
28
Font BitMask
1 2 3 4 5 6 7 0 0 0
00000000000
0 0 0 0 1111 0 0
0 0 0 4 4 4 4 4 1 0
0 0 4 4 4 4 4 4 4 1
0 4 4 0 0 0 0 4 4 1
0 4 4 0 0 0 0 4 4 1
0 0 0 0 0 0 4 4 1 0
0 0 0 0 0 4 4 1 0 0
0 0 0 0 4 4 1 0 0 0
0 0 0 4 4 1 0 0 0 0
0 0 4 4 1 0 0 0 0 0
0 4 4 1 1 11 1 1 1
0 4 4 4 4 4 4 4 4 1
04444444441
0 0 0 0 0 0 0 0 0 0
5 5 5 5 5 5 5 5 5 5
0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
FONT_X = 12 pixels
Font Bit Mask
000000000000000000000000
000000000000000000000000
000000000010101010000000
000000000101010101100000
000000010101010101011000
000001010000000001011000
000001010000000001011000
000000000000000101100000
000000000000010110000000
000000000001011000000000
000000000101100000000000
000000010110000000000000
000001011010101010101000
000001010101010101011000
000001010101010101011000
0000000000000000000
111111111111111111111111
000000000000000000000000
FONT_Y = 18 lines
01
00
10
11
Figure 6.9-7 Three Bit Per Pixel Font
Four Bit per pixel
Four bits per pixel font definitions are arranged in Color Character Font SRAM Memory on a 24-bit by
36 addresses. The four bit per pixel OSD programmable font start address is specified in Register
0x08D ~ 0x08C. Each pixel row of a font contains up 12 pixels, with the font row broken up across two
consecutive Color Character Font SRAM Memory addresses.
FONT_X = 12 pixels
0
c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
FONT_Y = 18 lines
0
1
2
3
4
5
6
7
8
9
a
b
c
d
e
f
1
d
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
Font BitMask
2 3 4 5 6 7 8 9 a
e f 9 9 9 9 9 9 9
0 0 0 1111 0 0
0 0 e e e e e 1 0
0 e e e e e e e 1
e e 0 0 0 0 e e 1
e e 0 0 0 0 e e 1
0 0 0 0 0 e e 1 0
0 0 0 0 e e 1 0 0
0 0 0 e e 1 0 0 0
0 0 e e 1 0 0 0 0
0 e e 1 0 0 0 0 0
e e 1 1 1 1 1 1 1
e e e e e e e e 1
eeeeeeeee1
0 0 0 0 0 0 0 0 0
5 5 5 5 5 5 5 5 5
0 0 0 0 0 0 0 0 0
b
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
Figure 6.9-8 Four Bit Per Pixel Font
2008-05-05
29
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
OSD Color Character Font SRAM Memory Arrangement Map:
A single ported SRAM (4096-words × 24-bits) is used for storing character attribute, code index, and
programmable fonts. The following example illustrates the contents of SRAM memory for a sample
OSD. The OSD is three rows by four columns.
Note: That the OSD Frame SRAM and Font SRAM share the same on Color Character Font SRAM
Memory. Thus, the size of the memory map can be traded off against the number of different memory
definitions. In particular, the size of the OSD frame and the number of font data must fit in the Color
Character Font SRAM Memory. That is, the following inequality must be satisfied.
(OSD_HW+1)×(OSD_VH+1) + 18×CELING (Number of 1-bit per pixel fonts / 9) × 9 +
2×18×CELING (Number of 2-bit pixel fonts / 9) × 9 +
3/4×18×CELING (Number of 4-bit pixel fonts / 9) × 9 <= 5120
The programmable font start address setting:
OSD One Bit Font Address (FONT1B_ADDR) = (OSD_HW+1)×(OSD_VH+1)
OSD Two Bits Font Address (FONT2B_ADDR) = OSD One Bit Font Address (FONT1B_ADDR)
+ (Number of 1-bit per pixel fonts) ×(12×18/24)
OSD Three/Four Bits Font Address (FONT3B_ADDR/ FONT4B_ADDR) = OSD Two Bit Font
Address (FONT2B_ADDR) + (Number of 2-bit per pixel fonts) ×(2×12×18/24)
Note: The following inequality must be satisfied
MOD (Number of 1-bit pixel fonts / 9) = 0
MOD (Number of 2-bit pixel fonts / 9) = 0
MOD (Number of 4-bit pixel fonts / 9) = 0
2008-05-05
30
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
OSD Frame Definition:
Frame Origin
Point ( 0, 0 )
OSD_HS
OSD_HW
OSD_VS
ACTIVE DISPLAY
SCREEN
d
OSD_VH
N O VAT E K
OSD
FONT_Y
FONT_X
OSD Window 1-4
( WIN_HS, WIN_VS )
( WIN_HE, WIN_VE )
Figure 6.9-9 OSD Active Frame And Windows
OSD_HS : OSD Frame Horizontal Start (0 – 2047 pixels)
OSD_HW : OSD Frame Horizontal Width (1 – 64 chars)
OSD_VS : OSD Frame Vertical Start (0 – 2047 pixels)
OSD_VH : OSD Frame Vertical Height (1 – 32 chars)
WIN_HS : OSD Window Horizontal Start (1 – 64 chars)
WIN_HE : OSD Window Horizontal End (1 – 64 chars)
WIN_VS : OSD Window Vertical Start (1 – 32 chars)
WIN_VE : OSD Window Vertical End (1 – 32 chars)
FONT_X : Font X size (12/10 pixels)
FONT_Y : Font Y size (16/18 lines)
2008-05-05
31
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6.10. DPLL Clock Control
NT68667 Display PLL (Bandwidth 170MHz) for display timing generator.
Formula:
Fout = (Reference-Freq × DDDS_RATIO [21:0]) / 217
Fref = 12.000 MHz
Note: The value (Reference-Freq × DDDS_RATIO [21:0] / 217) must be large to 100 MHz
2008-05-05
32
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6.11. DISPLAY INTERFACE
NT68667 display interface supports single (24-bit) or dual (48-bit) pixel out format, and supports the
6-bit/color or 8-bit/color LCD panel. Built in internal PLL locking to the reference clock generates all of
the display timing to various LCD panels.
NT68667 also provides the programmable display driving capacity to reduce EMI influence as well as
programmable clock delay to compensate clock skew.
DH_TOTAL
DH_ACT_BEG
DH_HS_WID
DH_ACT_WID
DH_BG_BEG
Active Window
DV_TOTAL
DV_ACT_BEG
Display Background Window
DV_ACT_LEN
DV_BG_BEG
DV_BG_LEN
DV_VS_WID
DH_BG_WID
DE
Display Timing Control
Figure 6.11-1 Display Timing Control
6.11.1. Scaler Display Data
DISP_CLK
DISP_DE
BA, GA, RA[0:7]
Data 0
Data 1
Data 2
Data 3
Data 4
BB, GB, RB[0:7]
Figure 6.11-2 Single Pixel Width Display Data
2008-05-05
33
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
DISP_CLK
DISP_DE
BA, GA, RA[0:7]
Data 0
Data 2
Data 4
Data 6
Data 8
BB, GB, RB[0:7]
Data 1
Data 3
Data 5
Data 7
Data 9
Figure 6.11-3 Double Pixel Width Display Data
6.11.2. Single/Dual pixel LVDS Transmitter
The NT68667 transmitter is de-signed to support single or dual pixel data transmission between Scaler
and Flat Panel Display up to WSXGA resolutions. For single pixel mode, the transmitter converts 24
bits (single Pixel 24-bit color) data into 4 LVDS (Low Voltage Differential Signaling) data streams. For
dual pixel mode, the transmitter converts 48 bits (Dual Pixel 24-bit color) data into 8 LVDS (Low
Voltage Differential Signaling) data streams Control signals (VSYNC, HSYNC, DE and two
user-defined signals) are sent during blanking intervals.
The LVDS transmitter can support the following:
1. Single or double pixel mode
2. 24/48-bit panel mapping to the LVDS channels
3. 18/36-bit panel mapping to the LVDS channels
4. Programmable even/odd LVDS swapping
5. Programmable channel swapping (the clocks are fixed)
6. Support up to WSXGA 75Hz output
Panel Data Mappings
Channel 0 / Channel 4
Channel 1 / Channel 5
Channel 2 / Channel 6
Channel 3 / Channel 7
LVDS channel 0 (T0)
LVDS channel 1 (T1)
LVDS channel 2 (T2)
LVDS channel 3 (T3)
LVDS channel 4 (T4)
LVDS channel 5 (T5)
LVDS channel 6 (T6)
2008-05-05
Dual Pixel mode (When DP_BIT_SHF = 0)
R0, R1, R2, R3, R4, R5, G0
G1, G2, G3, G4, G5, B0, B1
B2, B3, B4, B5, HS, VS, DE
R6, R7, G6, G7, B6, B7, RSVD
LVDS output
D7
D6
D4
D3
Data order
GA0
RA5
RA4
RA3
LVDS output
D18
D15
D14
D13
Data order
BA1
BA0
GA5
GA4
LVDS output
D26
D25
D24
D22
Data order
DE
VS
HS
BA5
LVDS output
D23
D17
D16
D11
Data order
RSVD BA7
BA6
GA7
LVDS output
D7
D6
D4
D3
Data order
GB0
RB5
RB4
RB3
LVDS output
D18
D15
D14
D13
Data order
BB1
BB0
GB5
GB4
LVDS output
D26
D25
D24
D22
34
D2
RA2
D12
GA3
D21
BA4
D10
GA6
D2
RB2
D12
GB3
D21
D1
RA1
D9
GA2
D20
BA3
D5
RA7
D1
RB1
D9
GB2
D20
D0
RA0
D8
GA1
D19
BA2
D27
RA6
D0
RB0
D8
GB1
D19
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
LVDS channel 7 (T7)
Channel 0 / Channel 4
Channel 1 / Channel 5
Channel 2 / Channel 6
Channel 3 / Channel 7
LVDS channel 0 (T0)
LVDS channel 1 (T1)
LVDS channel 2 (T2)
LVDS channel 3 (T3)
LVDS channel 4 (T4)
LVDS channel 5 (T5)
LVDS channel 6 (T6)
LVDS channel 7 (T7)
2008-05-05
Data order
LVDS output
Data order
DE
D23
NA
BB5
D11
GB7
BB4
D10
GB6
BB3
D5
RB7
BB2
D27
RB6
Dual Pixel mode (When DP_BIT_SHF = 1)
R2, R3, R4, R5, R6, R7, G2
G3, G4, G5, G6, G7, B2, B3
B4, B5, B6, B7, HS, VS, DE
R0, R1, G0, G1, B0, B1, RSVD
LVDS output
D7
D6
D4
D3
Data order
GA2
RA7
RA6
RA5
LVDS output
D18
D15
D14
D13
Data order
BA3
BA2
GA7
GA6
LVDS output
D26
D25
D24
D22
Data order
DE
VS
HS
BA7
LVDS output
D23
D17
D16
D11
Data order
RSVD BA1
BA0
GA1
LVDS output
D7
D6
D4
D3
Data order
GB2
RB7
RB6
RB5
LVDS output
D18
D15
D14
D13
Data order
BB3
BB2
GB7
GB6
LVDS output
D26
D25
D24
D22
Data order
DE
NA
NA
BB7
LVDS output
D23
D17
D16
D11
Data order
NA
BB1
BB0
GB1
D2
RA4
D12
GA5
D21
BA6
D10
GA0
D2
RB4
D12
GB5
D21
BB6
D10
GB0
D1
RA3
D9
GA4
D20
BA5
D5
RA1
D1
RB3
D9
GB4
D20
BB5
D5
RB1
D0
RA2
D8
GA3
D19
BA4
D27
RA0
D0
RB2
D8
GB3
D19
BB4
D27
RB0
35
NA
D17
BB7
NA
D16
BB6
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6.12. Miscellaneous
6.12.1. PWM Output
There are two Pulse Width Modulation signal pins available for controlling the LCD back light or audio
volume, PWMA and PWMB. The duty cycle and Frequency of these signals is programmable.
PWM_HCNT
PWM_LCNT
Fref
Figure 6.12-1 Pulse Width Modulation Signal (PWM)
When clock source select from reference clock
F PWM_CLK F REFCLK (PWM_DIV 1 PWM_DIV 2 )
When clock source select from Display Hsync
F PWM_CLK F DISP _ HS (PWM_DIV 1 PWM_DIV 2 )
F PWM_CLK
F PWM
(PWM_HCNT PWM_LCNT)
PWM _ HCNT
Duty
( PWM_HCNT PWM_LCNT )
Duty F PWM_CLK
PWM _ HCNT
F PWM
(1 Duty ) F PWM_CLK
PWM _ LCNT
F PWM
PWM_HCNT
0
1~255
1~255
2008-05-05
PWM_LCNT
0~255
0
1~255
PWM Output
DC ‘0’
DC ‘1’
PWM pulse
36
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6.13. MCU Interface
6.13.1. IRQn Interrupt Sources
NT68667 provides an internal interrupt request output IRQn to internal MCU. The following figure
shows the detail structure of the IRQn sources.
Interrupt Control
Flags
Enables
INT_VFREQ
Detect Rising Edge
Edge Dectect
INT_VFREQ
INT_VFREQ_EN
INT_HFREQ
Edge Dectect
INT_HFREQ
INT_HFREQ_EN
INT_VPOL
Edge Dectect
INT_VPOL
INT_VPOL_EN
INT_HPOL
Edge Dectect
INT_HPOL
INT_HPOL_EN
INT_VEDGE
Edge Dectect
INT_VEDGE
INT_VEDGE_EN
INT_HEDGE
Edge Dectect
INT_HEDGE
INT_HEDGE_EN
INT_ISPRE
Edge Dectect
INT_ISPRE
INT_ISPRE_EN
INT_CSPRE
Edge Dectect
INT_CSPRE
INT_CSPRE_EN
INT_VPRE
Edge Dectect
INT_VPRE
INT_VPRE_EN
INT_HPRE
Edge Dectect
INT_HPRE
INT_HPRE_EN
INT_DVIPRE
Edge Dectect
INT_DVIPRE
INT_DVIPRE_EN
INT_FFOV
Edge Dectect
INT_FFOV
INT_FFOV_EN
INT_FFUN
Edge Dectect
INT_FFUV
INT_FFUV_EN
OR
IRQn
Clear Flags
IRQn Interrupt Source
Figure 6.13-1 IRQn Interrupt Block Diagram
INTHV_IRQ
INT_VFREQ
INT_HFREQ
INT_VPOL
INT_HPOL
INT_VEDGE
INT_HEDGE
INT_ISPRE
INT_ CSPRE
INT_VPRE
INT_HPRE
INT_DVIPRE
2008-05-05
Meaning
Vsync Frequency
Change
Hsync Frequency
Change
V-Polarity Change
INT
H-Polarity Change
INT
Vsync Edge INT
Hsync Edge INT
Interlaced Sync
INT
Composite Sync
INT
Vsync Present INT
Hsync Present INT
DVI sync Present
INT
Action
It will be activated when the Input frequency of Vsync
changes.
It will be activated when the Input frequency of Hsync
changes.
It will be activated when the Input Polarity of Vsync changes.
It will be activated when the Input Polarity of Hsync changes.
It will be activated when the Vsync rising edge is occur.
It will be activated when the Hsync rising edge is occur.
It will be activated when the Interlaced Sync is present.
It will be activated when the Composite Sync is present.
It will be activated when the Vsync is present.
It will be activated when the Hsync is present.
It will be activated when the DVI sync is present.
37
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
INT_FFOV
INT_ FFUV
INT_UPD_DDC0
INT_ UPD_DDC1
FIFO Overflow INT It will be activated when the FIFO is overflow
FIFO Underflow
It will be activated when the FIFO is underflow
INT
DDC0 updated
It will be activated when DDC0 Ram-Buffer contents
INT
updated.
DDC1 updated
It will be activated when DDC1 Ram-Buffer contents
INT
updated.
Table 6.13-1 IRQn Interrupt
6.14. 8031 On-Chip Microcontroller
Reference NT68667 MCU Spec.
2008-05-05
38
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
7. Electrical Specifications
Absolute Maximum Ratings
3.3V Supply voltage range, V3.3 (see Note1)…………………………………….-..0.3V to 4V
Output voltage range, VO…..……………….……………………………….………-0.3V to V33 +0.3V
Input voltage range (5V Tolerant), VI……………………….…………..…………-0.3V to V5V +0.3V
Electrostatic Discharge, VESD…………………….…………..…………………….2.0KV
ESD MM …………………………………………………………………………. 200V ( Class 2 )
Latch Up …………………………………………………………………………. .200mA ( Class 3 )
MSL………………………………………………………………………………...Class 3
Ambient Operating temperature, TA………………………………………….…....0C to 70C
Lead temperature 1, 6 mm (1/16 inch) from case for 10 seconds………………….260C
Junction temperature……………………………………………………….……...150C
Surface temperature.................................................................................................125C
Storage temperature range, Tstg……………………………………………..……...-40C to 125C
Storage humidity………………………….……..………………………..………..< 60% HR
Storage Life (Storage Temperature < 30 ℃)………………………………………1 year
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to this device. These are stress ratings
only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this
specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device
reliability.
Note1: Includes pins ADC_VAA, AVCC, PVCC, DVDD.
Note2: Includes pins CVDD, PLL_VDD
7.1. DC Electrical Characteristics
(TA = 25C, Oscillator freq. = 12.000MHz, unless otherwise specified)
Symbol
VCVDD
VPLL
Parameter
IADC
ITMDS
IDD33
1.8 V digital power supply
PLL power supply
R/G/B channel ADC analog
power supply
TMDS analog power supply
TMDS PLL power supply
Display interface power
supply
ADC power supply current
TMDS power supply current
3.3 V Operating current
IDDPD33
3.3 V Power down current
VADC
VTMDSA
VTMDSP
VDDD
VOH
Output high voltage
2008-05-05
Min.
Typ.
Max.
Power Requirements
1.6
1.8
2.0
1.6
1.8
2.0
Unit
Conditions
V
V
CVDD
PLL_VDD
3.15
3.3
3.47
V
ADC_VAA,
3.15
3.15
3.3
3.3
3.47
3.47
V
V
AVCC
PVCC
3.15
3.3
3.47
V
DVDD
150
160
200
mA
mA
mA
20
mA
Digital Outputs
2.0
39
VDD
V
Except ADC, TMDS
Inculde
ADC,TMDS.DVDD
IN_HSO, IN_VSO
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
VOL
VOH
Output low voltage
Output high voltage for open
drain type
GND
0.8
5
V
V
IOZ
IOH
Tri-State Leakage Current
Output high current
-25
-16
25
-2
uA
mA
IOL
Output low current
2
16
mA
PWM[6:9],PWMA,
PWMB,
DDC_SCL[1:0],
DDC_SCL[1:0],
PC0,PC1
(VOH = 2.5V)
DISP_DE, DISP_VS,
DISP_HS, DISP_CLK
GPO[8:1]
(VOL = 0.4V)
DISP_DE, DISP_VS,
DISP_HS, DISP_CLK
GPO[8:1]
LVDS Outputs
lVODl
Differential Steady-state
Output Voltage Magnitude
IVODI
Change in the Steady-state
Differential Output Voltage
Magnitude between
Opposite binary States
VOC(SS)
Steady-state Common-mode
Output Voltage
△
VOC(PP)
240
1.125
80
Short-circuit Output Current
IOZ
35
mV
1.475
V
RL = 100 ,
See Figure 7.1.1
See Figure 7.1.1
Peak-to-peak
Common-mode Output
Voltage
IOS
mV
Output Tri-State Current
150
mV
±24
mA
VO(TP) = 0
±12
mA
VOD = 0
μA
VO = 0 to Vcc
±1
Analog Input
VIAMIN
VIAMAX
VID
VICOM
Minimum Input Voltage
Range
Maximum Input Voltage
Range
Differential Input Voltage
Input Common Mode Voltage
2008-05-05
DVI Input
150
AVCC
300m
40
0.55
V p-p
0.9
V p-p VIAMAX
1200
AVCC37mV
mV
mV
See Figure 7.1.3
See Figure 7.1.3
Ver. 1.5
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for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
VBTD
Behavior when Transmitter is
disabled
VIH
Input high voltage
VIL
Input low voltage
VT+(HSYN Schmitt Trigger Positive
Going Threshold Voltage for
C)
HSYNC Inputs
VT-(HSYN Schmitt Trigger Negative
Going Threshold Voltage for
C)
HSYNC Inputs
VT+(VSYN Schmitt Trigger Positive
Going Threshold Voltage for
C)
VSYNC Inputs
VT-(VSYN Schmitt Trigger Negative
Going Threshold Voltage for
C)
VSYNC Inputs
VIHC
Clock high voltage
VILC
Clock low voltage
IIH
Input high current
IIL
Input low current
2008-05-05
V
AVCC
10mV
Digital Input
2.0
GND
1.5
1.6
AVCC
+
10mV
mV
See Figure 7.1.3
VDD
0.8
2.2
V
V
V
Y[7:0],
0.7
1.1
1.4
V
HSYNCI0, HSYNCI1
1.8
2.0
V
VSYNCI0, VSYNCI1
V
VSYNCI0, VSYNCI1
V
V
μA
μA
YUV_CLK,
0.8
2.0
GND
-25
-25
41
1.5
VDD
0.4
25
25
HSYNCI0, HSYNCI1
(VIH = 2.5V)
(VIL = 0.4V)
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
49.91% (2 Places)
TP
VOD
Voc
TM
CL = 10 pF Max
(2 Places)
(a)SCHEMATIC
100%
80%
VOD(H)
0V
OD(L)
V
20%
0%
t
tr
f
VOC(PP)
OC(SS)
OC(SS)
V
V
0V
7 WAVEFORMS
Figure 7.1-1 Test Load and Voltage Definitions for LVDS Outputs
3.0V
VDD
>0.5ms
RSTn
2.5V
Internal Register Initial Period
Programmed Timing
All output
Power -up Sequence
Figure 7.1-2 Power-up Sequence
2008-05-05
42
Ver. 1.5
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for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
RX+
AVCC
V ID
RXV ICOM
Figure 7.1-3 DVI Single-ended Differential Signal
2008-05-05
43
Ver. 1.5
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for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
7.2. AC Electrical Characteristics
(VDD=3.3V, TA=25C, Oscillator freq.=12MHz, unless otherwise specified)
ADCPLL
Phase-locked loop
Symbol
Parameter
jPLL
Short term jitter
Conditions
fclkout=188MHz
fclkout=188MHz
Divider ratio
Input HS frequency range
For normal type
Output clock frequency range For H type
For U type
In start-up conditions
PLL capture time
CKOUT clock duty cycle
165 MHz output
Long term jitter
DR
fCLKIN
fCLKOUT
tCAP
δ
Clamping Pulse
Symbol
Parameter
tDELAY
Clamp pulse delay time
Conditions
CLAMP_BEG<5:0>=0x00
CLAMP_BEG<5:0>=0x0F
tWIDTH
Clamp pulse width
tCOR1
Clamp correction time to
within ±10 mV
tCOR2
Clamp correction time to
less than 1 LSB
CLAMP_WID<5:0>=0x01
CLAMP_WID<5:0>=0x0F
±100mV black level input
variation; clamp capacitor
= 4.7nF
±100mV black level input
variation; clamp capacitor
= 4.7nF
Analog-to-Digital Converter
Symbol
Parameter
fs
Sampling frequency
Channel to channel
match
Input signal voltage
Vin(p-p)
(peak-peak)
DC differential non
DNL
linearity
GMATCH
2008-05-05
Conditions
Min
2
15
15
15
15
45
Typ
120
0.6
50
Max
4096
110
166
188
190
5
55
Unit
Min
-
Typ
0
15
1
15
Max
-
Unit
4/CKOUT
4/CKOUT
4/CKOUT
4/CKOUT
-
-
300
ns
-
-
10
Lines
ps
ns
KHz
MHz
ms
%
Min
Typ
Max
For normal type
15
-
166
For H type
15
188
For U type
15
190
Corresponding to full scale
output
From analog input to digital
output; ramp input;
44
Unit
MHz
-
2
5
%
0.55
0.7
0.9
V
-
±0.5
LSB
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
INL
DC integral non linearity
ENOB
Effective number of bits
THD
From analog input to digital
output; ramp input;
From analog input to digital
output;10KHz sine wave input;
ramp input
Input 1V(p-p) and 10MHz
LSB
-
±0.6
-
7
-
bits
-
-
1
%
No Missing Codes is guaranteed.
Signal-to-Noise Ratio
Symbol
Parameter
S/N
Signal-to-noise ratio
Conditions
Maximum gain
Minimum gain
Min
-
Typ
45
44
-
Max
-
Unit
dB
dB
TMDS Receiver
TMDS Receiver
Symbol
Parameter
Conditions
fOP
Operating Frequency range
tJJT
Jitter tolerance
tSTART
Receiver Startup Time
Intra-Pair (+ to -) Differential
tDPS
165MHz 1 pixel/clock
Input Skew
Channel to Channel
tCCS
165MHz 1 pixel/clock
Differential Input Skew
CIN
TMDS Input Pin Capacitance
Min
25
2
-
Typ
-
-
7
Max
165
10
Unit
MHz
ns
ms
250
ps
5.0
ns
-
pF
Sync Processor (Oscillator freq.=12MHz)
H/V Sync Processor
Symbol
Parameter
fVSYNC
Vsync Input Frequency
Vsync Input Frequency for
fVCLK
DDC-1 Mode
tVPW
VSYNC input Pulse Width
fHSYNC
Hsync Input Frequency
tHPW
HSYNC input Pulse Width
tHPW(COMP) HSYNC input Pulse Width
tHTTT(COMP) Horizontal total time
Conditions
Vsync Duty Cycle = 40%
Supply VCLK for DDC-1
mode only
Vsync Duty Cycle < 40%
Hsync Duty Cycle = 40%
Hsync Duty Cycle < 40%
Hsync Duty Cycle < 40%
2008-05-05
45
Min
15
Typ Max
250
Unit
Hz
-
-
25
KHz
15
8.66
-
2.5
250
8.66
8.66
ms
KHz
us
us
us
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
td7
CLKIN
(RFB=0)
CLKIN
(RFB=1)
TCLK
td0
TD7
Tn
TD6
TD4
TD3
TD2
TD1
TD0
TD7+1
TD6+1
td1
td 2
td 3
td4
td5
td 6
2.5V
CLKIN
VOD(H)
TCLK
or
Tn
1.4V
0.5V
0.00V
VOD(L)
td 7
td 0 - td 6
Figure 7.2-1 LVDS Timing Definitions
PWDN
TCLK
ten
Invalid
TDn
CLKIN
Valid
Figure 7.2-2 LVDS Enable Time Waveforms
CLKIN
tdis
PWDN
TCLK
Figure 7.2-3 LVDS Disable Time Waveforms
2008-05-05
46
Ver. 1.5
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for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
8.
Registers Mapping
Block Name
Byte Offset
ADC PLL Interface
DVI Input Control 1
Graphic Port Control
Video Port Control
Back End Image Processing
NR Control
GPIO Control
PWM Control
DDC Control
OSD Control
Index Port Access Control
Misc. Access Control
HS Digital PLL
Display Digital PLL & SSC
Page 0
0x000 ~ 0x017
0x018 ~ 0x01E
0x020 ~ 0x03F
0x040 ~ 0x05F
0x060 ~ 0x064
0x068 ~ 0x06F
0x070 ~ 0x073
0x074 ~ 0x077
0x078 ~ 0x07D
0x080 ~ 0x0CF
0x0E0 ~ 0x0E3
0x0E5 ~ 0x0E6
0x0D0 ~ 0x0EF
0x0F0 ~ 0x0F7
Power Control
Auto Tune
Bright Frame Display
Display General Control
Sync Processor
sRGB Control
Page 1
0x101 ~ 0x102
0x106 ~ 0x12F
0x130 ~ 0x13B
0x150 ~ 0x18F
0x196 ~ 0x1B0
0x1D0 ~ 0x1DF
Timing Control
Page 2
0x200 ~ 0x2FF
HDCP
Dithering Control
Non-Linear Scaling Adjust
Bright Frame
Dynamic Backlight Control
Page 3
0x300 ~ 0x36F
0x370 ~ 0x371
0x380 ~ 0x38B
0x390 ~ 0x3FE
0x430 ~ 0x43F
2008-05-05
Page 4
47
Ver. 1.5
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for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
8.1. ADC Interface
0x000
ADCPLL Control
Bits
7-5
4
Name
HPLL_HSYNC_SEL
3
HSYNC_SEL
2-0
Default: 1010 0000B
0x001
Bits
7-0
Description
Reserved
HPLL Hsync input signal selection
0: HSYNCI ( from HSYNCI )
1: SYNC_HS ( from sync processor )
HPLL Hsync input signal selection
0: HSYNCI ( from HSYNCI )
1: SOGI
Reserved
Red Channel Gain Control
Name
RGAIN[8:1]
R/W
R/W
Description
The RAGAIN[7:0] that sets the gain of the R channel. The ADC can
accommodate input signals with a full-scale range of between 0.55V and
0.9Vp-p. Note that increasing RGAIN results in the picture having less
contrast.
Default: 1000 0000B
0x002
ADC Common Mode
Bits Name
7-0
Default: 1000 0000B
0x003
Bits
7-0
Description
ADC common voltage compensation
Red Channel DC Shift Control
Name
RCSC [7:0]
R/W
R/W
Description
Control the R channel DC shift value to compensate the color excursion.
Bigger value gives less brightness.
Default: 1000 0000B
0x004
Bits
7-0
Green Channel Gain Control
Name
GGAIN[8:1]
R/W
Description
The GAGAIN[7:0] that sets the gain of the G channel. The ADC can
accommodate input signals with a full-scale range of between 0.55V and
0.9Vp-p. Note that increasing GGAIN results in the picture having less contrast.
Default: 1000 0000B
0x005
ADC GAIN RANGE
Bits Name
7-0
Default: 0000 0000B
0x006
Bits
7-0
Description
ADC gain range compensation
Green Channel DC Shift Control
Name
GCSC [7:0]
R/W
R/W
Description
Control the G channel DC shift value to compensate the color excursion.
Bigger value gives less brightness.
Default: 1000 0000B
2008-05-05
48
Ver. 1.5
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for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x007
Bits
7-0
Blue Channel Gain Control
Name
BGAIN[8:1]
R/W
Description
The BAGAIN[7:0] that sets the gain of the B channel. The ADC can
accommodate input signals with a full-scale range of between 0.55V and
0.9Vp-p. Note that increasing BGAIN results in the picture having less contrast.
Default: 1000 0000B
0x008
ADC Channel and MID Clamp Control
Bits
7-3
2
Name
CHANNEL_SEL
1
BMID
0
RMID
R/W
Description
Reserved
ADC channel
0: Disable
1: Enable
Blue Clamp Select
0: Clamp to ground
1: Clamp to midscale
Red Clamp Select
0: Clamp to ground
1: Clamp to midscale
Default: 0000 0100B
0x009
Bits
7-0
Blue Channel DC Shift Control
Name
BCSC[7:0]
R/W
Description
Control the B channel DC shift value to compensate the color excursion.
Bigger value gives less brightness.
Default: 1000 0000
0x00A ~ 0x00D : Reserved
0x00E
ADC PLL Power-up Control
Bits Name
7-6
5
BGAIN[0]
4
GGAIN[0]
3
RGAIN[0]
2
PU_B_ADC
1
PU_G_ADC
0
PU_R_ADC
Default: 1111 1111B
Description
Reserved
BGAIN bit 0
GGAIN bit 0
RGAIN bit 0
1= Power-up B channel A2D converter.
1= Power-up G channel A2D converter.
1= Power-up R channel A2D converter.
R/W
0x00F : Reserved
0x010
Bits
7-3
2-1
Analog Bandwidth Control
Name
ADC_BW
[2:0]
2008-05-05
R/W
Description
Reserved
Analog bandwidth select , Bit2 set from 0x1ED.5
011:500M
111:450M
110:400M
49
Ver. 1.5
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for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0
Default: 0000 0110B
101:350M
010:300M
100:250M
001:150M
000:75M
Reserved
0x011 : Reserved
0x012
Bits
7-3
SOG Slicer Control
R/W
Name
SOG_THR
[4:0]
Description
The comparator threshold of the Sync-on-Green Slicer to be adjusted.
This register adjust it in steps of 10 mV, with the setting
100 mV <= SOG_THR <=400 mV
2
EN_SOG_SLICER Enable internal SOG Slicer.
0 = Disable
1 = Enable
1-0
Reserved
Default: 0111 1100B
0x013
Bits
7-2
1-0
White Balance Control
Name
VREF[1:0]
R/W
Description
Reserved
Select the signal source for VGA input. When VR1 is selected, the PLL will
go into free-run state.
00: VR0. Internal zero voltage.
01: Add resistor between external RGB and A/D circuit , the ADC
bandwidth is decided by the two bit and 0x010[2:1]
10: VR1. Internal reference voltage 1. (0.7V)
11: Normal. From external RGB input pin.
Default: 0000 0011B
0x014
Hsync Trigger Level Control
Bits
7
6-4
Name
HS_THR_H
3
2-0
HS_THR_L
R/W
Description
Reserved
The trigger level threshold of the sync high level to be adjusted.
This register adjust it in steps of 100 mV, with the setting
1500 mV <= HS_THR_H <=2000 mV
Reserved
The trigger level threshold of the sync low level to be adjusted.
This register adjust it in steps of 100 mV, with the setting
950 mV <= HS_THR _L<=1400 mV
Default: 0000 0000B
0x015
Vsync Trigger Level Control
Bits
7
Name
VS_SCHMITT
6-4
VS_THR_H
2008-05-05
R/W
Description
VSI uality triggle
0: Disable
1: Enable
The trigger level threshold of the sync high level to be adjusted.
50
Ver. 1.5
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for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
3
2-0
VS_THR_L
This register adjust it in steps of 100 mV, with the setting
1500 mV <= VS_THR_H <=2000 mV
Reserved
The trigger level threshold of the sync low level to be adjusted.
This register adjust it in steps of 100 mV, with the setting
950 mV <= VS_THR _L<=1400 mV
Default: 0000 0000B
8.2. DVI Input Control 1
0x016
DVI Clock Detection
Bits
Name
7-0
DVI_CLK
Default: XXXX XXXXB
Description
DVI clock detection , unit : Mhz
R
0x017 : Reserved
0x018
Bits
7-5
4
3
DVI Control
Name
SYNC_SEL
2-0
Default: 0000 0000B
0x019
R/W
Description
Reserved
For internal circuit DVI control , force to “0” for normal operate
Sync is generated from R channel or B channel
0 = From B Channel (RX0)
1 = From R Channel (RX2)
Reserved
DVI Control
Bits Name
7-0
Default: 0000 0000B
R/W
Description
For internal circuit DVI control
0x01A : Reserved
0x01B
Bits
7-4
3-1
DVI Control
R/W
Name
Description
Reserved
DVI_FILT_ADJ
DVI noise filter
000 : Weakness
111 : Strength
0
DVI_NOISE_FIL Noise filter
0: Disable
1: Enable
Default: 0000 0000B
0x01C : Reserved
0x01D
Bits
7-4
DVI Control
Name
2008-05-05
R/W
Description
Reserved
51
Ver. 1.5
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for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
3-0
DVI_PLL_BW
DVI PLL frequence range control
0000 : Low frequency
1111 : High frequency
Default: 0000 0000B
0x01E
Bits Name
7-0
DVI_EQ_DATA
Default: 0000 0000B
2008-05-05
DVI Control
R/W
Description
Equalizer bias current control
52
Ver. 1.5
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for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
8.3. Pre-Pattern Control
0x01F
Bits
7
6
5
4
3-0
Pre-Pattern Control
R/W
Name
PRE_PATT_EN
Description
Pre-Pattern Enable.
0 = Disable
1 = Enable
PRE_INV
Pre-Pattern Data invert
0 = Normal
1 = Invert the RGB Data
PRE_CBAR_EN Paste a Cross Bar on the built-in Pre-pattern and the Bar’s gray level is
controlled via CBAR_FG[7:0] register (0x15A)
0 = Disable
1 = Enable
PRE_PATT_BK Built-in pre-pattern bank Select
0 = Bank 0
1 = Bank 1
PRE_PATT_SEL Select built-in pre-pattern type
[3:0]
Pattern number = 0~7
If PRE_PATT_BK = Bank 0
0000 = Reserved
0001 = Dot Moiré
0010 = Vertical Line Moire (1B1W)
0011 = Vertical Line Moire (2B1W)
0100 = Vertical Line Moire (2B2W)
0101 = 256 V_Gray Bar
0110 = 256 H_Gray Bar
0111 = Horizontal Line Moire (1B1W)
1000 = Horizontal Line Moire (2B1W)
1001 = Horizontal Line Moire (2B2W)
1010 = Chat Pattern
1011 = White Pattern
11xx = Rectangular pattern, outline width is defined by xx bits.
00 = 1 pixel
01 = 3 pixels
10 = 5 pixels
11 = 7 pixels
If PATT_BK = Bank 1
0000 = Black pattern
0001~1111 = Reserved
Default: 0000 0000B
8.4. Graphic Port Control
ADC/TMDS/Digital input source selection
Clamp pulse
Interlace decision window
Mask window
Capture window
2008-05-05
53
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
General Control
0x020
Graphic Port Control
R/W
Bits
7
Name
Description
GI_VSYNC_EDGE Mask window and capture Vsync referenced edge
0 = Leading edge
1 = Trailing edge
6
GI_IFLD_INV
Invert the internal field reference signal for data merging priority
0 = Normal
1 = Invert
5
GI_MKWIN_EN
Mask Window Enable. When GI_MKWIN_EN =1, GI_HMASK_BEG,
GI_HMASK_END, GI_VMASK_BEG and GI_VMASK_END are used to set
the window around the HSYNC and VSYNC during which the captured
data is 0x000 and auto tune is ignored. This filters out noise occurring on
the RGB channels around the HSYNC and VSYNC pulse.
0 = Disable
1 = Enable
4
GI_WRAP_SEL
Wrap around method select. ( see the figure as below )
0 = Wrap around
1 = Wrap black
3
GI_HSYNC_EDGE Mask window and capture H sync referenced edge.
0 = Leading edge
1 = Trailing edge
2
GI_INTE_EN
Interlaced input enable. When GI_INTE_EN =1, the field status is reference
to internal field detector.
0 = Non-interlaced
1 = Interlaced
1
GI_SRC_SEL
Graphic input source select
0 = ADC
1 = TMDS
0
GI_CAP_EN
Graphic input capture enable
0 = Disable
1 = Enable
Default: 0000 0000B
2008-05-05
54
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Current H
Display Area
WRAP Disable
0x021
H Blanking Area
Current H
Display Area
Next H Area
Clamp Pulse Begin
Bits
7
Name
CLAMP_EDG
6
CLAMP_POL
5-0
CLAMP_BEG
[5:0]
WRAP Enable
H Blanking Area
Next H Area
R/W
Description
Clamp Pulse Reference Edge
0 = GHS rising edge
1 = GHS falling edge
Clamp Pulse Polarity.
0 = Active Low
1 = Active High
Clamp Pulse Begin. (Unit 4xCLP_REFCLK = 4xCapture Clock)
CLAMP_BEG =5, means waiting 5 x 4CLP_REFCLK after GHS edge to
begin the pulse.
Default: 0000 0000B
0x022
Clamp Pulse Width
Bits
7
Name
CLAMP_EN
6
CLP_CLK_SEL
5-0
CLAMP_WID
[5:0]
Default: 0000 1111B
0x023
Bits
7
6
5
R/W
Description
Clamp Pulse Enable
0 = Disable
1 = Enable
Clamp Pulse Reference clock (CLP_REFCLK = Capture Clock) Select
0 = CLP_REFCLK
1 = 2 x CLP_REFCLK
Clamp Pulse Width.(unit 4xCLP_REFCLK = Capture Clock)
CLAMP_WID =5, means pulse width being 6 x 4CLP_REFCLK wide.
Digital Port Input Control
R/W
Name
Description
YpbPr_EN
YpbPr Input Enable
CLAMP_SOURCE Clamp source select.
0 = Selects Row Hs to be used for clamping.
1 = Selects Sync Separated Hsync to be used for clamping.
HS_DEJITTER_EN For TMDS input mode, This bit enables/disable the HSYNC De-jitter
2008-05-05
55
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
4
DEJITTER_RST
3
HCAP_DE_EN
2
1
DVI_DE_AUTO
0
SYNC_SEL
function.
0 = Disable
1 = Enable
For TMDS input mode, De-jitter reset
0 = Normal
1 = Reset
For TMDS input mode, active data is enclosed by DE signal. Hardware can
automatically capture the first data and bypass the setting of capture begin
registers (0x034~0x035). This bit is effective if DVI_SYNC_SEL=1 (0x196
bit 7).
0 = According to horizontal capture registers
1 = According to DE signal
Reserved
DVI DE auto detection control
0: Disable auto DE mode
1: Enable auto DE mode , if input negative DE then invert DE polarity
Sync processor input path selection
0: Graphic
1: Video
Default: 0000 0000B
0x024
Fast Mute Delay
R/W
Bits
7-4
Name
Description
FAST_MUTE_DELAY While input HS mute , delay this programmable delay time , fast mute
enable .
“1000” : 1024/Ref.CLK
“1100” : 512/Ref.CLK
“1110” : 256/Ref.CLK
3-0
Reserved
Default: 0000 0000B
0x025
ADCLK Delay & Invert Control
Bits
7
6
Name
CLKI_INV
5-4
3-0
CLKI_DLY
R/W
Description
Reserved
Internal data latch clock invert
0 = Normal
1 = Invert
Reserved
Internal data latch clock delay (0.5nS/step)
0~15 step
Default: 0000 0000B
0x026
Bits
7
6
5
Data Delay & Swap Control
R/W
Name
Description
CLAMP_MASK_EN Clamping pulse mask in V blanking interval
0: Disable
1: Enable
Reserved
CAP_RB_SWAP
Capture R/B channel swap
0 = Normal
1 = Swap
2008-05-05
56
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
4-3
2
CAP_BIT_SWAP
1-0
Default: 0000 0000B
Reserved
Capture data bit swap D7-D0 -> D0-D7
0 = Normal
1 = Swap
Reserved
0x027 ~ 0x29 : Reserved
Mask Window Define
0x02A
Bits
7-0
Name
GI_HMASK_BEG
[7:0]
Horizontal Mask Window Begin
R/W
Description
Horizontal Mask Window Begin. When GI_MKWIN_EN =1, this register
sets the number of clocks after the referenced edge (CR:0x020[3]) of the
HSYNC pulse in which the captured data is ‘0x00’ and the auto-tune starts
outside this window.
Default: 0000 0000B
0x02B
Bits
7-0
Horizontal Mask Window End
Name
GI_HMASK_END
[7:0]
R/W
Description
Horizontal Mask Window End. When GI_MKWIN_EN =1, this register
sets the number of clocks before the referenced edge (CR:0x020[3]) of
the HSYNC pulse in which the captured data is ‘0x00’ and the auto-tune
stops.
Default: 0000 0000B
0x02C
Bits
7-0
Vertical Mask Window Begin
Name
GI_VMASK_BEG
[7:0]
R/W
Description
Vertical Mask Window Begin. When GI_MKWIN_EN =1, this register sets
the number of lines after the referenced edge (CR:0x020[7]) of the VSYNC
pulse in which the captured data is ‘0x00’ and auto-tune starts outside this
window.
Default: 0000 0000B
0x02D
Bits
7-0
Vertical Mask Window End
Name
GI_VMASK_END
[7:0]
R/W
Description
Vertical Mask Window End. When GI_MKWIN_EN =1, this register sets
the number of lines before the referenced edge (CR:0x020[7]) of the
VSYNC pulse in which the captured data is ‘0x00’ and the auto-tune
stops.
Default: 0000 0000B
2008-05-05
57
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
CAP_HWID
VS
HS
CAP_VLEN
CAP_VBEG
CAP_HBEG
Active
Capture Window Control
Figure 8.4-1
Capture Window Control
0x02E
Capture Vertical Begin for Odd Field –lo
Bits
7-0
Name
GI_CAP_VBEGO
[7:0]
R/W
Description
Vertical Capture Begin for Odd Field. GI_CAP_VBEGO indicates how
many lines to wait after referenced edge (CR:0x020[7]) of VSYNC before
starting image capture. GI_CAP_VBEGO =3, means waiting 3 lines to
begin capture. This register is double-buffered.
Default: 0000 0000B
0x02F
Bits
7-3
2-0
Capture Vertical Begin for Odd Field –hi
Name
GI_CAP_VBEGO
[10:8]
Default: 0000 0000B
0x030
Bits
7-0
Description
Reserved
MSB of GI_CAP_VBEGO.
This register is double-buffered.
Capture Vertical Begin for Even Field –lo
Name
GI_CAP_VBEGE
[7:0]
R/W
R/W
Description
Vertical Capture Begin for Even Field. GI_CAP_VBEGE indicates how
many lines to wait after referenced edge (CR:0x020[7]) of VSYNC before
starting image capture. GI_CAP_VBEGE =3, means waiting 3 lines to
begin capture. This register is double-buffered.
Default: 0000 0000B
0x031
Bits
7-3
2-0
Capture Vertical Begin for Even Field –hi
Name
GI_CAP_VBEGE
[10:8]
Default: 0000 0000B
2008-05-05
R/W
Description
Reserved
MSB of GI_CAP_VBEGE.
This register is double-buffered.
58
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x032
Bits
7-0
Capture Vertical Length –lo
Name
GI_CAP_VLEN
[7:0]
R/W
Description
Vertical Capture Length. GI_CAP_VLEN indicates how many lines to
capture. GI_CAP_VLEN = 3, means capturing 3 lines.
This register is double-buffered.
Default: 0000 0000B
0x033
Bits
7-3
2-0
Capture Vertical Length –hi
Name
GI_CAP_VLEN
[10:8]
Default: 0000 0000B
0x034
Bits
7-0
Description
Reserved
MSB of GI_CAP_VLEN.
This register is double-buffered.
Capture Horizontal Begin –lo
Name
GI_CAP_HBEG
[7:0]
R/W
R/W
Description
Horizontal Capture Begin. GH_CAP_HBEG indicates how many pixels to
wait after referenced edge (CR:0x020[3]) of HSYNC before starting image
capture. GH_CAP_HBEG =3, means waiting 3 pixels to begin capture.
This register is double-buffered.
Default: 0000 0000B
0x035
Bits
7-4
3-0
Capture Horizontal Begin –hi
Name
GI_CAP_HBEG
[11:8]
Default: 0000 0000B
0x036
Bits
7-0
Description
Reserved
MSB of GI_CAP_HBEG.
This register is double-buffered.
Capture Horizontal Width –lo
Name
GI_CAP_HWID
[7:0]
R/W
R/W
Description
Horizontal Capture Width. GI_CAP_HWID indicates how many pixels to
capture. GI_CAP_HWID = 3, means capturing 3 pixels.
This register is double-buffered.
Default: 0000 0000B
0x037
Bits
7-4
3-0
Capture Horizontal Width –hi
Name
GI_CAP_HWID
[11:8]
Default: 0000 0000B
R/W
Description
Reserved
MSB of GI_CAP_HWID.
This register is double-buffered.
0x038
Capture CLK Invert
Bits
Name
7-5
4
3-0
Default: 0000 0000B
Description
Reserved
Capture CLK invert
Reserved
R/W
0x039 ~ 0x3B : Reserved
2008-05-05
59
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x03C
DVI Input Horizontal Active Width-lo
Bits
7-0
Name
DVI_CAP_HWID
[7:0]
Default: XXXX XXXXB
Description
The active window horizontal width. The value is valid only for DVI
interface is enabled and the SYNC input source is from DVI DE signal
0x03D
DVI Input Horizontal Active Width-hi
Bits
3-0
Name
DVI_CAP_HWID
[11:8]
Default: XXXX XXXXB
0x03E
Description
MSB of DVI_CAP_HWID
Bits
7-0
Name
DVI_CAP_VLEN
[7:0]
Default: XXXX XXXXB
Description
The active window vertical length. The value is valid only for DVI interface
is enabled and the SYNC input source is from DVI DE signal
0x03F
DVI Input Vertical Active Length-hi
Bits
2-0
Description
MSB of DVI_CAP_VLEN
Name
DVI_CAP_VLEN
[10:8]
Default: XXXX XXXXB
2008-05-05
DVI Input Vertical Active Length-lo
60
R
R
R
R
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
8.5. Video Port Control
General Control
0x040
Bits Name
7-5
4
UV_SWAP
3-2
1
VI_INTE_EN
0
VI_CAP_EN
Video Port Control 1
R/W
Description
Reserved
Swap the order of received UV data.
0 = Normal
1 = Swap
Reserved
Interlaced input enable
0 = Non-interlaced
1 = Interlaced
Input capture enable
0 = Disabled
1 = Enabled
Default: 0000 0000B
0x041
Video Port Control 2
R/W
Bits Name
Description
7-6
Reserved
5
VI_CAP_656_AUTO For BT656 mode, when VI_CAP_656_AUTO = “1”. Hardware referee to the
setting of capture registers to capture the active data
0 = Disable
1 = Enable
4
VI_MKWIN_EN
Mask Window Enable. When VI_MKWIN_EN =1, VI_HMASK_BEG,
VI_HMASK_END, VI_VMASK_BEG and VI_VMASK_END are used to set
the window around the HSYNC and VSYNC during which the captured data
is 0x00 and auto tune is disabled. This filters out noise occurring on the
RGB channels around the HSYNC and VSYNC pulse.
0 = Disable
1 = Enable
3
VI_WRAP_SEL
Wrap around method select
0 = Wrap around
1 = Wrap black
2
VI_SYNC_EDGE
Select the H/V sync reference edge.
0 = Leading edge
1 = Trailing edge
1
VCAP_656_EN
For BT656 mode, active data is enclosed by SAV/EAV code. Hardware can
automatically capture the active data and bypass the setting of capture
registers except the Horizontal Capture Width.
0 = According to vertical capture registers
1 = According to SAV/EAV code
0
HCAP_656_EN
For BT656 mode, active data is enclosed by SAV/EAV code. Hardware can
automatically capture the active data and bypass the setting of capture
registers except the Horizontal Capture Width.
0 = According to horizontal capture registers
1 = According to SAV/EAV code
Default: 0000 0000B
0x042
2008-05-05
Polarity Control
61
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits
7-6
5
Name
4
VI_IFLD_INV
VI_656CLK_INV
3-0
Default: 0000 0000B
0x043
Bits
7-4
3-0
Description
Reserved
Invert the polarity of CLK for internal BT656 data processing unit
0 = Normal
1 = Invert
Invert the internal field reference signal for data merging priority
0 = Normal
1 = Invert
Reserved
VSYNC Delay
Name
VI_VSDLY
[3:0]
R/W
Description
Reserved
Delay the video port VSYNC pulse by input pixel clock to avoid the
confusion of 1st HSYNC recognized following VSYNC trailing edge.
0~15 pixels delay
Default: 0000 0001B
0x044 ~ 0x46 : Reserved
Mask Window Define
0x047
Bits
7-0
Name
VI_HMASK_BEG
[7:0]
Horizontal Mask Window Begin
R/W
Description
Horizontal Mask Window Begin. When VI_MKWIN_EN =1, this register
sets the number of clocks after the referenced edge (CR:0x041[2]) of the
HSYNC pulse in which the captured data is ‘0x00’ and the auto-tune starts
outside this window.
Default: 0000 0000B
0x048
Bits
7-0
Horizontal Mask Window End
Name
VI_HMASK_END
[7:0]
R/W
Description
Horizontal Mask Window End. When VI_MKWIN_EN =1, this register
sets the number of clocks before the referenced edge (0x041[2]) of the
HSYNC pulse in which the captured data is ‘0x00’ and the auto-tune
stops.
Default: 0000 0000B
0x049
Bits
7-0
Vertical Mask Window Begin
Name
VI_VMASK_BEG
[7:0]
R/W
Description
Vertical Mask Window Begin. When VI_MKWIN_EN =1, this register sets
the number of lines after the referenced edge (CR:0x041[2]) of the VSYNC
pulse in which the captured data is ‘0x00’ and auto-tune starts outside this
window.
Default: 0000 0000B
0x04A
Bits
7-0
Vertical Mask Window End
Name
VI_VMASK_END
[7:0]
2008-05-05
R/W
Description
Vertical Mask Window End. When VI_MKWIN_EN =1, this register sets
the number of lines before the referenced edge (CR:0x041[2]) of the
VSYNC pulse in which the captured data is ‘0x00’ and the auto-tune
62
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
stops.
Default: 0000 0000B
8.6. Color space conversion Control
Color Transfer Equation
R = Y601 + COEFA*(Cr-128)/512
G = Y601 – COEFB*(Cr-128)/512 – COEFC*(Cb-128)/512
B = Y601 + COEFD*(Cb-128)/512
SDTV
R = Y601 + 1.371(Cr-128)
G = Y601 – 0.698(Cr-128) – 0.336(Cb-128)
B = Y601 + 1.732(Cb-128)
HDTV
R = Y709 + 1.540(Cr-128)
G = Y709 – 0.459(Cr-128) – 0.183(Cb-128)
B = Y709 + 1.816(Cb-128)
Color Transfer Coefficient
0x04B
Color Transfer Coefficient D –lo
Bits
7-0
Name
COEFD
[7:0]
Default: 1011 1110B
Description
Video YUV/YpbPr to RGB Color Transfer Coefficient.
0~1023
0x04C
Color Transfer Coefficient D –hi
Bits
7-2
1-0
Name
COEFD
[9:8]
Default: 0000 0010B
Color Transfer Coefficient C –lo
Bits
7-0
Name
COEFC
[7:0]
Default: 0110 0101B
Description
Video YUV/YpbPr to RGB Color Transfer Coefficient.
0~1023
0x04E
Color Transfer Coefficient C –hi
Bits
1-0
Name
COEFC
[9:8]
Default: 0000 0001B
Description
MSB of COEFC
0x04F
Color Transfer Coefficient B –lo
Bits
7-0
Description
Video YUV/YpbPr to RGB Color Transfer Coefficient.
0~1023
2008-05-05
R/W
Description
Reserved
MSB of COEFD
0x04D
Name
COEFB
[7:0]
Default: 1010 1100B
R/W
63
R/W
R/W
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x050
Color Transfer Coefficient B –hi
Bits
1-0
Name
COEFB
[9:8]
Default: 0000 0000B
Description
MSB of COEFB
0x051
Color Transfer Coefficient A –lo
Bits
7-0
Name
COEFA
[7:0]
Default: 0111 0111B
Description
Video YUV/YpbPr to RGB Color Transfer Coefficient.
0~1023
0x052
Color Transfer Coefficient A –hi
Bits
1-0
Description
MSB of COEFA
Name
COEFA
[9:8]
Default: 0000 0011B
R/W
R/W
R/W
8.7. Video Port Capture Control
Capture Window Control
0x053
Bits
7-0
Name
VI_CAP_VBEGO
[7:0]
Vertical Capture Begin for Odd Field –lo
R/W
Description
ODD Field Vertical Capture Begin. VI_CAP_VBEGO indicates how many
lines to wait after referenced edge (CR:0x041[2]) of VSYNC before starting
image capture. VI_CAP_VBEGO =3, means waiting 3 lines to begin
capture.
This register is double-buffered.
Default: 0000 0000B
0x054
Vertical Capture Begin for Odd Field –hi
Bits
2-0
Name
VI_CAP_VBEGO
[10:8]
Default: 0000 0000B
0x055
Bits
7-0
Description
MSB of VI_CAP_BEG.
This register is double-buffered.
Vertical Capture Begin for Even Field –lo
Name
VI_CAP_VBEGE
[7:0]
R/W
R/W
Description
Even Field Vertical Capture Begin. VI_CAP_VBEGE indicates how many
lines to wait after referenced edge (CR:0x041[2]) of VSYNC before starting
image capture. VI_CAP_VBEGE =3, means waiting 3 lines to begin
capture.
This register is double-buffered.
Default: 0000 0000B
0x056
Bits
2-0
Name
VI_CAP_VBEGE
[10:8]
Default: 0000 0000B
2008-05-05
Vertical Capture Begin for Even Field –hi
R/W
Description
MSB of VI_CAP_VBEGE.
This register is double-buffered.
64
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x057
Bits
7-0
Vertical Capture Length –lo
Name
VI_CAP_VLEN
[7:0]
R/W
Description
Vertical Capture Length. VI_CAP_VLEN indicates how many lines to
capture. VI_CAP_VLEN =3, means capturing 3 lines.
This register is double-buffered.
Default: 0000 0000B
0x058
Vertical Capture Length –hi
Bits
2-0
Name
VI_CAP_VLEN
[10:8]
Default: 0000 0000B
Description
MSB of VI_CAP_VLEN.
This register is double-buffered.
0x059
Bits
7-0
Horizontal Capture Begin –lo
Name
VI_CAP_HBEG
[7:0]
R/W
R/W
Description
Horizontal Capture Begin. VI_CAP_HBEG indicates how many pixels to
wait after referenced edge (CR:0x041[2]) of HSYNC before starting image
capture. VI_CAP_HBEG =3, means waiting 3 pixels to begin capture.
This register is double-buffered.
Default: 0000 0000B
0x05A
Horizontal Capture Begin –hi
Bits
3-0
Name
VI_CAP_HBEG
[11:8]
Default: 0000 0000B
Description
MSB of VI_CAP_HBEG.
This register is double-buffered.
0x05B
Bits
7-0
Horizontal Capture Width –lo
Name
VI_CAP_HWID
[7:0]
R/W
R/W
Description
Horizontal Capture Width. VI_CAP_HWID indicates how many pixels to
capture. VI_CAP_HWID = 3, means capturing 3 pixels.
This register is double-buffered.
Default: 0000 0000B
0x05C
Horizontal Capture Width –hi
Bits
3-0
Name
VI_CAP_HWID
[11:8]
Default: 0000 0000B
R/W
Description
MSB of VI_CAP_HWID
This register is double-buffered.
0x05D ~ 0x5F : Reserved
8.8. Back End Image Processing
Back-end offset control
Back-end gain control
Back-end sharpness and smooth control
0x060
Back-end Horizontal Sharpness
Bits
7
Name
2008-05-05
R/W
Description
Reserved
65
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6
BK_H_ASRP
5
4
BK_H_SRPSMO
3-0
BK_H_SRP
[3:0]
Default: 0000 0000B
Graphic horizontal adaptive sharpness adjusting.
0 = Disable
1 = Enable
Reserved
Graphic horizontal back-end smooth and sharpness select.
0 = sharpness
1 = smooth
Graphic horizontal back-end sharpness/smooth adjusting.
16 steps
0x061 : Reserved
0x062
Gamma Fixed Bit
Bits
Name
7-6
5-4
3-2
1-0
Default: 0000 0000B
0x063
Description
Reserved
B[1:0] fixed “00” , “01” , “10” , “11”
G[1:0] fixed “00” , “01” , “10” , “11”
R[1:0] fixed “00” , “01” , “10” , “11”
Gamma Fixed Bit Enable
Bits
Name
7-3
2
1
0
Default: 0000 0000B
0x064
Name
TEXT_EN
[2:0]
4-3
V_INTE_TYPE
[1:0]
2-0
H_INTE_TYPE
[2:0]
R/W
Description
Reserved
B enable , gamma disable or gamma 10 bit out [1:0] = “00”
G enable ,
R enable
Interpolation Control
Bits
7-5
R/W
R/W
Description
Select the Text Mode type
000 = Normal Mode
001 = Level 1 Text Mode
010 = Level 2 Text Mode
011 = Level 3 Text Mode
1xx = Reserved
Select the Vertical interpolation type
00 = DSP (2-pixel)
01 = Bi-linear (2-pixel)
10 = Duplicate (2-pixel)
11 = Reserved
Select the Horizontal interpolation type
000 = Advanced DSP (4-pixel)
001 = Bi-linear (2-pixel)
010 = Duplicate (2-pixel)
011 = DSP (2-pixel)
100 = DSP (4-pixel)
101, 110, 111 = Reserved
Default: 0000 0000B
0x065
2008-05-05
Gamma Control
66
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits
7
Name
GAMMA_EN
6-0
Default: 0000 0000B
0x066
Bits
7-3
2-0
Description
Gamma Table Enable, When GAMMA_EN = 1, the Gamma Table can’t read
or write by host interface. When GAMMA_EN = 0 the display is bypass the
Gamma table.
0 = Disable
1 = Enable
Reserved
Back-end Vertical Sharpness
Name
INT_V_SHARP
[2:0]
Default: 0000 0000B
R/W
Description
Reserved
Vertical interpolation sharpness adjusting
8 steps
0x067 : Reserved
8.9. Noise Reduction Filter Control
0x068
Noise Reduction Filter Control
Bits
7
6
Name
NR2_EN
5
NR_ROUND
4
NR_EDGE_DET
3
2-0
NR_TYPE
R/W
Description
Reserved
Second Noise Reduction enable , NR2_THR[3:0] ( CR: 0x06B ) adjust the
threshold ( NR_TYPE = “001” , “010” , “011” )
0 = Disable
1 = Enable
Noise Reduction round calculation enable ( NR_TYPE = “001” , “010” ,
“011” )
0 = Disable
1 = Enable
Noise Reduction edge detection enable , NR_EDGE_THR[3:0] ( 0x069 )
adjust the threshold ( NR_TYPE = “001” , “010” , “011” )
0 = Disable
1 = Enable
Reserved
Select the Noise Reduction Filter type
000 = Normal Mode (NR disable)
001 = Mode 1
010 = Mode 2
011 = Mode 3 , NR_THR[3:0] ( 0x069 ) adjust the threshold
1xx = Reserved
Default: 0000 0000B
0x069
Bits
7-4
Name
NR_EDGE_THR
[3:0]
3-0
NR_THR
[3:0]
Default: 0000 0000B
2008-05-05
Noise Reduction threshold
R/W
Description
Edge Threshold of the noise reduction filter adjusting.
0x068[4] must be set “1”
Threshold of the noise reduction filter adjusting.
0x068[2:0] must be set “001” or “010” or “011”
67
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x06A
ADC High Pass Filter
Bits
7-6
5
Name
4
ADC_HPASS_EN
NR_DITHER _RST
3
2-0
ADC_HPASS
[2:0]
Default: 0000 0000B
0x06B
Bits
7-6
5
R/W
Description
Reserved
NR random dither reset mode ( 0x06B.4 NR_DITHER must set random
mode )
0 = Disable
1 = Enable
ADC high pass filter
0 = Disable
1 = Enable
Reserved
ADC high pass filter level
Seconded Noise Reduction threshold
R/W
Name
Description
Reserved
GHOST_CANCEL Ghost cancellation
0 = Disable
1 = Enable
4
NR_DITHER
NR dither mode :
0: Order mode
1: Random mode
3-0
NR2_THR
Threshold of the seconded noise reduction filter adjusting.
[3:0]
CR: 0x068[6] must be set “1”
Default: 0000 0000B
0x06C : Reserved
0x06D
Bits
7-6
5-4
NR Reset Dither Frame Invert
Name
NR_RST_INV
3-1
0
NR_RST_INV
Default: 0000 0000B
R/W
Description
Reserved
NR dither reset mode frame invert count
00: 1 frame
01: 2 frame
10: 3 frame
11: 4 frame
Reserved
NR dither reset mode frame invert enable
0x06E ~ 0x6F : Reserved
8.10. General Purpose Input Output (GPIO)
0x070
Bits
5
GPIO Port Control
Name
PWMA_EN
2008-05-05
R/W
Description
PWMA output enable (open-drain)
0 = Disable
1 = PWMA Enable
68
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
4
PWMB_EN
PWMB output enable (open-drain)
0 = Disable
1 = PWMB Enable
Reserved
3-0
Default: 0000 0000B
0x071 ~ 0x073 : Reserved
8.11. PWM Output
Frequency programmable
Duty cycle programmable
PWM_HCNT
PWM_LCNT
PWM_CLK
When clock source select from reference clock
F PWM_CLK F REFCLK (PWM_DIV 1 PWM_DIV 2 )
When clock source select from Display Hsync
F PWM_CLK F DISP _ HS (PWM_DIV 1 PWM_DIV 2 )
F PWM_CLK
F PWM
(PWM_HCNT PWM_LCNT)
PWM _ HCNT
Duty
( PWM_HCNT PWM_LCNT )
Duty F PWM_CLK
PWM _ HCNT
F PWM
(1 Duty ) F PWM_CLK
PWM _ LCNT
F PWM
PWM_HCNT
0
0
1~255
1~255
0x074
Bits
7-0
Name
PWMB_LCNT
[7:0]
Default: 0000 0000B
2008-05-05
PWM_LCNT
0
1~255
0
1~255
PWM Output
Tri-state
DC ‘0’
DC ‘1’
PWM pulse
PWMB Low Period Counter
R/W
Description
PWMB pulse low period counter value. Count with 12M or display HS
Double-buffered.
69
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x075
PWMB High Period Counter
Bits
7-0
Name
PWMB_HCNT
[7:0]
Default: 0000 0000B
0x076
Description
PWMB pulse high period counter value. Count with 12M or display HS
Double-buffered.
PWMA Low Period Counter
Bits
7-0
Name
PWMA_LCNT
[7:0]
Default: 0000 0000B
0x077
Name
PWMA_HCNT
[7:0]
Default: 0000 0000B
R/W
Description
PWMA pulse low period counter value. Count with 12M or display HS
Double-buffered.
PWMA High Period Counter
Bits
7-0
R/W
R/W
Description
PWMA pulse high period counter value. Count with 12M or display HS
Double-buffered.
0x078 ~ 0x7D : Reserved
0x07E
PWM Control 1
Bits
7
Name
PWMA_VS_LOCK
6-5
4
PWMA_DIV1
[1:0]
PWMA_CLK
3
PWMB_VS_LOCK
2-1
PWMB_DIV1
[1:0]
PWMB_CLK
0
R/W
Description
PWMA counter lock to display vertical sync
0 = Roll PWM counter over continuously
1 = Load PWM on Display VS (DISP_VS) leading edge
First divider–PWMA clock divide of the selected clock by
00 = 1; 01 = 2; 10 = 4; 11 = 8
PWMA clock source select
0 = Reference Clock
1 = Display HS (DISP_HS)
PWMB counter lock to display vertical sync
0 = Roll PWM counter over continuously
1 = Load PWM on Display VS (DISP_VS) leading edge
First divider–PWMB clock divide of the selected clock by
00 = 1; 01 = 2; 10 = 4; 11 = 8
PWMB clock source select
0 = Reference Clock
1 = Display HS (DISP_HS)
Default: 0000 0000B
0x07F
PWM Control 2
Bits
7
Name
PWMA_VSRESET
6
PWMB_VSRESET
5-4
2008-05-05
R/W
Description
PWMA reset counter on DSIP_VS leading edge
0 = Roll PWMA counter over continuously
1 = Reset PWMA on DISP_VS leading edge
PWMB reset counter on DSIP_VS leading edge
0 = Roll PWMB counter over continuously
1 = Reset PWMB on DISP_VS leading edge
Reserved
70
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
3-2
PWMA_ DIV2
1-0
PWMB_DIV2
[1:0]
Second divider–PWMA clock divide of the selected clock by
00 = 1;
01 = 16
10 = 256;
11 = 4096
Second divider–PWMB clock divide of the selected clock by
00 = 1;
01 = 16
10 = 256;
11 = 4096
Default: 0000 0000B
8.12. On Screen Display Registers
OSD Control
0x080
Bits
7
Name
ROT_EN
6
FLIP_EN
5
MIR_EN
4
WIN4_EN
3
WIN3_EN
2
WIN2_EN
1
WIN1_EN
0
OSD_EN
OSD and Window Enable Control
R/W
Description
Rotation control.
0: Normal
1: Rotated
Flip control
0: No flip
1: Flip ON
Mirror control
0: No mirror
1: Mirror ON
Enable Window 4
0: Disable
1: Enable
Enable Window 3
0: Disable
1: Enable
Enable Window 2
0: Disable
1: Enable
Enable Window 1
0: Disable
1: Enable
Enable OSD
0: Disable
1: Enable
Default: 0000 0000B
0x081
OSD Frame Horizontal Start – Low byte
Bits
7-0
Name
OSD_HS
[7:0]
Default: 0000 0000B
0x082
Bits
7-4
3-0
Description
OSD frame horizontal start low byte [7:0]. Specifies the horizontal starting
position of the OSD in pixel units. This register is double-buffered.
OSD Frame Horizontal Start – High Byte
Name
OSD_HS
[11:8]
2008-05-05
R/W
R/W
Description
Reserved
OSD frame horizontal start high byte [11:8]. Specifies the horizontal starting
position of the OSD in pixel units. This register is double-buffered.
71
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Default: 0000 0000B
0x083
Bits
7
5-0
OSD Frame Horizontal Width
Name
Description
Reserved
Specifies the width of the OSD in font units.
Range: 0~ 63 (OSD display width = 1~64)
OSD_HW
[5:0]
Default: 0000 0000B
0x084
OSD Frame Vertical Start Low byte
Bits
7-0
Name
OSD_VS
[7:0]
Default: 0000 0000B
0x085
Bits
7-3
2-0
R/W
Description
OSD frame vertical start low byte [7:0]. Specifies the vertical starting position
of the OSD in line units. This register is double-buffered.
OSD Frame Vertical Start High byte
Name
OSD_VS
[10:8]
Default: 0000 0101B
0x086
Bits
7-5
4-0
R/W
Description
Reserved
OSD frame vertical start high byte [10:8]. Specifies the vertical starting
position of the OSD in line units. This register is double-buffered.
OSD Frame Vertical Height
Name
OSD_VH
[4:0]
Default: 0000 0000B
0x087
R/W
R/W
Description
Reserved
Specifies the height of the OSD in font units.
Range: 0~31 (OSD display height = 1~32)
OSD Shift Row Offset
R/W
Bits
4-0
Name
Description
OSD_SHIFT_ROW Specifies the row of the OSD shift offset. Top row will shift to bottom and
like rolling function .
Range: 0~31
Default: 0000 0000B
0x088
Bits
7-0
OSD One Bit Font Address – Low Byte
Name
FONT1B_ADDR
[7:0]
R/W
Description
OSD one bit per pixel programmable font start address high byte [7:0].
Specifies the start address for the On-Chip programmable font.
Default for this 12 bit register = 1000 (dec)
Default: 1110 1000B
0x089
Bits
3-0
OSD One bit Font Address – High Byte
Name
FONT1B_ADDR
[11:8]
R/W
Description
OSD one bit per pixel programmable font start address high byte [11:8].
Specifies the start address for the On-Chip programmable font
Default for this 12 bit register = 1000 (dec)
Default: 0000 0011B
0x08A
2008-05-05
OSD Two Bit Font Address – Low Byte
72
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits
7-0
Name
FONT2B_ADDR
[7:0]
Description
OSD two bit per pixel programmable font start address high byte [7:0].
Specifies the start address for the On-Chip programmable font.
Default for this 12 bit register = 2656 (dec)
Default: 0110 0000B
0x08B
Bits
3-0
OSD Two Bit Font Address – High Byte
Name
FONT2B_ADDR
[11:8]
R/W
Description
OSD two bit per pixel programmable font start address high byte [11:8].
Specifies the start address for the On-Chip programmable font
Default for this 12 bit register = 2656 (dec)
Default: 0000 1010B
0x08C
Bits
7-0
OSD Three/Four Bit Font Address – Low Byte
Name
FONT4B_ADDR
[7:0]
R/W
Description
OSD three/four bit per pixel programmable font start address high byte
[7:0]. Specifies the start address for the On-Chip programmable font.
If 0x09F[7] = “1” , this register for three bit font address low byte
Default for this 12 bit register = 3808 (dec)
Default: 1110 0000B
0x08D
Bits
3-0
OSD Three/Four Bit Font Address – High Byte
Name
FONT4B_ADDR
[11:8]
R/W
Description
OSD three/four bit per pixel programmable font start address high byte
[11:8]. Specifies the start address for the On-Chip programmable font
If 0x09F[7] = “1” , this register for three bit font address high byte
Default for this 12 bit register = 3808 (dec)
Default: 0000 1110B
OSD Fade in/out Control
0x08E
OSD Fade-in / Fade-out Step
Bits
7-4
Name
FAD_V_STEP
[3:0]
3-0
FAD_H_STEP
[3:0]
Default: 0000 0000B
Description
OSD Vertical side Fade-in / Fade-out Step (4 pixel/step)
0~15 step
OSD Horizontal side Fade-in / Fade-out Step (4 pixel/step)
0~15 step
0x08F
OSD Fade-in / Fade-out Frequency
Bits
7
Name
FAD_EN
6-4
FAD_VFREQ
[2:0]
3-0
FAD_HFREQ
[3:0]
Default: 0000 0000B
OSD Zoom Control
0x090
2008-05-05
R/W
R/W
Description
Fade-in / Fade-out function enable.
0: Fade-in / Fade-out disable
1: Fade-in / Fade-out enable
OSD Fade-in / Fade-out Vertical Frequency for every step (4 frame/step)
OSD Fade-in / Fade-out Horizontal Frequency for every step (4 frame/step)
OSD Zoom Control for Separate Row Control Disable
73
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits
7-4
3
Name
2
HROW_ZMEN
1
VGLOB_ZMEN
0
HGLOB_ZMEN
VROW_ZMEN
Description
Reserved
Vertical Row Zoom Enable; Vertical zoom for all characters in one row
defined in Reg 0x09A ~ 0x09D.
0: Disable
1: Enable.
Horizontal Row Zoom Enable; Horizontal zoom for all characters in one row
defined in Reg 0x096 ~ 0x099.
0: Disable
1: Enable.
Vertical Global Zoom Enable; Vertical zoom for all characters in OSD
frame.
0: Disable
1: Enable.
Horizontal Global Zoom Enable; Horizontal zoom for all characters in OSD
frame.
0: Disable
1: Enable.
Default: 0000 0000B
0x090
Bits
7-6
OSD Zoom Control for Separate Row Control Enable
R/W
3-1
Name
Description
ROW_V_ZMRNG1 Row zoom range
[1:0]
This is a user definable zoom pattern. Pixels with ‘1’ pattern that define at
0x092 ~ 0x094 are duplicated according to the zoom range.
ROW_V_ZMRNG0 Row zoom range
[1:0]
This is a user definable zoom pattern. Pixels with ‘0’ pattern that define at
0x092 ~ 0x094 are duplicated according to the zoom range.
ROW_SPACE
Separate Row vertical space , the row select at 0x09F[4:0]
0
HGLOB_ZMEN
5-4
Row vertical zoom
0: Disable
1: Enable.
Default: 0000 0000B
0x091
Bits
7-0
OSD Font Horizontal Global Zoom Pattern – Low Byte
Name
HZM_PATN
[7:0]
R/W
Description
Least significant 8 bits (7:0) of the horizontal zoom pattern.
This is a user definable zoom pattern. Pixels with ‘1’ pattern are duplicated
according to the zoom range.
Default: 0000 0000B
0x092
Bits
7-6
5-4
3-0
OSD Font Horizontal/Vertical Global Zoom Pattern – High Byte
Name
VZM_PATN
[17:16]
HZM_PATN
[11:8]
2008-05-05
R/W
Description
Reserved
Most significant 2 bits (17:16) of the vertical zoom pattern.
This is a user definable zoom pattern. Pixels with ‘1’ pattern are duplicated
according to the zoom range.
Most significant 4 bits (11:8) of the horizontal zoom pattern.
This is a user definable zoom pattern. Pixels with ‘1’ pattern are duplicated
according to the zoom range.
74
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Default: 0000 0000B
0x093
Bits
7-0
OSD Font Vertical Global Zoom Pattern – Low Byte
Name
VZM_PATN
[7:0]
R/W
Description
Least significant 8 bits (7:0) of the vertical zoom pattern.
This is a user definable zoom pattern. Pixels with ‘1’ pattern are duplicated
according to the zoom range.
Default: 0000 0000B
0x094
Bits
7-0
OSD Font Vertical Global Zoom Pattern – Mid Byte
Name
VZM_PATN
[15:8]
R/W
Description
Bits (15:8) of the vertical zoom pattern.
This is a user definable zoom pattern. Pixels with ‘1’ pattern are duplicated
according to the zoom range.
Default: 0000 0000B
0x095
OSD Font Global Zoom Range
R/W
Bits
7-6
Name
Description
VGLOB_ZMRNG1 Vertical Global Zoom Pattern (Reg 0x092 ~ 0x094) ‘1’ Zoom Range
[1:0]
00: No Zoom
01: Vertical Zoom Pattern ‘1’ bits are duplicated once
10: Vertical Zoom Pattern ‘1’ bits are duplicated twice
11: Vertical Zoom Pattern ‘1’ bits are duplicated three times
5-4
HGLOB_ZMRNG1 Horizontal Global Zoom Pattern (Reg 0x091 ~ 0x092) ‘1’ Zoom Range
[1:0]
00: No Zoom
01: Horizontal Zoom Pattern ‘1’ bits are duplicated once
10: Horizontal Zoom Pattern ‘1’ bits are duplicated twice
11: Horizontal Zoom Pattern ‘1’ bits are duplicated three times
3-2
VGLOB_ZMRNG0 Vertical Global Zoom Pattern (Reg 0x092 ~ 0x094) ‘0’ Zoom Range
[1:0]
00: No Zoom
01: Vertical Zoom Pattern ‘0’ bits are duplicated once
10: Vertical Zoom Pattern ‘0’ bits are duplicated twice.
11: Vertical Zoom Pattern ‘0’ bits are duplicated three times.
1-0
HGLOB_ZMRNG0 Horizontal Global Zoom Pattern (Reg 0x091 ~ 0x092) ‘0’ Zoom Range
[1:0]
00: No Zoom
01: Horizontal Zoom Pattern ‘0’ bits are duplicated once
10: Horizontal Zoom Pattern ‘0’ bits are duplicated twice
11: Horizontal Zoom Pattern ‘0’ bits are duplicated three times
Default: 0000 0000B
0x096
Bits
7-0
Horizontal Row Zoom Control Row 7 – 0
Name
HROW_ZMPN
[7:0]
R/W
Description
Horizontal Row Zoom Pattern 7-0
Zooms each row horizontally defined as zoom range according to each bit.
Each bit controls a row correspondingly. Reg 0x090 [2] must be set to ‘1’.
Default: 0000 0000B
0x097
Bits
7-0
Horizontal Row Zoom Control Row 15 – 8
Name
HROW_ZMPN
[15:8]
2008-05-05
R/W
Description
Horizontal Row Zoom Pattern 15-8
Zooms each row horizontally defined as zoom range according to each bit.
75
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Each bit controls a row correspondingly. Reg 0x090 [2] must be set to ‘1’.
Default: 0000 0000B
0x098
Bits
7-0
Horizontal Row Zoom Control Row 23 – 16
Name
HROW_ZMPN
[23:16]
R/W
Description
Horizontal Row Zoom Pattern 23-16
Zooms each row horizontally defined as zoom range according to each bit.
Each bit controls a row correspondingly. Reg 0x090 [2] must be set to ‘1’.
Default: 0000 0000B
0x099
Bits
7-0
Horizontal Row Zoom Control Row 31 – 24
Name
HROW_ZMPN
[31:24]
R/W
Description
Horizontal Row Zoom Pattern 31-24
Zooms each row horizontally defined as zoom range according to each bit.
Each bit controls a row correspondingly. Reg 0x090 [2] must be set to ‘1’.
Default: 0000 0000B
0x09A
Bits
7-0
Vertical Row Zoom Control Row 7 – 0
Name
VROW_ZMPN
[7:0]
R/W
Description
Vertical Row Zoom Pattern 7-0
Zooms each row vertically defined as zoom range according to each bit.
Each bit controls a row correspondingly. Reg 0x090 [3] must be set to ‘1’.
Default: 0000 0000B
0x09B
Bits
7-0
Vertical Row Zoom Control Row 15 – 8
Name
VROW_ZMPN
[15:8]
R/W
Description
Vertical Row Zoom Pattern 15-8
Zooms each row vertically defined as zoom range according to each bit.
Each bit controls a row correspondingly. Reg 0x090 [3] must be set to ‘1’.
Default: 0000 0000B
0x09C
Bits
7-0
Vertical Row Zoom Control Row 23 – 16
Name
VROW_ZMPN
[23:16]
R/W
Description
Vertical Row Zoom Pattern 23-16
Zooms each row vertically defined as zoom range according to each bit.
Each bit controls a row correspondingly. Reg 0x090 [3] must be set to ‘1’.
Default: 0000 0000B
0x09D
Bits
7-0
Vertical Row Zoom Control Row 31 – 24
Name
VROW_ZMPN
[31:24]
R/W
Description
Vertical Row Zoom Pattern 31-24
Zooms each row vertically defined as zoom range according to each bit.
Each bit controls a row correspondingly. Reg 0x090 [3] must be set to ‘1’.
Default: 0000 0000B
0x09E
Bits
7-4
3-2
OSD Font Row Zoom Range
Name
VROW_ZMRNG [1:0]
2008-05-05
R/W
Description
Reserved
Vertical Row Zoom Range; The rows assigned by Vertical Row Zoom
Control registers will be zoomed up.
00: Vertical Zoom 1x for all fonts in the row
76
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
1-0
HROW_ZMRNG [1:0]
01: Vertical Zoom 2x for all fonts in the row
10: Vertical Zoom 3x for all fonts in the row
11: Vertical Zoom 4x for all fonts in the row
Horizontal Row Zoom Range; The rows assigned by Horizontal Row
Zoom Control registers will be zoomed up.
00: Horizontal Zoom 1x for all fonts in the row
01: Horizontal Zoom 2x for all fonts in the row
10: Horizontal Zoom 3x for all fonts in the row
11: Horizontal Zoom 4x for all fonts in the row
Default: 0000 0000B
0x09F
Separate ROW Control
R/W
Bits Name
7
Three_BIT_FONT
Description
Three bit font
0: Disable
1: Enable
6
SEPARATE_ROW_EN 32 separat row control
0: Disable
1: Enable
5
ROW_ACCESS
Row access
0: Disable
1: Enable
4-0 ROW_SELECT
32 row select
Default: 0000 0000B
OSD Translucent and Blinking Control
0x0A0
OSD Blink Control
Bits
7
6
Name
5
BS_BLINK
4-2
BLINK_FREQ
[2:0]
1-0
BLINK_RATE
[1:0]
OSD_BLINK
R/W
Description
Reserved
Blink
0=Blink control from font attribute bit 0.
1=OSD frame blink enable, don’t care the attribute bit 0.
Mask Border/Shadow at Blink
0= Character border/shadow will blink with the foreground of the character.
1=Character border/shadow will not blink with the foreground of the character.
Blink Frequency
000: Character foreground’s blinking period is 4 frames.
001: Character foreground’s blinking period is 8 frames.
010: Character foreground’s blinking period is 16 frames.
011: Character foreground’s blinking period is 32 frames.
100: Character foreground’s blinking period is 64 frames.
Blink Rate
00: Character foreground is turned 25% on / 75% off.
01: Character foreground is turned 50% on / 50% off.
10: Character foreground is turned 75% on / 25% off.
11: Reserved.
Default: 0000 0001B
0x0A1
Bits
7-6
OSD Character Translucent Level
Name
2008-05-05
R/W
Description
Reserved
77
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
5-3
TP_LEVEL_TWO
[2:0]
2-0
TP_LEVEL_ONE
[2:0]
When the attribute BG_Index is set to ”0001”, these 3-bits set the
translucent level of the character background color. Translucent level
refers to the percentage of color composition that is OSD.
“111” = 0%
“110” = 12.25%
“101” = 25%
“100” = 37.5%
“011” = 50%
“010” = 62.5%
“001” = 75%
“000” = 87.5%
When the attribute BG_Index is set to “0000” ~ “1111” except “0001”,
these 3-bits set the translucent level of the character background color.
Translucent level refers to the percentage of color composition that is
OSD.
“111” = 0%
“110” = 12.25%
“101” = 25%
“100” = 37.5%
“011” = 50%
“010” = 62.5%
“001” = 75%
“000” = 87.5%
Default: 0000 0000B
OSD Spacing Control
0x0A2
Bits
7
Name
V_FS_SEL
6
H_FS_SEL
5-3
VSPACE
[2:0]
2-0
HSPACE
[2:0]
OSD Space
R/W
Description
Vertical Font size selection
0: 18 font size for Vertical
1: 16 font size for Vertical
Horizontal Font size selection
0: 12 font size selected for Horizontal
1: 10 font size selected for Horizontal
OSD vertical space. These 3 bits define the vertical scan pixel of background
color added to above and below of each character.
Range: 0~7
OSD horizontal space. These 3 bits define the horizontal scan pixel of
background color added to left and right of each character.
Range: 0~7
Default: 0000 0000B
0x0A3
OSD Window/Font Gradient Control – 1
Bits
7
Name
GRD_B_POL
6
GRD_G_POL
5
GRD_R_POL
4
GRD_DIRECT
3
GRD_B_EN
2008-05-05
R/W
Description
Windrow/Font gradient Blue polarity
0: Increase
1: Decrease
Windrow/Font gradient Green polarity
0: Increase
1: Decrease
Windrow/Font gradient Red polarity
0: Increase
1: Decrease
Windrow gradient direction
0: Horizontal direction
1: Vertical direction
Windrow gradient Blue
0: Disable
1: Enable
78
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
2
GRD_G_EN
Windrow gradient Green
0: Disable
1: Enable
1
GRD_R_EN
Windrow gradient Red
0: Disable
1: Enable
0
WIN_GRD_EN Windrow gradient , the palette index define at 0x0AB
0: Background gradient enable
1: Foreground gradient enable
Default: 0000 0000B
0x0A4
OSD Window Gradient Control -2
R/W
Bits
7-4
Name
Description
WIN_GRD_STEP Window gradient step , define decrease or increase level each step
3-0
WIN_GRD_PIX
Window gradient pixel , define how many pixel decrease or increase level
each step
Default: 0000 0000B
OSD Window Control
0x0A5
OSD Window Select
Bits
7
Name
WIN8_EN
6
WIN7_EN
5
WIN6_EN
4
WIN5_EN
3
2-0
WIN_SEL
[2:0]
R/W
Description
Enable Window 8
0: Disable
1: Enable
Enable Window 7
0: Disable
1: Enable
Enable Window 6
0: Disable
1: Enable
Enable Window 5
0: Disable
1: Enable
Reserved
This register is used to select which window is to be accessed or modified. It
is programmed prior to accessing the registers Reg 0x0A6h ~ 0x0Afh
“000” = Window1
“001” = Window2
“010” = Window3
“011” = Window4
“100” = Window5
“101” = Window6
“110” = Window7
“111” = Window8
Default: 0000 0000B
0x0A6
Bits
7-6
5-0
OSD Window Horizontal Start
Name
WIN_HS
[5:0]
R/W
Description
Reserved
Horizontal starting position relative to the OSD for the selected window. The
unit is in font.
Range: 0~63
Default: 0000 0000B
2008-05-05
79
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x0A7
Bits
7-6
5-0
OSD Window Horizontal End
Name
WIN_HE
[5:0]
R/W
Description
Reserved
Horizontal ending position relative to the OSD for the selected window.
unit is in font.
The OSD Window Horizontal Width = (WIN_HE+1) – WIN_HS
Range: 0~63
The
Default: 0000 0000B
0x0A8
Bits
4-0
OSD Window Vertical Start
Name
WIN_VS
[4:0]
R/W
Description
Vertical starting position relative to the OSD for the selected window. The unit
is in font.
Range: 0~31
Default: 0000 0000B
0x0A9
Bits
7-5
4-0
OSD Window Vertical End
Name
WIN_VE
[4:0]
R/W
Description
Reserved
Vertical ending position relative to the OSD for the selected window. The unit
is in font.
The OSD Window 1 Vertical Height = (WIN1_VE+1) – WIN1_VS
Range: 0~31
Default: 0000 0000B
0x0AA
Bits
7
6-5
4
3-2
1
OSD Window Attribute
R/W
Name
WIN_BLEN
Description
Window bevel enable
Bevel size is specified in 0x0AD[2:0] : WIN_BL_WIDTH
WIN_BL_TYPE Window bevel type
00:Type1,Left/Bottom color define at 0x0AF,Right/Top color define at 0x0AC
or 0x0AE
01:Type2,Left/Top color define at 0x0AF,Right/Bottom color define at 0x0AC
or 0x0AE
10:Type3,Top/Bottom color define at 0x0AF,Left/Right color define at 0x0AC
or 0x0AE
11:Reserved
WIN_MIX
Window translucent enable for the selected window
0 – Normal
1 – Translucent ((1- TP_LEVEL_ONE) * Display + (TP_LEVEL_ONE) *
OSD_BG)
WIN_SDSZ
Shadow Size for the selected window when window shadow enable
[1:0]
00: 2 pixels in width and 2 lines in height.
01: 4 pixels in width and 4 lines in height.
10: 6 pixels in width and 6 lines in height.
11: 8 pixels in width and 8 lines in height.
WIN_SDEN
Window Shadow Enable for the selected window
Shadow size is specified in bits 3:2.
1= Shows a shadow for Window.
0= No shadow
2008-05-05
80
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0
WIN_FADE
Window gradient fade in/out
0: Disable
1: Enable
Default: 0000 0000B
0x0AB
OSD Window Color
R/W
Bits
7-0
Name
WIN_CL
[7:0]
Default: 0000 0000B
Description
Color index for the selected OSD Window. This color will cover the character
background color when Window is enabled.
0x0AC
OSD Gradient Font Color
R/W
Bits
7-0
Name
Description
GRAD_COLOR Color index for foreground gradient color
[7:0]
Default: 0000 0000B
0x0AB
0x0AC
0x0AE
0x0AF
Gradient Disable
Window
Color
X
Bevel top/right side ,
shadow color
Bevel bottom/left
side color
Background Gradient
Window
Color
X
Bevel top/right side ,
shadow color
Bevel bottom/left
side color
Foreground Gradient
Window
Color
Font Color
Bevel top/right side ,
shadow color
Bevel bottom/left
side color
0x0AD
OSD Window Bevel Width
R/W
Bits Name
Description
7-3 WIN_FADE_SPEED Window gradient fade in/out speed , based on VS count
2-0 WIN_BL_WIDTH
Specifies the width of the window bevel units.
[2:0]
Range: 1~8 , units : pixel
Default: 0000 0000B
0x0AE
Bits
7-0
Name
WIN_BL_RCL
[7:0]
Default: 0000 0000B
0x0AF
Bits
7-0
Name
WIN_BL_LCL
[7:0]
Default: 0000 0000B
OSD Window Bevel Right / Shadow Color
Description
Color index for all eight window’s top/right side bevel and shadow
OSD Window Bevel Left Color
R/W
Description
Color index for all eight window’s bottom/left side bevel
OSD Border And Shadow Control
0x0B0
OSD Shadow Control Row 7 – 0
2008-05-05
R/W
81
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits
7-0
Name
OSD_SCR
[7:0]
Description
Character Row Shadow Enable for 7-0. Each bit controls each row
correspondingly. Used only in one bit per pixel font.
1= Enable shadow for a row.
Default: 0000 0000B
0x0B1
Bits
7-0
OSD Shadow Control Row 15 – 8
Name
OSD_SCR
[15:8]
R/W
Description
Character Row Shadow Enable for 15-8. Each bit controls each row
correspondingly. Used only in one bit per pixel font.
1= Enable shadow for a row.
Default: 0000 0000B
0x0B2
Bits
7-0
OSD Shadow Control Row 23 – 16
Name
OSD_SCR
[23:16]
R/W
Description
Character Row Shadow Enable for 23-16. Each bit controls each row
correspondingly. Used only in one bit per pixel font.
1= Enable shadow for a row.
Default: 0000 0000B
0x0B3
Bits
7-0
OSD Shadow Control Row 31 – 24
Name
OSD_SCR
[31:24]
R/W
Description
Character Row Shadow Enable for 31-24. Each bit controls each row
correspondingly. Used only in one bit per pixel font.
1= Enable shadow for a row.
Default: 0000 0000B
0x0B4
Bits
7-0
OSD Border Control Row 7 – 0
Name
OSD_BCR
[7:0]
R/W
Description
Character Row Border Enable for 7-0. Each bit controls each row
correspondingly. Used only in one bit per pixel font.
1= Enable border for a row.
Default: 0000 0000B
0x0B5
Bits
7-0
OSD Border Control Row 15-8
Name
OSD_BCR
[15:8]
R/W
Description
Character Row Border Enable for 15-8. Each bit controls each row
correspondingly. Used only in one bit per pixel font.
1= Enable border for a row.
Default: 0000 0000B
0x0B6
Bits
7-0
OSD Border Control Row 23-16
Name
OSD_BCR
[23:16]
R/W
Description
Character Row Border Enable for 23-16. Each bit controls each row
correspondingly. Used only in one bit per pixel font.
1= Enable border for a row.
Default: 0000 0000B
0x0B7
Bits
7-0
OSD Border Control Row 31-24
Name
OSD_BCR
2008-05-05
R/W
Description
Character Row Border Enable for 31-24. Each bit controls each row
82
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
[31:24]
correspondingly. Used only in one bit per pixel font.
1= Enable border for a row.
Default: 0000 0000B
0x0B8
OSD Border & Shadow Color Row 1 – 0
Bits
7-4
Name
OSD_BSCR1
[3:0]
3-0
OSD_BSCR0
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 1. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 0. Used only in one bit per
pixel font.
0x0B9
OSD Border & Shadow Color Row 3 – 2
Bits
7-4
Name
OSD_BSCR3
[3:0]
3-0
OSD_BSCR2
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 3. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 2. Used only in one bit per
pixel font.
0x0BA
OSD Border & Shadow Color Row 5 – 4
Bits
7-4
Name
OSD_BSCR5
[3:0]
3-0
OSD_BSCR4
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 5. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 4. Used only in one bit per
pixel font.
0x0BB
OSD Border & Shadow Color Row 7- 6
Bits
7-4
Name
OSD_BSCR7
[3:0]
3-0
OSD_BSCR6
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 7. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 6. Used only in one bit per
pixel font.
0x0BC
OSD Border & Shadow Color Row 9 – 8
Bits
7-4
Name
OSD_BSCR9
[3:0]
3-0
OSD_BSCR8
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 9. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 8. Used only in one bit per
pixel font.
0x0BD
OSD Border & Shadow Color Row 11 – 10
Bits
7-4
Description
Character Border/Shadow Color Index For Row 11. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 10. Used only in one bit per
pixel font.
Name
OSD_BSCR11
[3:0]
3-0
OSD_BSCR10
[3:0]
Default: 0000 0000B
2008-05-05
83
R/W
R/W
R/W
R/W
R/W
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x0BE
OSD Border & Shadow Color Row 13 – 12
Bits
7-4
Name
OSD_BSCR13
[3:0]
3-0
OSD_BSCR12
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 13. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 12. Used only in one bit per
pixel font.
0x0BF
OSD Border & Shadow Color Row 15 – 14
Bits
7-4
Name
OSD_BSCR15
[3:0]
3-0
OSD_BSCR14
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 15. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 14. Used only in one bit per
pixel font.
0x0C0
OSD Border & Shadow Color Row 17 – 16
Bits
7-4
Name
OSD_BSCR17
[3:0]
3-0
OSD_BSCR16
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 17. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 16. Used only in one bit per
pixel font.
0x0C1
OSD Border & Shadow Color Row 19 – 18
Bits
7-4
Name
OSD_BSCR19
[3:0]
3-0
OSD_BSCR18
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 19. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 18. Used only in one bit per
pixel font.
0x0C2
OSD Border & Shadow Color Row 21 – 20
Bits
7-4
Name
OSD_BSCR21
[3:0]
3-0
OSD_BSCR20
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 21. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 20. Used only in one bit per
pixel font.
0x0C3
OSD Border & Shadow Color Row 23- 22
Bits
7-4
Name
OSD_BSCR23
[3:0]
3-0
OSD_BSCR22
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 23. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 22. Used only in one bit per
pixel font.
0x0C4
OSD Border & Shadow Color Row 25 – 24
Bits
Name
2008-05-05
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
84
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
7-4
OSD_BSCR25
[3:0]
3-0
OSD_BSCR24
[3:0]
Default: 0000 0000B
Character Border/Shadow Color Index For Row 25. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 24. Used only in one bit per
pixel font.
0x0C5
OSD Border & Shadow Color Row 27 – 26
Bits
7-4
Name
OSD_BSCR27
[3:0]
3-0
OSD_BSCR26
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 27. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 26. Used only in one bit per
pixel font.
0x0C6
OSD Border & Shadow Color Row 29 – 28
Bits
7-4
Name
OSD_BSCR29
[3:0]
3-0
OSD_BSCR28
[3:0]
Default: 0000 0000B
Description
Character Border/Shadow Color Index For Row 29. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 28. Used only in one bit per
pixel font.
0x0C7
OSD Border & Shadow Color Row 31 – 30
Bits
7-4
Description
Character Border/Shadow Color Index For Row 31. Used only in one bit per
pixel font.
Character Border/Shadow Color Index For Row 30. Used only in one bit per
pixel font.
Name
OSD_BSCR31
[3:0]
3-0
OSD_BSCR30
[3:0]
Default: 0000 0000B
OSD Splitting Control
0x0C8
OSD Horizontal Splitting Control
Bits
7
Name
H_SPL_EN
6-0
SPL_HP
[6:0]
R/W
R/W
R/W
R/W
Description
Horizontal Splitting Enable
0: Disable
1: Enable
Splitting horizontal begin position relative to the OSD frame for the selected
window. The unit is in 1 horizontal font size.
Range: 0~127
Default: 0000 0000B
0x0C9
OSD Horizontal Splitting width Control
Bits
7-0
Name
SPL_HW
[7:0]
Default: 0000 0000B
Description
Splitting horizontal width relative to the OSD frame. The unit is in 8 pixels.
Range: 0~255
0x0CA
OSD Vertical Splitting Control
Bits
7
Name
V_SPL_EN
2008-05-05
R/W
R/W
Description
Vertical Splitting Enable
0: Disable
85
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6
5-0
SPL_VP
[5:0]
1: Enable
Reserved
Splitting vertical begin position relative to the OSD frame. The unit is in 1
vertical font size.
Range: 0~64
Default: 0000 0000B
0x0CB
OSD Vertical Splitting Height Control
Bits
7-0
Description
Splitting vertical height relative to the OSD frame. The unit is in 8 lines.
Range: 0~255
Name
SPL_VH
[7:0]
Default: 0000 0000B
OSD Attribute Control and OSD Fast Clear Control
0x0CC
OSD Attribute LSB
Bits
7-0
Name
OSD_ATTR
[7:0]
R/W
R/W
Description
OSD Attribute LSB. The register OSD_ATTR [15:0] is use for fast clear and
update code from host and attribute from Register. This value is appended
with the character font code. When update OSD SRAM code from host and
“attribute from Reg 0x0CC ~ 0x0CD is selected in Reg 0x0E0 [7:4]. If fast
clear is enable, the hardware will fill the entire SRAM with the values in Reg
0x0CE (Code) and Reg 0x0CC ~ 0x0CD (Attribute).
Default: 0000 0000B
0x0CD
Bits
7-0
OSD Attribute MSB
Name
OSD_ATTR
[15:8]
R/W
Description
OSD attribute MSB. The register OSD_ATTR [15:0] is use for fast clear and
update code from host and attribute from Register. This value is appended
with the character font code. When update OSD SRAM code from host and
attribute from Reg 0x0CC ~ 0x0CD is selected in Reg 0x0E0 [7:4]. If fast clear
is enable, the hardware will fill the entire SRAM with the values in Reg 0x0CE
(Code) and Reg 0x0CC ~ 0x0CD (Attribute).
Default: 0000 0000B
0x0CE
OSD SRAM Code Value For Fast Clear
Bits
7-0
Name
CODE_FC
[7:0]
Default: 0000 0000B
Description
SRAM code for fast clear.
0x0CF
Fast Clear and Fade Mode Control
Bits
7-6
Name
FADE_MODE
5
4
BG_MIX_EN
FG_MIX_EN
2008-05-05
R/W
R/W
Description
Fade-in/Fade-out mode select
00:Left-Top corner
01:Right-Top corner
10:Left-Bottom corner
11:Right-Bottom corner
Background translucent enables.
Foreground translucent enables.
86
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
3
2
1
Reserved
FONT_MIX_EN Border/Shadow translucent enable.
FC_MASK
Fast Clear area mask
0: SRAM on OSD frame
1: SRAM on 0x0000 to One bit Font Address
0
FC_EN (W)/
Fast Clear Enable, When enable this bit, the hardware will fill the entire SRAM
FC_RDY I
with the values in Reg 0x0CE (Code) and Reg 0x0CC ~ 0x0CD (Attribute).
1: Enable the fast clear. If fast clear is finished, this bit FC_RDY will be clear to
‘0’.
0: No Effect
Default: 0000 0000B
Translucent
BG =
“001”
Character
★
Win Color
Bit 5 = 1
★
★
★
Border/Shadow
0x0A1[2:0]
0x0A1[5:3]
0x0AA[4]
TP_LEVEL
TP_LEVEL
WIN_MIX
★
★
★
Bit 5 = 1
★ except
“0000”
Win Color
Border/Shadow
Bit 4 = 1
★
Character
Background
0x0CF
Bit 4 = 1
★
Character
Character
Background
BG = “000” ~
“1111” except
“0001”
★
★
★
★
★
★
Bit 2 = 1
★
Bit 2 = 1
★
8.13. Source Hsync Digital PLL Control
0x0D0
HS DDS PLL Control
Bits Name
7
6
VER_DOUB_BYPASS
Description
Reserved
Vertical double buffer bypass
0: Normal ( DBL_EN define PLL load at VS blanking or disable
PLL data load )
1: Bypass ( realtime PLL update )
Double buffer load data at VSYNC Blanking
0: Disable (VER_DOUB_BYPASS define realtime update or disable
PLL data load )
1: Enable
Reserved
5
DBL_EN
4-1
2008-05-05
87
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0
DDS_EN
DDS enable
0: Disable
1: Ensable
Default: 0000 0000B
0x0D1
HS Frequency Control
Bits
6-4
3
Description
Reserved
HS DDS Divide control
0: Enable
1: Disable
Reserved
HS DDS output frequency range control
00: 100~200MHz
01: 50~100MHz
10: 25~50MHz
11: 12.5~25MHz
2
1-0
Name
HSDDS_DIV_CTRL
HPLL_FREQ_RANGE
[1:0]
R/W
Default:0001 0000B
0x0D2
Bits Name
7-0 HSDDS_RATIO
[7:0]
Default: 0000 0000B
0x0D3
Bits Name
7-0 HSDDS_RATIO
[15:8]
Default: 0000 0000B
0x0D4
Bits Name
5-0 HSDDS_RATIO
[21:16]
Default: 0001 0000B
HS PLL Frequency Control Ratio – lo
Description
HS PLL frequency control ration ( for manual mode )
HS PLL Frequency Control Ratio – mi
HS PLL Frequency Control Ratio – hi
Bits Name
7-4
3
HS_INV
Description
Reserved
HSYNC Invert
0: Normal
1: Inverted
HPLL manual mode
0: Auto
1: Manual
Reserved
HS PLL DDS enable
0: Disable
1: Enable
HPLL_EN
R/W
Description
HS PLL frequency control ration ( for manual mode )
HS PLL phase lock control
1
0
R/W
Description
HS PLL frequency control ration ( for manual mode )
0x0D5
2
R/W
R/W
Default: 0000 0011B
2008-05-05
88
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x0D6
Bits
7
6-5
HS PLL control
Name
HPLL_LOCK_EN
HPLL_PLOOP_FIT
[1:0]
4-0
Default: 0011 1111B
0x0D7
Bits
7-0
Description
HS PLL phase lock enable
HS PLL phase lock error correction ratio
Reserved
HS PLL divider – lo
Name
HSDDS_DIVIDER
[7:0]
R/W
R/W
Description
Clock divides value in the feedback loop of the HS PLL. The HS PLL
reference is the input Hsync signal.
CR:0D1[3] must be set “1”
Default: 0000 0000B
0x0D8
Bits
3-0
HS PLL divider – hi
Name
HSDDS_ DIVIDER
[11:8]
R/W
Description
The low byte [7:0] of HS PLL divider value. The register is
double-buffered.
Divider = HSDDS_ DIVIDER <11:0> + 1
fHPPL = Divider * fHS
Default: 0000 1000B
0x0D9
Bits
7-6
HS PLL phase control 1
Name
CLK_DLY_SEL
5-0
HS_PHASE_STEP
[5:0]
Default: 1000 0000B
0x0DA
0x0DB
Bits
7-5
Description
Select clock channel with clock delay adjusting.
00 = R
01 = G
10 = B
11 = Reserved
HS PLL 64 step phase adjust
HS PLL Phase control 2
Bits
Name
7-4
3-0
ADC_CK_DELAY[3:0]
Default: 0000 0000B
2008-05-05
R/W
Description
Reserved
To ADC Clock delay control
HS PLL Line count Select
Name
R/W
R/W
Description
Reserved
89
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
4-0
HS_LINE_CNT_SEL[ Horizontal Sync Line Count Select ( count with 12Mhz )
4:0]
00000: 20 Line
00001: 21 Line
00010: 22 Line
.
.
11110: 230 Line
11111: 231 Line
HS = 12M/( HS_CNT_RESULT[21:0] / HS_LINE_CNT_SEL[4:0] )
Default: 0000 0100B
0x0DC
Bits
7-2
1
Name
CAP_CKO_INV
0
Default: 0000 0000B
HS_DDS DPLL Output Control
Description
Reserved
Capture clock output polarity invert
0: Normal
1: Inverted
Reserved
0x0DD
Bits
7-0
Name
HS_CNT_RESULT
[7:0]
Default: XXXX XXXXB
HS HPLL Frequency Read back– lo
Name
HS_CNT_RESULT
[15:8]
Default: XXXX XXXXB
HS HPLL Frequency Read back – mi
Name
HS_CNT_RESULT
[21:16]
Default: XXXX XXXXB
R
Description
HS DPLL Frequency read back [15:8]
0x0DF
Bits
5-0
R
Description
HS DPLL Frequency read back [7:0]
HS = 12M/( HS_CNT_RESULT[21:0] / HS_LINE_CNT_SEL[4:0] )
0x0DE
Bits
7-0
R/W
HS HPLL Frequency Read back – hi
R
Description
HS DPLL Frequency read back [21:16]
8.14. Index Port Access Control
0x0E0
Index Access Port
Bits Name
7-4 TBL_SEL
INDEX_ADDR [7:0]
INDEX_ADDR [7:0]
INDEX_ADDR [7:0]
INDEX_ADDR [7:0]
Description
Table Select
0000: Red Gamma Table (Read/Write) (10 bits/word)
0001: Green Gamma Table (Read/Write) (10 bits/word)
0010: Blue Gamma Table (Read/Write) (10 bits/word)
0011: R/G/B Gamma Tables modified simultaneously (Write only) (10
bits/word)
0100: OSD SRAM code only (Read/Write) (8 bits/word)
0101: OSD SRAM attribute MSB (Read/Write) (8 bits/word)
0110: OSD SRAM attribute LSB (Read/Write) (8 bits/word)
INDEX_ADDR [11:0]
INDEX_ADDR [11:0]
INDEX_ADDR [11:0]
2008-05-05
90
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
INDEX_ADDR [11:0]
INDEX_ADDR [11:0]
INDEX_ADDR [11:0]
0111: OSD SRAM attribute (Read/Write) (16 bits/word)
1000: OSD SRAM code and attribute (Read/Write) (24 bits/word)
1001: OSD SRAM code from host and attribute from Reg 0x0CC ~
0x0CD (Read/Write) (8 bits/word)
INDEX_ADDR [9:0]
1010: OSD Programmable 1 Bit Color Font (Read/Write) (24 bits/word)
1011: OSD Programmable 2 Bit Color Font (Read/Write) (24 bits/word)
INDEX_ADDR [7:0]
1100: OSD Programmable 4 Bit Color Font (Read/Write) (24 bits/word)
INDEX_ADDR [7:0]
1101: OSD Palette (Read/Write) (16 bits/word)
INDEX_ADDR [7:0]
1110: HDCP Data(Read/Write) (8 bits/word)
INDEX_ADDR [7:0]
1111: OD SDRAM index port access
INDEX_ADDR [7:0]
3
PORT_RW
Port Read/Write
0: Write
1: Read
2
DIRECT_WR_GAMMA Gamma write directly
0: Write gamma table must set gamma disable
1: Write gamma table directly
1-0
Reserved
Default: 0000 0000B
0x0E1
Index Address Port – Low Byte
Bits
7-0
Name
INDEX_ADDR
[7:0]
Default: 0000 0000B
Description
Table Address – low bits
0x0E2
Index Address Port – High Byte
Bits
7-0
Name
INDEX_ADDR
[15:8]
Default: 0000 0000B
Description
Table Address – upper bits
0x0E3
Index Data Port
Bits
7-0
Description
Data port for the SRAM, Palette, and Programmable Font.
Name
PORT_DATA
[7:0]
Default: 0000 0000B
R/W
R/W
R/W
Note: 1. If The Index Port’s access is over 8 bit data length, the host interface will transfer or receive
data from LSB to MSB.
0x0E4 ~ 0x0E5: Reserved
8.15. Auto Gain/Gauge Access Window Control
0x0E6
Bits
7-0
Auto Gain/Gauge Window Odd field Vertical Begin –lo
Name
GI_CAP_VBEGO
[7:0]
R/W
Description
Vertical Capture Begin for Odd Field. GI_CAP_VBEGO indicates how
many lines to wait after referenced edge of VSYNC before starting image
capture. GI_CAP_VBEGO =3, means waiting 3 lines to begin capture.
This register is double-buffered.
Default: 0000 0000B
2008-05-05
91
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x0E7
Bits
7-3
2-0
Auto Gain/Gauge Window Odd field Vertical Begin –hi
Name
GI_CAP_VBEGO
[10:8]
Default: 0000 0000B
0x0E8
Bits
7-0
R/W
Description
Reserved
MSB of GI_CAP_VBEGO.
This register is double-buffered.
Auto Gain/Gauge Window Even field Vertical Begin –lo
Name
GI_CAP_VBEGE
[7:0]
R/W
Description
Vertical Capture Begin for Even Field. GI_CAP_VBEGE indicates how
many lines to wait after referenced edge of VSYNC before starting image
capture. GI_CAP_VBEGE =3, means waiting 3 lines to begin capture. This
register is double-buffered.
Default: 0000 0000B
0x0E9
Auto Gain/Gauge Window Even field Vertical Begin –hi
Bits
2-0
Name
GI_CAP_VBEGE
[10:8]
Default: 0000 0000B
Description
MSB of GI_CAP_VBEGE.
This register is double-buffered.
0x0EA
Auto Gain/Gauge Window Vertical Length –lo
Bits
7-0
Name
GI_CAP_VLEN
[7:0]
R/W
R/W
Description
Vertical Capture Length. GI_CAP_VLEN indicates how many lines to
capture. GI_CAP_VLEN = 3, means capturing 3 lines.
This register is double-buffered.
Default: 0000 0000B
0x0EB
Auto Gain/Gauge Window Vertical Length –hi
Bits
2-0
Name
GI_CAP_VLEN
[10:8]
Default: 0000 0000B
Description
MSB of GI_CAP_VLEN.
This register is double-buffered.
0x0EC
Auto Gain/Gauge Window Horizontal Begin –lo
Bits
7-0
Name
GI_CAP_HBEG
[7:0]
R/W
R/W
Description
Horizontal Capture Begin. GH_CAP_HBEG indicates how many pixels to
wait after referenced edge of HSYNC before starting image capture.
GH_CAP_HBEG =3, means waiting 3 pixels to begin capture.
This register is double-buffered.
Default: 0000 0000B
0x0ED
Bits
7-4
3-0
Auto Gain/Gauge Window Horizontal Begin –hi
Name
GI_CAP_HBEG
[11:8]
Default: 0000 0000B
0x0EE
2008-05-05
R/W
Description
Reserved
MSB of GI_CAP_HBEG.
This register is double-buffered.
Auto Gain/Gauge Window Horizontal Width –lo
92
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits
7-0
Name
GI_CAP_HWID
[7:0]
Description
Horizontal Capture Width. GI_CAP_HWID indicates how many pixels to
capture. GI_CAP_HWID = 3, means capturing 3 pixels.
This register is double-buffered.
Default: 0000 0000B
0x0EF
Bits
7-4
3-0
Auto Gain/Gauge Window Horizontal Width –hi
Name
GI_CAP_HWID
[11:8]
Default: 0000 0000B
R/W
Description
Reserved
MSB of GI_CAP_HWID.
This register is double-buffered.
8.16. Display Digital PLL Control
0x0F0
Bits
7-4
3
2
0
Display DDS PLL Control
Name
DDDS_RST
DDDS_EN
R/W
Description
DDS debug mode
Display DDS Reset
0: Normal
1: Reset
Reserved
Display DDS enable
0: Disable
1: Enable
Default: 0000 0000B
0x0F1
Bits
7-2
1-0
Display Frequency Control
Name
DISPLAY_PORT
R/W
Description
Reserved
Display data port control
00: Dual port
01: Single port
Default: 0001 0000B
0x0F2
Display PLL Frequency Control Ratio – lo
Bits
7-0
Name
DDDS_RATIO
[7:0]
Default: 0000 0000B
0x0F3
Name
DDDS_RATIO
[15:8]
Default: 0000 0000B
0x0F4
Bits
5-0
Description
Display DDS frequency control ratio
Display PLL Frequency Control Ratio – mi
Bits
7-0
2008-05-05
R/W
Description
Display DDS frequency control ratio
Display PLL Frequency Control Ratio – hi
Name
DDDS_RATIO
[21:16]
R/W
R/W
Description
Display DDS frequency control ratio
93
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Default: 0000 1010B
Fout = (Reference-Freq × DDDS_RATIO [21:0] ) / 217
Fref = 12.000 MHz
0x0F5
SSC Control
R/W
Bits
7-5
Name
Description
SSC_MOD_FREQ Display PLL spread spectrum modulation frequency control
“111” = REFCLK/4
“110” = REFCLK/8
“101” = REFCLK/16 “100” = REFCLK/32
“011” = REFCLK/64 “010” = REFCLK/128
“001” = REFCLK/256 “000” = REFCLK/512
4-1
SSC_RATIO
DDDS PLL spread spectrum ratio
“1000” = 1/4
“0111” = 1/8
“0110” = 1/16
“0101” = 1/32
“0100” = 1/64
“0011” = 1/128
“0010” = 1/256
“0001” = 1/512
“0000” = 1/1024
0
SSC_EN
DDS PLL spread spectrum enable
0: Disable
1: Enable
Default: 0000 1010B
0x0F6 : Reserved
0x0F7
Bits
7-1
0
Gauge Control 1
R/W
Description
Reserved
Gauge Detection Area mode select
GAUGE_MOD_SEL 0 = Detecting area is defined by capture registers
1 = Detecting area is defined by Auto Gain/Gauge window registers.
Default: 0000 0000B
0x0F8
Gauge Control 2
R/W
Bits
7
Name
Name
GAUGE_EN
6-5
4-3
GAUGE_SEL
2-0
GAUGE_STEP
[7:0]
Description
To Gauge the distribution of input data. When GAUGE_EN set “1”, the
function is enable, then if the gauge is finished this bit is cleared to “0”.
, repeat read gauge this bit must set “0” follow set “1”
0 = Disable
1 = Enable
Reserved
Gauge Source Select
00: Blue Channel
01: Green Channel
10: Red Channel
11: Reserved
The step of gauge Data
000: 1 Step
100: 16 Step
001: 2 Step
101: 32 Step
010: 4 Step
110: Reserved
011: 8 Step
111: Reserved
Default: 0000 0000B
2008-05-05
94
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x0F9
Bits
7-3
2-0
Gauge Result Read Back Area Select
Name
R/W
Description
Reserved
The Gauge Result Read back area select
0~7
GAUGE_AREA
Default: 0000 0000B
0x0FA
Gauge Offset
Bits
Name
7-0
GAUGE_OFFSET
Default: 0000 0000B
R/W
Description
The level of R/G/B Input when Gauge function is enable
0x0FB
Gauge Result – lo
Bits
7-0
Name
GAUGE_RESULT
[7:0]
Default: XXXX XXXXB
R
Description
The gauge result of input data in capture window
0x0FC
Gauge Result – mi
Bits
7-0
Name
GAUGE_RESULT
[15:8]
Default: XXXX XXXXB
R
Description
The gauge result of input data in capture window
0x0FD
Gauge Result – hi
Bits
7-0
Name
GAUGE_RESULT
[23:16]
Default: XXXX XXXXB
R
Description
The gauge result of input data in capture window
0x0FE : Reserved
8.17. Graphic Input Gauge
0x0FF
Bits
D7-2
D1-0
Accessing Register Page Enable
R/W
Name
Description
Reserved
REG_PAGE_SEL Register Page Enable
000: Enable register Page0.
001: Enable register Page1.
010: Enable register Page2.
011: Enable register Page3.
011: Enable register Page4.
Default: 0000 0000B
8.18. Product ID
0x100
Bits
7-4
3-0
Product ID
Name
CHIP_ID
2008-05-05
R
Description
Reserved
Chip ID = 1011
95
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
8.19. Power Control
0x101
Power Control
Bits
7
6
Name
PU_LVDSA
5
WARM_RST
4
3
GCLK_OFF
2
VCLK_OFF
1
0
DCLK_OFF
R/W
Description
Reserved
LVDS A Port power up control.
0 = Power down
1 = Power up
Chip Warm Reset. When WARM_RST=1, all state machines will be reset
other than the all of register’s value.
0 = Normal
1 = Reset
Reserved
Graphic Port Clock Off. When GCLK_OFF=1, Graphic Port clock is disabled
to conserve power
Video Port Clock Off. When VCLK_OFF=1, Video Port clock is disabled to
conserve power
Reserved
Display Clock Off. When DCLK_OFF=1, display clock is disabled to
conserve power
Default: 0000 1101B
0x102
Bits
7-6
5
Power Down Control 2
Name
PU_HPLL
4
3
PU_ADC
2
1
PU_TMDS
0
Default: 0000 0000B
R/W
Description
Reserved
HPLL Power up control.
0 = Power down
1 = Power up
Reserved
ADC Power up control.
0 = Power down
1 = Power up
Reserved
TMDS PD power up mode. When PU_TMDS = ‘0’, TMDS circuit will go
into power down state.
0 = Power down
1 = Power up
Reserved
0x103 ~ 0x105 : Reserved
8.20. Auto Tune
Graphic Auto Tune Control
0x106
Bits
7
Name
GI_AGPD_MOD
2008-05-05
Graphic Auto Tune Control
R/W
Description
Auto Gain and Phase Detection Area mode select , if this bit set “1” then
GI_AUTO_WIN don’t care .
0 = Normal/ Original ( depend on GI_AUTO_WIN )
1 = Detecting area is defined by Auto Gain/Gauge window registers.
( 0x0E6 ~ 0x0EF )
96
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6-5
GI_AUTO_WIN
4
GI_POS_DE
3-2
GI_GAINPHS_SEL
[1:0]
1
GI_GAINPHS_EN/
GI_GAINPHS_RDY
0
GI_POS_EN/
GI_POS_RDY
Auto Gain and Phase Detection Area select
00 : Whole frame
01 : Capture
1x : Mask window
Enable Position Detection depending on DE signal when TMDS is
enabled. If GI_POS_DE =1, 0xFF data is input to RGB channel for
position detection instead of data from graphic port when DE is ‘1’.
Graphic Input Gain and Phase Detection Type Select.
00 = Phase Tune 1 ( sum of difference calculate mode 1 )
01 = Phase Tune 2 ( sum of difference calculate mode 2 )
10 = Min RGB Gain ( read back CR:0x113 ~ 0x116 )
11 = Max RGB Gain ( read back CR:0x113 ~ 0x116 )
Graphic Input Gain and Phase Detection Enable. When
GI_GAINPHS_EN = 1, detection will start from next VSYNC. When
detection is finished, this bit is cleared to ‘0’.
0 = Disable
1 = Enable
Graphic Input Active Window Position Detection Enable. When
GI_POS_EN = 1, detection will start from next VSYNC. When detection
is finished, this bit is cleared to ‘0’.
0 = Disable.
1 = Enable
Default: 0001 1100B
Graphic Auto Position
0x107
Bits
7-0
Name
GI_POS_THR
[7:0]
Default: 0000 1111B
0x108
Name
GI_POS_VBEGO
[7:0]
Default: XXXX XXXXB
0x109
Name
GI_POS_VBEGO
[10:8]
Default: XXXX XXXXB
0x10A
Name
GI_POS_VBEGE
[7:0]
Default: XXXX XXXXB
0x10B
2008-05-05
R
Description
Active Window Vertical Begin for Even Field. GI_POS_VBEGE= 3 means
there are 3 blanking lines.
Auto Position Vertical Begin for Even Field –hi
Name
R
Description
MSB of GI_POS_VBEGO
Auto Position Vertical Begin for Even Field –lo
Bits
7-0
R
Description
Active Window Vertical Begin for Odd Field. GI_POS_VBEGO= 3 means
there are 3 blanking lines.
Auto Position Vertical Begin for Odd Field –hi
Bits
2-0
R/W
Description
Graphic data lager then GI_POS_THR will be considered to be non-black
pixel for position detecting.
Auto Position Vertical Begin for Odd Field –lo
Bits
7-0
Bits
Auto Position Black Threshold
R
Description
97
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
2-0
GI_POS_VBEGE
[10:8]
Default: XXXX XXXXB
MSB of GI_POS_VBEGE
0x10C
Auto Position Vertical Length –lo
Bits
3-0
Name
GI_POS_VLEN
[7:0]
Default: XXXX XXXXB
Description
The active window vertical length. GI_POS_VLEN = 3 means there are 3
active lines.
0x10D
Auto Position Vertical Length –hi
Bits
2-0
Name
GI_POS_VLEN
[10:8]
Default: XXXX XXXXB
Auto Position Horizontal Begin –lo
Name
GI_POS_HBEG
[7:0]
Default: XXXX XXXXB
Auto Position Horizontal Begin –hi
Name
GI_POS_HBEG
[11:8]
Default: XXXX XXXXB
Auto Position Horizontal Width –lo
Name
GI_POS_HWID
[7:0]
Default: XXXX XXXXB
Auto Position Horizontal Width –hi
Name
GI_POS_HWID
[11:8]
Default: XXXX XXXXB
Name
GI_PHS_MASK
[2:0]
R
Description
MSB of GI_POS_HWID
Graphic Auto Phase and Gain
0x112
Bits
7-3
2-0
R
Description
The active window horizontal width. GI_POS_HWID = 3 means there are 3
active pixels.
0x111
Bits
3-0
R
Description
MSB of GI_POS_HBEG
0x110
Bits
3-0
R
Description
The active window horizontal begin. GI_POS_HBEG = 3 means there are
3 blanking pixels.
0x10F
Bits
3-0
R
Description
MSB of GI_POS_VLEN
0x10E
Bits
7-0
R
Auto Phase Bit Mask
R/W
Description
Reserved
Decide how many LSB bits will be masked out, and then the difference
between adjacent pixels will be added to the sum of difference
accumulator.
Default: 0000 0100B
0x113
Bits
Auto Phase Sum of Difference –lo
Name
2008-05-05
R
Description
98
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
7-0
GI_PHS_SDIFF
[7:0]
R_MINMAX
[7:0]
Default: XXXX XXXXB
0x114
Auto Phase Sum of Difference – 2’nd
Bits
7-0
Name
GI_PHS_SDIFF
[15:8]
G_MINMAX
[7:0]
Default: XXXX XXXXB
0x115
Name
GI_PHS_SDIFF
[23:16]
B_MINMAX
[7:0]
Default: XXXX XXXXB
0x116
The minimum or maximum value of green channel data in one frame.
Name
GI_PHS_SDIFF
[31:24]
Default: XXXX XXXXB
Graphic Auto Clock
0x117
Bits
7-0
Name
GI_CLK_REF
[7:0]
Default: 0000 0000B
0x118
The minimum or maximum value of blue channel data in one frame.
GI_CLK_REF
[11:8]
Default: 0000 0000B
0x119
Auto Clock Reference Width –lo
Name
GI_CLK_COMP
[1:0]
5-0
GI_CLK_DIFF
2008-05-05
R/W
Description
Auto Clock Reference Width. This register provides the reference value
for calibrating the frequency of sampling clock in ADCPLL block.
R/W
Description
Reserved
MSB of AUTO_CLK_REF
Auto Clock Detecting Result
Bits
7-6
R
Description
MSB of GI_PHS_SDIFF
Auto Clock Reference Width –hi
Name
R
Description
Third byte of GI_PHS_SDIFF
Auto Phase Sum of Difference –hi
Bits
7-0
R
Description
Second byte of GI_PHS_SDIFF
Auto Phase Sum of Difference – 3’rd
Bits
7-0
Bits
7-4
3-0
Auto Phase Sum of Difference (LSB). GI_PHS_SDIFF specifies how the
phase locking quality in ADCPLL block.
The minimum or maximum value of red channel data in one frame.
R
Description
Auto Clock Comparing Relation. GI_CLK_COMP specifies the comparing
relation between GI_POS_HWID and GI_CLK_REF
00: GI_POS_HWID = GI_CLK_REF
01: GI_POS_HWID < GI_CLK_REF
1X: GI_POS_HWID > GI_CLK_REF
Difference of |GI_POS_HWID – GI_CLK_REF|
99
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
[5:0]
Default: XXXX XXXXB
The difference value is clamped to 0x3F if difference 0x3F
0x11A : Reserved
Video Auto Tune Control
0x11B
Bits
7-6
5
Name
VI_AUTO_MASK
4
3
VI_GAIN_AREA
2
VI_GAIN_SEL
1
VI_GAIN_EN/
VI_GAIN_RDY
0
VI_POS_EN/
VI_POS_RDY
Video Auto Tune Control
R/W
Description
Reserved
Gain Detection Area masking when VI_GAIN_AREA = “1”
0 = Detecting area is whole frame
1 = Detecting area is defined by mask window registers.
( define by CR: 0x047 ~ 0x04A )
Reserved
Gain Detection Area Define Enable.
0 = Detecting area is over one frame except the area defined by mask
window registers.
1 = Detecting area is defined by capture registers.
Video Input Gain Type Select
0 = Min Y Gain
1 = Max Y Gain
Video Input Y Min/Max Data Detection Enable. When VI_GAIN_EN = 1,
detection will start from next VSYNC.
When detection is finished, this bit is cleared to ‘0’.
0 = Disable
1 = Enable
Video Input Active Window Position Detection Enable. When VI_POS_EN
= 1, detection will start from next VSYNC. When detection is finished, this
bit is cleared to ‘0’.
0 = Disable
1 = Enable
Default: 0000 0000B
Video Auto Position
0x11C
Bits
7-0
Name
VI_POS_THR
[7:0]
Default: 0000 1111B
0x11D
Bits
7-0
Name
VI_VTOTAL
[7:0]
Default: XXXX XXXXB
0x11E
Bits
2-0
Name
VI_VTOTAL
[10:8]
Default: XXXX XXXXB
2008-05-05
Auto Position Black Threshold
R/W
Description
Video data lager than VI_POS_THR will be considered to be non-black
pixel for position detecting.
Auto Position Vertical Total –lo
R
Description
Vertical Period Total. VI_VTOTAL =99 means total 99 lines.
Auto Position Vertical Total –hi
R
Description
MSB of VI_VTOTAL.
100
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x11F
Auto Position Vertical Begin for Odd Field –lo
Bits
7-0
Name
VI_POS_VBEGO
[7:0]
Default: XXXX XXXXB
0x120
Name
VI_POS_VBEGO
[10:8]
Default: XXXX XXXXB
0x121
Name
VI_POS_VBEGE
[7:0]
Default: XXXX XXXXB
0x122
Name
VI_POS_VBEGE
[10:8]
Default: XXXX XXXXB
0x123
Name
VI_POS_VLEN
[7:0]
Default: XXXX XXXXB
0x124
VI_POS_VLEN
[10:8]
Default: XXXX XXXXB
0x125
Name
VI_HTOTAL
[7:0]
Default: XXXX XXXXB
0x126
Bits
7-4
3-0
VI_HTOTAL
[11:8]
Default: XXXX XXXXB
2008-05-05
R
Description
Horizontal Period Total. VI_HTOTAL=99, means total 99 pixels.
Auto Position Horizontal Total –hi
Name
R
Description
Reserved
MSB of VI_POS_VLEN.
Auto Position Horizontal Total –lo
Bits
7-0
R
Description
Active Window Vertical Length. VI_POS_VLEN =99 means 99 active
lines.
Auto Position Vertical Length –hi
Name
R
Description
MSB of VI_POS_VBEGE.
Auto Position Vertical Length –lo
Bits
7- 0
R
Description
Active Window Vertical Begin for Even Field. VI_POS_VBEGE =9
means 9 blanking lines.
Auto Position Vertical Begin for Even Field –hi
Bits
2-0
R
Description
MSB of VI_POS_VBEGO.
Auto Position Vertical Begin for Even Field –lo
Bits
7-0
Bits
7-3
2-0
Description
Active Window Vertical Begin for Odd Field. VI_POS_VBEGO =9 means
9 blanking lines.
Auto Position Vertical Begin for Odd Field –hi
Bits
2-0
R
R
Description
Reserved
MSB of VI_HTOTAL.
101
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x127
Auto Position Horizontal Begin –lo
Bits
7-0
Name
VI_POS_HBEG
[7:0]
Default: XXXX XXXXB
0x128
Bits
7-4
3-0
R
Description
Active Window Horizontal Begin. VI_POS_HBEG =3 means 3 blanking
pixels.
Auto Position Horizontal Begin –hi
Name
VI_POS_HBEG
[11:8]
Default: XXXX XXXXB
0x129
R
Description
Reserved
MSB of VI_POS_HBEG
Auto Position Horizontal Width –lo
Bits
7-0
Name
VI_POS_HWID
[7:0]
Default: XXXX XXXXB
0x12A
R
Description
Active Window Horizontal Width. VI_POS_HWID =99 means 99 active
pixels.
Auto Position Horizontal Width –hi
Bits
3-0
Name
VI_POS_HWID
[11:8]
Default: XXXX XXXXB
Video Auto Gain
0x12B
Bits
7-0
Name
Y_MINMAX
[7:0]
Default: XXXX XXXXB
R
Description
MSB of VI_POS_HWID
Video Min/Max Y Value
R
Description
The minimum or maximum value of Y channel data in one frame.
0x12C ~ 0x12F : Reserved
8.21. Bright Frame Display Registers
Bright Frame Control
Note–When both Bright Frames are enabled and if two windows are overlapped frame2 has higher
priority than frame 1.
0x130
Bright Frame Enable Control
R/W
Bits
7-5
4
3-2
1
Name
Description
Reserved
BRIGHT_REF_CTL Bright Frame Active reference
0: Front (Capture)
1: Post (Display)
Reserved
BRIGHT_FRM2_EN Enable Bright Frame 2
0: Disable
1: Enable
2008-05-05
102
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
BRIGHT_FRM1_EN Enable Bright Frame 1
0: Disable
1: Enable
Default: 0000 0000B
0
0x131
Bits
7-1
0
Bright Frame access index Select
R/W
Name
Description
Reserved
BRIGHT_FRM_SEL This register is used to select which frame is to be accessed or modified.
It is programmed prior to accessing the registers Reg 0x132 ~ 0x13B
[0]
“0” = Bright Frame 1
“1” = Bright Frame 2
Default: 0000 0000B
0x132
Bits
7-0
Bright Frame Horizontal Start – Low byte
Name
BRIGHT_FRM_HS
[7:0]
R/W
Description
Bright Frame horizontal start low byte [7:0]. Specifies the horizontal
starting position of the Bright Frame in pixel units. This register is
double-buffered.
Default: 0000 0000B
0x133
Bits
7-4
3-0
Bright Frame Horizontal Start – High Byte
Name
BRIGHT_FRM_HS
[11:8]
R/W
Description
Reserved
Bright Frame horizontal start high byte [11:8]. Specifies the horizontal
starting position of the Bright Frame in pixel units. This register is
double-buffered.
Default: 0000 0000B
0x134
Bright Frame Horizontal Width – Low byte
Bits
7-0
Name
BRIGHT_FRM_HW
[7:0]
Default: 0000 0000B
0x135
Bits
7-4
3-0
BRIGHT_FRM_HW
[11:8]
Default: 0000 0000B
0x136
Bits
7-0
Description
Bright Frame horizontal Width low byte [7:0]. Specifies the width of the
Bright Frame in pixel units. . This register is double-buffered.
Bright Frame Horizontal Width – High byte
Name
R/W
Description
Reserved
Bright Frame horizontal Width low byte [11:8]. Specifies the width of the
Bright Frame in pixel units. . This register is double-buffered.
Bright Frame Vertical Start – Low byte
Name
BRIGHT_FRM_VS
[7:0]
R/W
R/W
Description
Bright Frame vertical start low byte [7:0]. Specifies the vertical starting
position of the Bright Frame in pixel units. This register is
double-buffered.
Default: 0000 0000B
0x137
Bits
7-4
Bright Frame Vertical Start – High Byte
Name
2008-05-05
R/W
Description
Reserved
103
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
3-0
BRIGHT_FRM_VS
[10:8]
Bright Frame vertical start high byte [10:8]. Specifies the vertical starting
position of the Bright Frame in pixel units. This register is
double-buffered.
Default: 0000 0000B
0x138
Bright Frame Vertical Height – Low byte
Bits
7-0
Name
BRIGHT_FRM_VH
[7:0]
Default: 0000 0000B
0x139
Bits
7-4
2-0
Description
Bright Frame vertical Width low byte [7:0]. Specifies the width of the
Bright Frame in pixel units. . This register is double-buffered.
Bright Frame Vertical Height – High byte
Name
BRIGHT_FRM_VH
[10:8]
Default: 0000 0000B
R/W
R/W
Description
Reserved
Bright Frame vertical Width low byte [10:8]. Specifies the width of the
Bright Frame in pixel units. . This register is double-buffered.
0x13A~0x142 : Reserved
8.22. DVI Input Control 2
0x143
DVI Control
Bits Name
7
TMDS_PLL_PD
6-3
2
TMDS_PWN
1
TMDS_PWN
0
TMDS_PWN
Default: 0000 0000B
Description
TMDS PLL power down control
Reserved
TMDS R terminal power down
TMDS G terminal power down
TMDS B terminal power down
0x144
Bits
7-1
0
R/W
DVI Control
Description
Reserved
TMDS_IPDS_PD Power down control of three channel impedances (
pair , clock channel power down by 0x146.6
Default: 0000 0000B
R/W
Name
uality ct ) only for data
0x145 : Reserved
0x146
Bits
7
6
DVI Control
Name
5-0
Default: 1111 0011B
R/W
Description
Reserved
0: DVI clock channel power down
1: normal
Reserved
0x147~0x14F : Reserved
2008-05-05
104
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
8.23. Display Port Control
Display timing control
Single pixel or dual pixel output
Output signals drive current and slew rate control
Phase delay adjustment for accessing clock to external LCD
Dithering function supports 24-bit quality for 18-bit panel
Mute display control
Display Video Special mode Control
Display General Control
0x150
Display Control
Bits
7
Name
DP_BIT_SHF
6
DP_LOCK
5
DP_AUTO
4
3
DP_COLDEP
2
DP_BUSWID
1
DP_DE
0
DP_EN
R/W
Description
When display bus is 6-bit/color, this bit enable will shift the data RA[7:2],
GA[7:2], BA[7:2] to RA[5:0], GA[5:0], BA[5:0] and RB[7:2], GB[7:2], BB[7:2]
to RB[5:0], GB[5:0], BB[5:0]. When display bus is 8-bit/color, this bit enable
will rotate the data RA[7:0], GA[7:0], BA[7:0] and RB[7:0], GB[7:0], BB[7:0] to
right 2 bits
0 = Normal
1 = Shift / Rotate
Display lock event control. Under frame-sync display mode, this bit select
the way of display locking to input image. For manual lock mode, the lock
position is defined by DV_LOCK and DH_LOCK registers.
0 = Manual lock
1 = Auto lock
Display timing auto control. Under frame-sync display mode, this bit select
the way of display timing generation.
0 = Manual
1 = Auto
Reserved
Display Color Depth
0 = 8-bit/color
1 = 6-bit/color
Display Bus Width
0 = Double pixel 48-bit
1 = Single pixel 24-bit
Panel supports DE mode
0 = Panel supports Sync mode, display Hs/Vs signal is at normal state
1 = Panel supports DE mode, display Hs/Vs signal will be pulled low
Display Enable
0 = Disable
1 = Enable
Default: 0110 0000B
0x151
Bits Name
7-0
Default: 0000 0000B
0x152
2008-05-05
DV_LOCK
R/W
Description
Display sync manual mode V lock
DH_LOCK
R/W
105
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits Name
7-0
Default: 0000 0000B
0x153
DH_LOCK
Bits Name
7-0
Default: 0000 0000B
0x154
Bits
7-4
Description
Display sync manual mode H lock control low byte
R/W
Description
Display sync manual mode H lock control high byte
Display Mute and Color Control
Name
DP_PATT
[3:0]
R/W
Description
Select built-in display pattern
Pattern number = 0~15
If PATT_BK = Bank 0
0000 = Gamma Correction pattern
0001 = Dot Moiré
0010 = Vertical Line Moire (1B1W)
0011 = Vertical Line Moire (2B1W)
0100 = Vertical Line Moire (2B2W)
0101 = 256 V_Gray Bar
0110 = 256 H_Gray Bar
0111 = Horizontal Line Moire (1B1W)
1000 = Horizontal Line Moire (2B1W)
1001 = Horizontal Line Moire (2B2W)
1010 = Chat Pattern
1011 = White Pattern
11xx = Rectangular pattern, outline width is defined by xx bits.
00 = 1 pixel
01 = 3 pixels
10 = 5 pixels
11 = 7 pixels
3
PATT_BK
2
CBAR_EN
1-0
DP_MUTE
[1:0]
If PATT_BK = Bank 1
0000 = Black pattern
0001~1111 = Reserved
Built-in pattern bank Select
0 = Bank 0
1 = Bank 1
Paste a Cross Bar on the built-in display pattern and the Bar’s gray level is
controlled via CBAR_FG[7:0] register (0x15A)
0 = Disable
1 = Enable
Display Mute Mode Select
00 = Normal display, RGB channel output controlled via DP_RGB
01 = Mute input with output built-in display pattern, pattern color decided
by DP_RGB registers. (Display free-run)
10 = Mute input with output OSD and background color, background color
decided by DP_BG_R/G/B registers. (Display free-run)
11 = Pull low all display signals including data, clock and control lines
Default: 0000 0000B
2008-05-05
106
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x155 : Reserved
0x156
Display Drive and Polarity Control
Bits
7
Name
DDE_POL
6
DCLK_POL
5
DHS_POL
4
DVS_POL
3-0
Default: 1011 0010B
0x157
Bits
7
6-5
R/W
Description
Display DE
1 = Active High
0 = Active Low
Display Clock
0 = Normal
1 = Inverted
Display Hsync
1 = Active High
0 = Active Low
Display Vsync
1 = Active High
0 = Active Low
Reserved
Display Clock and Data Delay Control
R/W
Name
Description
Reserved
DCLK_SYNC_SEL Display clock synchronous mode select
00 = Display clock free-run
01 = Display clock is synchronized to input(default by TCON enable)
10 = Display clock free-run and DISP_DE synchronized to DISP_CLK
11 = Reserved
4-0
DCLK_DLY
Select panel interface CLOCK delay time. (0.5nS/step)
[4:0]
0~32 step
Default: 0010 0000B
0x158
Display Dithering Control
R/W
Bits
7-4
Name
Description
Dithering mode select
DITH_MODE
[3:0]
3
GAMMA_DITH_EN Gamma dithering enable. ( 10 to 8 ) ( 0x1EE[2] must set “0” )
0 = Disable
1 = Enable ( gamma table set 4.0 ) , 0x390.4 set “0” , gamma after OSD
2
DITH_8BIT/
Rounded 10 bit gamma data output to 8 bit for dithering
GAMMA_RANDOM 0 = Disable
1 = Enable 8 Bit dithering
If GAMMA_DITH_EN = “1” (0x158[3]), this bit is for gamma dithering
random mode control
1
DITH_TURBO
0 = Disable
1 = Enable , 0x1DA[5:4] must disable
0x158[7:4] set “0000” for check
0
DITH_EN
Dithering enable. When DITH_EN =0, the LSB bits of display data will be
truncated if display color depth is less than internal data resolution.
0 = Disable
1 = Enable
Default: 0000 0000B
2008-05-05
107
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x159
Display Channel Select
Bits
7
Name
INT_FAST_EN
6
5
MUTE_FR_EN
3
2-0
DP_RGB
[2:0]
R/W
Description
Mute mode with Free Run timing when graphic input sync fail ( when input
change HS/VS polarity , frequency )
0: Disable
1: Enable
Reserved
Mute mode with Free Run timing Enable, this display Horizontal sync
timing reference to Reg. 0x179~0x17A.( Vertical free run follow display
VTOTAL 0x15B,0x15C )
0: Disable
1: Enable
Reserved
Select RGB channel for display
000 = RGB normal display
001 = R channel only
010 = G channel only
011 = B channel only
100 = R & G channels
101 = R & B channels
110 = G & B channels
111 = RGB inverted display
Default: 0000 0000B
0x15A
Bits
7-0
Name
CBAR_FG
[7:0]
Default: 0000 0000B
2008-05-05
Cross Bar Gray Level
R/W
Description
Select the foreground gray level of Cross Bar for burn-in display pattern.
R=G=B= 0~255
108
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
DH_TOTAL
DH_ACT_BEG
DH_HS_WID
DH_ACT_WID
DV_BG_BEG
DV_TOTAL
Active Window
DV_ACT_BEG
Display Background Window
DV_ACT_LEN
DV_BG_BEG
DV_BG_LEN
DV_VS_WID
DH_BG_WID
DE
Display Timing Control
Figure 8.23-1 Display Timing
Display Sync Timing Control
0x15B
Bits
7-0
Name
DV_TOTAL
[7:0]
Default: 0000 0000B
0x15C
Bits
2-0
Name
DV_TOTAL
[10:8]
Default: 0000 0000B
0x15D
Bits
7-0
Name
DV_VS_WID
[7:0]
Default: 0000 0000B
0x15E
Bits
7-0
Name
DH_TOTAL
[7:0]
Default: 0000 0000B
0x15F
2008-05-05
Display Vertical Total –lo
R/W
Description
Display Vertical Total Lines.
DV_TOTAL = 3 means there are 4 total lines.
Display Vertical Total –hi
R/W
Description
MSB of DV_TOTAL
Display VSYNC Pulse Width
R/W
Description
Display VSYNC Pulse Width. DV_VS_WID =3, means pulse width is 3 lines
wide.
Display Horizontal Total –lo
R/W
Description
Display Horizontal Total Pixels.
DH_TOTAL = 3 means there are 4 total pixels.
Display Horizontal Total –hi
109
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits
7-4
3-0
Name
DH_TOTAL
[11:8]
Default: 0000 0000B
0x160
Description
Reserved
MSB of DH_TOTAL
Display HSYNC Pulse Width
Bits
7-0
Name
DH_HS_WID
[7:0]
Default: 0000 0000B
Description
Display HSYNC Pulse Width. DH_HS_WID =3, means pulse width is 3
pixels wide.
0x161
Bits
7-2
1
R/W
R/W
Name
Description
Reserved
Display Registers update enable on next DVS when DR_VDOUBLE_EN =
DR_VUPDATE_EN
“1”
0
DR_VDOUBLE_EN Display Registers update on next DVS enable, When this bit enable will
causes display registers update on next DVS. Otherwise, display registers
will direct update.
0 = Disable
1 = Enable
Default: 0000 0010B
Display Background Window Control
0x162
Display Background Window Vertical Begin –lo
Bits
7-0
Name
DV_BG_BEG
[7:0]
R/W
Description
Display Background Window Vertical Begin. DV_BG_BEG indicates how
many lines to wait after DVSYNC leading edge before starting image
display. DV_BG_BEG =3, means waiting 3 lines to begin display.
Default: 0000 0000B
0x163
Bits
7-3
2-0
Display Background Window Vertical Begin –hi
Name
DV_BG_BEG
[10:8]
Default: 0000 0000B
0x164
Name
DV_BG_LEN
[7:0]
Default: 0000 0000B
0x165
Bits
7-3
2-0
Description
Reserved
MSB of DV_BG_BEG
Display Background Window Vertical Length –lo
Bits
7-0
DV_BG_LEN
[10:8]
Default: 0000 0000B
2008-05-05
R/W
Description
Display Background Window Vertical Length. DV_BG_LEN indicates how
many lines to display. DV_BG_LEN =3, means displaying 3 lines.
Display Background Window Vertical Length –hi
Name
R/W
R/W
Description
Reserved
MSB of DV_BG_LEN
110
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x166
Bits
7-0
Display Background Window Horizontal Begin –lo
Name
DH_BG_BEG
[7:0]
R/W
Description
Display Background Window Horizontal Begin. DH_BG_BEG indicates how
many pixels to wait after DHSYNC leading edge before starting image
display. DH_BG_BEG =3, means waiting 3 pixels to begin display.
Default: 0000 0000B
0x167
Bits
7-4
3-0
Display Background Window Horizontal Begin –hi
Name
DH_BG_BEG
[11:8]
Default: 0000 0000B
R/W
Description
Reserved
MSB of DH_BG_BEG
0x168
Display Background Window Horizontal Width –lo
Bits
7-0
Name
DH_BG_WID
[7:0]
Default: 0000 0000B
Description
Display Background Window Horizontal Width. DV_BG_WID indicates how
many pixels to display. DV_BG_WID =3, means displaying 3 pixels.
0x169
Display Background Window Horizontal Width –hi
Bits
7-4
3-0
Name
DH_BG_WID
[11:8]
Default: 0000 0000B
R/W
R/W
Description
Reserved
MSB of DH_BG_WID
0x16A
R/W
Bits
7-5
4
Name
DP_PORT_SWAP
3
DP_BYTE_SWAPB
2
DP_BYTE_SWAPA
1
DP_BIT_SWAPB
0
DP_BIT_SWAPA
Description
Reserved
A /B Port Swap Control
0: Normal
1: A/B Port Swap
Display Bus Port B Byte Swap Control
0: Normal
1: B Port R/B Channel Byte Swap
Display Bus Port A Byte Swap Control
0: Normal
1: A Port R/B Channel Byte Swap
Display Bus Port B Bit Swap Control
0: Normal
1: B Port Bit Swap
Display Bus Port A Bit Swap Control
0: Normal
1: Port A Bit Swap (RGB bit7~bit0 in 8 bit Mode, bit5~bit0 in 6 bit Mode)
Default: 0000 0000B
Display Background Color Control
0x16B
Display Background Color – Red
Bits
Name
2008-05-05
R/W
Description
111
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
7-0
DP_BG_R
[7:0]
Default: 0000 0000B
0x16C
Display Background Window Red Color.
Display Background Color – Green
Bits
7-0
Name
DP_BG_G
[7:0]
Default: 0000 0000B
0x16D
Description
Display Background Window Green Color.
Display Background Color – Blue
Bits
7-0
Name
DP_BG_B
[7:0]
Default: 0000 0000B
6-3
2-1
0
Name
VD_EN
GD_FLD
[1:0]
GD_EN
R/W
Description
Display Background Window Blue Color.
Graphic Display Active Window Control
0x16E
Graphic Display Window Control
Bits
7
R/W
R/W
Description
Video Display Window Enable
0 = Disable
1 = Enable
Reserved
Select the field to display for interlaced graphic input
00 = Display both odd and even field mode
01 = Display only odd field mode
10 = Display only even field mode
11 = Spatial Interlace mode
Graphic Display Window Enable
0 = Disable
1 = Enable
Default: 0000 0110B
0x16F
Bits
7-0
Graphic Display Active Window Vertical Begin –lo
Name
GDV_ACT_BEG
[7:0]
R/W
Description
Graphic Display Active Window Vertical Begin. GDV_ACT_BEG indicates
how many lines to wait after DVSYNC leading edge before starting graphic
image display. GDV_BG_BEG =3, means waiting 3 lines to begin display.
Default: 0000 0000B
0x170
Bits
7-3
2-0
Graphic Display Active Window Vertical Begin –hi
Name
GDV_ACT_BEG
[10:8]
Default: 0000 0000B
0x171
Bits
7-0
Description
Reserved
MSB of GDV_ACT_BEG
Graphic Display Active Window Vertical Length –lo
Name
GDV_ACT_LEN
[7:0]
2008-05-05
R/W
R/W
Description
Graphic Display Active Window Vertical Length. GDV_ACT_LEN indicates
how many lines to display. GDV_ACT_LEN =3, means displaying 3 lines.
112
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Default: 0000 0000B
0x172
Bits
7-3
2-0
Graphic Display Active Window Vertical Length –hi
Name
GDV_ACT_LEN
[10:8]
Default: 0000 0000B
0x173
Bits
7-0
Description
Reseerved
MSB of GDV_ACT_LEN
Graphic Display Active Window Horizontal Begin –lo
Name
GDH_ACT_BEG
[7:0]
R/W
R/W
Description
Graphic Display Active Window Horizontal Begin. GDH_ACT_BEG indicates
how many pixels to wait after DHSYNC leading edge before starting graphic
image display. GDH_ACT_BEG =3, means waiting 3 pixels to begin display.
Default: 0000 0000B
0x174
Bits
7-4
3-0
Graphic Display Active Window Horizontal Begin –hi
Name
GDH_ACT_BEG
[11:8]
Default: 0000 0000B
0x175
Bits
7-0
Description
Reserved
MSB of GDH_ACT_BEG
Graphic Display Active Window Horizontal Width –lo
Name
GDH_ACT_WID
[7:0]
R/W
R/W
Description
Graphic Display Active Window Horizontal Width. GDH_ACT_WID
indicates how many pixels to display. GDH_ACT_WID =3, means
displaying 3pixels.
Default: 0000 0000B
0x176
Bits
7-4
3-0
Graphic Display Active Window Horizontal Width –hi
Name
GDH_ACT_WID
[11:8]
Default: 0000 0000B
Description
Reserved
MSB of GDH_ACT_WID
0x177
H Lock
Bits
7-0
Name
LOCK_RD_H
[7:0]
Default: XXXX XXXXB
Description
Lock H position read back low byte
0x178
V Lock
Bits
7-4
Description
Lock V position read back
Name
LOCK_RD_V
[3:0]
3-0
LOCK_RD_H
[11:8]
Default: XXXX XXXXB
2008-05-05
R/W
R
R
Lock H position read back high byte
113
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Free Run Htotal Control
0x179
Bits
7-0
Name
FRH_TOTAL
[7:0]
Free Run Horizontal Total –lo
R/W
Description
Free Run Horizontal Total Pixels. This register is used when MUTE_FR_EN
= “1” (Reg. 0x159[5]).
DH_TOTAL = 3 means there are 4 total pixels.
Default: 0000 0000B
0x17A
Bits
7-4
3-0
Free Run Horizontal Total –hi
Name
FRH_TOTAL
[11:8]
Default: 0000 0000B
R/W
Description
Reserved
MSB of DH_TOTAL
0x17B~0x181 : Reserved
0x182
Auto Control H-total Read Back
Bits
Name
7-0
Default: XXXX XXXXB
Description
Display auto mode H total read back
0x183
Auto Control H-total Read Back
Bits
Name
3-0
Default: XXXX XXXXB
Description
Display auto mode H total read back
0x184
Residual Display HSYNC Control
Bits
Name
7-0
Default: XXXX XXXXB
Description
Display manual mode residual HS count read back
0x185
Residual Display HSYNC Control
Bits
Name
7-0
Default: XXXX XXXXB
Description
Display manual mode residual HS count read back
0x186
Residual Display Mode Control
Bits
7-0
Name
R
R
R
R
R//W
Description
0x00 for normal display HS/VS
0x10 for average HS , last HS cycle is same as others
Default: 00000 0000B
0x187~0x18C : Reserved
0x18D
Residual Display Mode Control
Bits Name
5
Default: 0000 0000B
Description
Internal circuit option for display manual mode , default “0x00”
2008-05-05
114
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
FIFO Over/Under-flow Interrupt
0x18E
FIFO Interrupt Flag
Bits
Name
1
INT_FFOV
0
INT_FFUN
Default: XXXX XXXXB
Description
FIFO over-flow interrupt flag
FIFO under-flow interrupt flag
0x18E
FIFO Interrupt Flag Clear
Bits Name
1
CLR_FFOV
0
CLR_FFUN
Default: 0000 0000B
R
W
Description
Writing ‘1’ will clear INT_FFOV flag
Writing ‘1’ will clear INT_FFUN flag
0x18F
FIFO Interrupt Enable
Bits Name
7-2
1
INT_FFOV_EN
0
INT_FFUN_EN
Default: 0000 0000B
R/W
Description
Reserved
FIFO over-flow interrupt enable
FIFO under-flow interrupt enable
0x190 : Reserved
0x191
Bits
7
FIFO Control
R/W
Name
Description
Bypass the VI ( vertical interpolation ) data and power down the clock
BP_VI
For up scaling
6
Bypass the HI ( horizontal interpolation ) data and power down the clock
BP_HI
For up scaling
5
BP_SRGB
Bypass the SRGB data and power down the clock
4
Bypass the VC ( vertical compression ) data and power down the clock
BP_VC
For down scaling
3
Bypass the HC ( horizontal compression ) data and power down the clock
BP_HC
For down scaling
FIFO reference clock control auto select enable
2
GR_AUTO_CLK
0 = Disable
1 = Enable
FIFO reference clock control source select
1-0
GR_FIFO_CLK_SEL
00 = Graphic clock
[1:0]
01 = Video clock
Default: 0000 0100B
0x192 ~ 0x195 : Reserved
8.24. Sync Processor
H/V sync frequency counter & polarity detection
H/V sync frequency change detection
Composite/separate auto-switch
Interlaced/progressive input detection
Programmable free-run H/V frequency
Status change interrupt
2008-05-05
115
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Graphic Sync Processor Control
0x196
Bits
7
Name
DVI_SYNC_SEL
6
HPLL_HS_INV
5-4
GI_HS_SRC
[1:0]
3-2
GI_VCNT_BIT
[1:0]
1-0
GI_SYNC_TYPE
[1:0]
Graphic SYNC Processor Control 1
R/W
Description
Select the SYNC input source when DVI interface is enabled.
0 = From DVI DE signal
1 = From DVI HS/VS signal
Invert the HPLL output HS polarity
0 = Normal
1 = Invert
Select the HSYNC input source to sync processor and core logic.
00 = HPLL_HS -> sync processor and core logic
01 = RAW_HS -> sync processor and core logic
10 = RAW_HS -> sync processor and HPLL_HS -> core logic
11 = SOG_HS-> sync processor and core logic
Select the bit number of GI_VCNT.
00 = 11-bit. Overflow freq = 27.32Hz
01 = 12-bit. Overflow freq = 13.66Hz
1X = 13-bit. Overflow freq = 6.83Hz
Graphic sync type select.
00 = Separate SYNC
01 = Composite SYNC
1X = Reserved
Default: 0001 0110B
0x197
Graphic SYNC Processor Control 2
Bits
7-6
5
Name
GI_VRUN_EN
4
GI_HRUN_EN
3
GI_VSO_POL
2
GI_HSO_POL
1
INT_VSO_EN
0
INT_HSO_EN
R/W
Description
Reserved
VSYNC output free run enable
0 = Disable
1 = Enable
HSYNC output free run enable
0 = Disable
1 = Enable
VSYNC output polarity control
0 = Active low
1 = Active high
HSYNC output polarity control
0 = Active low
1 = Active high
Internal VS output pin-113 enable
0 = Enable
1 = Disable
Internal HS output pin-114 enable
0 = Enable
1 = Disable
Default: 1000 1111B
Interlace Detector Control
0x198
Graphic Field Decision Window
Bits
Name
2008-05-05
R/W
Description
116
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
7-4
3-0
GI_FLD_WINEDN
[3:0]
GI_FLD_WINBEG
[3:0]
Define the end position of graphic field decision window.
The G_HS period is divided into 16 segments; a field decision window is
defined by GI_FLD_WINBEG and GI_FLD_WINEND. GI_FLD_WINBEG
defines the window begin position, and GI_FLD_WINEND defines the end
position. If the G_VS reference edge locates inside the window, it means
ODD field.
Default: 0100 1100B
0x199
Graphic SYNC Processor Control 3
Bits
7-2
1
Name
GI_FLD_EDGE
0
GI_FLD_INV
R/W
Description
Reserved
Select the reference edge of VSYNC in Graphic Field Detector
0 = Leading edge
1 = Trailing edge
Invert the polarity of Graphic Field Detector output signal from sync
processor
0 = Normal
1 = Invert
Default: 0000 0000B
Sync Status
0x19A
Bits
7
Name
GI_VCNT_OV
6
GI_HCNT_OV
5
GI_CSPRE
4
GI_VPRE
3
GI_HPRE
2
GI_INTE
1
GI_VPOL
0
GI_HPOL
Graphic Sync Processor Status
R
Description
GI_VCNT overflow flag
0 = Non-overflow
1 = Overflow
GI_HCNT overflow flag
0 = Non-overflow
1 = Overflow
Composite SYNC present flag
0 = Non-present
1 = Present
VSYNC present flag
0 = Non-present
1 = Present
HSYNC present flag
0 = Non-present
1 = Present
Interlace input detected flag
0 = Progressive input
1 = Interlaced input
VSYNC polarity
0 = Active low
1 = Active high
HSYNC polarity
0 = Active low
1 = Active high
Default: XXXX XXXXB
2008-05-05
117
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
H/V Sync Counter
0x19B
Bits
7-0
Name
GI_HCNT
[7:0]
Graphic HSYNC Counter –lo
R
Description
Hsync period counter. GI_HCNT is the number of clock (=REFCLK/4) in the
period of 32x HSYNC.
Hfreq = (REFCLK x 32)/(4 x GI_HCNT) Hz
Default: XXXX XXXXB
0x19C
Graphic HSYNC Counter –hi
Bits
4-0
Name
GI_HCNT
[12:8]
Default: XXXX XXXXB
0x19D
Bits
7-0
R
Description
MSB of GI_HCNT
Graphic VSYNC Counter –lo
Name
GI_VCNT
[7:0]
R
Description
Vsync period counter. GI_VCNT is a 12-bit counter; counter value is the
number of clock (=REFCLK/256) between two VSYNC pulses.
Vfreq = REFCLK/(256 x GI_VCNT)
Default: XXXX XXXXB
0x19E
Graphic VSYNC Counter –hi
Bits
4-0
Name
GI_VCNT
[12:8]
Default: XXXX XXXXB
Description
MSB of GI_VCNT.
H/V Free Run Divider
0x19F
HSO Free Run Divider –lo
Bits
7-0
Name
HFREE_DIV
[7:0]
R
R/W
Description
HSYNC output to sync processor free-run divider value. HSYNC pulse
width = 15x REFCLK
Hfreq (free-run) = REFCLK/(HFREE_DIV+1)
0~511
Default: 0010 0111B
0x1A0
Bits
7-1
0
HSO Free Run Divider –hi
Name
HFREE_DIV
[8]
Default: 0000 0001B
0x1A1
Bits
7-0
Description
Reserved
MSB of HFREE_DIV
VSO Free Run Divider –lo
Name
VFREE_DIV
[7:0]
R/W
R/W
Description
VSYNC output to sync processor free-run divider value. VSYNC pulse
width = 3x HFREE
Vfreq (free-run) = Hfreq (free-run)/ (VFREE_DIV+1)
0~2048
Default: 0010 0110B
2008-05-05
118
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x1A2
Bits
7-3
2-0
VSO Free Run Divider –hi
Name
VFREE_DIV
[10:8]
Default: 0000 0011B
H/V Present Threshold
0x1A3
Bits
7
6-0
Name
HPRE_THR_LO
[6:0]
R/W
Description
Reserved
MSB of VFREE_DIV
HSYNC Present Low Count Threshold
R/W
Description
Reserved
Hsync non-present counter threshold
1 (0H)~127 (7EH)
Not-present when Hfreq < REFCLK / (4 x 8192 x HPRE_THR_LO) Hz
Default: 0010 1101B
0x1A4
Bits
7
6-0
HSYNC Present High Count Threshold
Name
HPRE_THR_HI
[6:0]
R/W
Description
Reserved
Hsync present counter threshold
1 (0H)~127 (7EH)
Present when Hfreq > REFCLK / (4 x 8x HPRE_THR_HI) Hz
Default: 0010 1100B
0x1A5
Bits
7
6-0
VSYNC Present Low Count Threshold
Name
VPRE_THR_LO
[6:0]
R/W
Description
Reserved
Vsync non-present counter threshold
1 (0H)~127 (7EH)
Not-present when Vfreq < REFCLK / (4 x 8192 x VPRE_THR_LO) Hz
Default: 0010 1100B
0x1A6
Bits
7
6-0
VSYNC Present High Count Threshold
Name
VPRE_THR_HI
[6:0]
R/W
Description
Reserved
Vsync present counter threshold
1 (0H)~127 (7EH)
Present when Vfreq > REFCLK / (4 x 2048x VPRE_THR_HI) Hz
Default: 0010 1100B
H/V Frequency Change Threshold
0x1A7
HSYNC Freq Change Threshold
R/W
Bits
7-0
Name
HCNT_THR
[7:0]
Default: 0000 0000B
Description
HSYNC counter value change threshold for mode change detection.
1~256
0x1A8
VSYNC Freq Change Threshold
Bits
7-5
Name
H_CHANG_CNT
2008-05-05
R/W
Description
The INT_HFREQ will occur if the times out of HSYNC frequency change
119
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
4-0
VCNT_THR
[4:0]
Default: 0000 0000B
Interrupt Control
0x1A9
Bits
7
Name
INT_INV
5
INT_VFREQ_EN
4
INT_HFREQ_EN
3
INT_VPOL_EN
2
INT_HPOL_EN
1
INT_VEDGE_EN
0
INT_HEDGE_EN
time are more than CHANG_CNT setting.
000~111: 1, 4, 8, ~ 28 times
VSYNC counter value change threshold for mode change detection.
1~32
SYNC Interrupt Enable 1
R/W
Description
Invert the polarity of IRQn output signal
0 = Normal
1 = Invert
VSYNC frequency change interrupt enable
0 = Disable
1 = Enable
HSYNC frequency change interrupt enable
0 = Disable
1 = Enable
VSYNC polarity change interrupt enable
0 = Disable
1 = Enable
HSYNC polarity change interrupt enable
0 = Disable
1 = Enable
VSYNC rising edge occur interrupt enable
0 = Disable
1 = Enable
HSYNC rising edge occur interrupt enable
0 = Disable
1 = Enable
Default: 1000 0000B
0x1AA
SYNC Interrupt Enable 2
Bits
7-5
4
Name
INT_DVIPRE_EN
3
INT_ISPRE_EN
2
INT_CSPRE_EN
1
INT_VPRE_EN
0
INT_HPRE_EN
R/W
Description
Reserved
DVI SYNC present or non-present interrupt enable
0 = Disable
1 = Enable
Interlaced SYNC present or non-present interrupt enable
0 = Disable
1 = Enable
Composite SYNC present or non-present interrupt enable
0 = Disable
1 = Enable
VSYNC present or non-present interrupt enable
0 = Disable
1 = Enable
HSYNC present or non-present interrupt enable
0 = Disable
1 = Enable
Default: 0000 0000B
2008-05-05
120
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x1AB
SYNC Interrupt Flag 1
Bits
Name
5
INT_VFREQ
4
INT_HFREQ
3
INT_VPOL
2
INT_HPOL
1
INT_VEDGE
0
INT_HEDGE
Default: XXXX XXXXB
Description
VSYNC frequency change interrupt
HSYNC frequency change interrupt
VSYNC polarity change interrupt
HSYNC polarity change interrupt
VSYNC rising edge occur interrupt
HSYNC rising edge occur interrupt
0x1AC
SYNC Interrupt Flag 2
Bits
Name
4
INT_DVIPRE
3
INT_ISPRE
2
INT_CSPRE
1
INT_VPRE
0
INT_HPRE
Default: XXXX XXXXB
Description
DVI SYNC present or non-present interrupt
Interlaced SYNC present or non-present interrupt
Composite SYNC present or non-present interrupt
VSYNC present or non-present interrupt
HSYNC present or non-present interrupt
0x1AB
SYNC Interrupt Flag 1 Clear
Bits
Name
7-6
5
CLR_VFREQ
4
CLR_HFREQ
3
CLR_VPOL
2
CLR_HPOL
1
CLR_VEDGE
0
CLR_HEDGE
Default: 0111 1111B
Description
Reserved
Writing ‘1’ will clear INT_VFREQ flag
Writing ‘1’ will clear INT_HFREQ flag
Writing ‘1’ will clear INT_VPOL flag
Writing ‘1’ will clear INT_HPOL flag
Writing ‘1’ will clear INT_VEDGE flag
Writing ‘1’ will clear INT_HEDGE flag
0x1AC
SYNC Interrupt Flag 2 Clear
Bits
Name
7-5
4
CLR_DVIPRE
3
CLR_ISPRE
2
CLR_CSPRE
1
CLR_VPRE
0
CLR_HPRE
Default: 0000 0000B
Description
Reserved
Writing ‘1’ will clear INT_DVIPRE flag
Writing ‘1’ will clear INT_ISPRE flag
Writing ‘1’ will clear INT_CSPRE flag
Writing ‘1’ will clear INT_VPRE flag
Writing ‘1’ will clear INT_HPRE flag
0x1AD
DVI Sync Status
Bits
7-2
1
Name
DVI_DEPOL
0
DVI_SCDT
2008-05-05
R
R
W
W
R
Description
Reserved
DVI DE polarity.
0 = Active low
1 = Active high
DVI Sync Detect.
0 = When DE is inactively, indicating the link is down
1 = When DE is actively toggling indicating that the link is alive.
The SCDT output itself, however, remains in the active mode at all times.
121
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Default: XXXX XXXXB
Video Sync Processor Control
0x1AE
Bits
2
Name
VI_INTE
1
VI_VPOL
0
VI_HPOL
Video Sync Processor Status
R
Description
Interlace input detected flag
0 = Progressive input
1 = Interlaced input
VSYNC polarity
0 = Active low
1 = Active high
HSYNC polarity
0 = Active low
1 = Active high
Default: XXXX XXXXB
0x1AF
HS Auto De-bouncing
R/W
Bits
7
Name
Description
V_FRONT_BOUNCE Read-back V front status
0: No bouncing happen
1: Bouncing happen at V front porch , write “1” to clear this flag
6
V_BACK_BOUNCE Read-back V back status
0: No bouncing happen
1: Bouncing happen at V back porch , write “1” to clear this flag
5
DEBOUNCE_DEL
De-bounce manual mode delay enable
0: Disable
1: Enable
4
DEBOUNCE_AUTO 0: De-bounce auto mode
1: De-bounce manual mode
3
Reserved
2
DEBOUNCE_EN
De-bounce enable
1
Reserved
0
COMP_H_INS
Composite H insertion mode
Default: 0000 1100B
0x1B0
Bits
7-1
0
Field Polarity Control
Name
VI_FLD_INV
R/W
Description
Reserved
Invert the polarity of Video Field Detector output signal
0 = Normal
1 = Invert
Default: 0000 0000B
0x1B1
Bits Name
7-0 GI_HS_WID
[7:0]
Hsync Pulse width counter
R/W
Description
Hsync pulse width counter. GI_HS_WID is the number of REFCLK in the
period of HSYNC.
Hpswid = (1/REFCLK x GI_HS_WID)
Default: 0110 0100B
0x1B2
2008-05-05
Vsync Pulse width counter
122
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits Name
7-0 GI_VS_WID
[7:0]
Default: 0000 0000B
Description
Vsync pulse width counter. GI_VS_WID is the number of clock in the period
of HSYNC.
0x1B3
R/W
Bits Name
7-0 PRE_COAST
Description
Sets the number of Hsync periods that coast becomes active prior to Vsync
to separate input composite sync
Default: 0000 0000B
0x1B4
R/W
Bits Name
7-0 POS_COAST
Description
Sets the number of Hsync periods that coast stays active following Vsync
to separate input composite sync
Default: 0000 0000B
0x1B5
Graphic Vtotal Counter-lo
Bits Name
7-0 GI_VTOTAL
[7:0]
Default: XXXX XXXXB
R
Description
Vertical total counter. GI_VTOTAL is an 11-bit counter, counter value is the
number of Hsync between two VSYNC pulses.
0x1B6
Graphic Vtotal Counter-hi
Bits Name
2-0 GI_VTOTAL
[10:8]
Default: XXXX XXXXB
R
Description
MSB of GI_VTOTAL
0x1B7 : Reserved
8.25. LVDS Output Control
0x1B8
Bits
7
6
5-3
LVDS Output Control
R/W
Name
Description
LVDS_POL_SWAP LVDS Channel Polarity Swap (Positive/Negative)
0 = Normal
1 = Enable
LVDS_CH_SWAP LVDS Channel Swap
0 = Normal
1 = Enable, When enable, T0/T3 swap, TCLK1/T1 swap, T4/T7 swap,
TCLK2/T5 swap
LVDS_LEVEL
Fine tune LVDS output differential voltage
[2:0]
000: Standard output 200 mVp-p
001: Output 250 mVp-p
010: Output 300 mVp-p
011: Output 450 mVp-p
100~111: Reserved
2008-05-05
123
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
2-1
LVDS_ICO
[1:0]
0
LVDS_RFB
Charge pump current
00 : 60uA
01 : 100uA
10 : 200uA
11 : 320uA
Data strobe edge selection
0 = falling edge strobe
1 = rising edge strobe
Default: 0000 0000B
0x1B9
Bits
7-2
1
Display Output Interface Control
Name
DOS_SEL
0
Default: 0001 0000B
R/W
Description
Reserved
Display output interface selection when timing controller disable
0 = LVDS
Reserved
0x1BA : Reserved
0x1BB
Auto offset Control -1
Bits Name
7
AO_SATU_PRETECT
6-5
4-0
CALCUL_PERIOD
R/W
Description
Auto offset saturation protect ( for clamp 0V mode only )
0: Disable ( for YpbPr mode )
1: Enable ( for RGB mode )
Reserved
Define the period of data calculation that start from falling edge of
clamp pulse + 8T
Set “1” mean is 1x8+7=15 pixel be calculated for auto offset
Default: 0000 0000B
0x1BC
Auto offset Control -2
Bits Name
7
AO_LINE_MODE_RDY
6
AO_LINE_MODE
5-1
1
0
AO_EN
R/W
Description
Auto offset line mode ready, When detection is finished, this bit is set to
“1”
Auto offset line mode enable
0 = Disable
1 = Enable
Reserved
Default “1” for auto offset enable
Auto offset enable
0 = Disable
1 = Enable
Default: 0000 0000B
0x1BD
Bits
Name
7-0
AO_RVALUE
Default: 0000 0000B
0x1BE
2008-05-05
Auto offset target value of Red channel
R/W
Description
Auto offset target value of Green channel
124
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits
Name
7-0
AO_GVALUE
Default: 0000 0000B
Description
0x1BF
Bits
Name
7-0
AO_RVALUE
Default: 0000 0000B
0x1C0
Auto offset target value of Blue channel
R/W
Description
Auto offset adjust value – Red channel
R
Bits
Name
Description
7-0
AO_ADJ_RVALUE
Default: 0000 0000B
0x1C1
Auto offset adjust value – Green channel
R
Bits
Name
Description
7-0
AO_ADJ_GVALUE
Default: 0000 0000B
0x1C2
Auto offset adjust value – Blue channel
R
Bits
Name
Description
7-0
AO_ADJ_RVALUE
Default: 0000 0000B
0x1C3
Auto offset mid value read back – Red channel
R
Bits
Name
Description
7-0
AO_MID_RVALUE
Default: 0000 0000B
0x1C4
Auto offset mid value read back – Green channel
R
Bits
Name
Description
7-0
AO_MID_GVALUE
Default: 0000 0000B
0x1C5
Auto offset mid value read back – Blue channel
R
Bits
Name
Description
7-0
AO_MID_RVALUE
Default: 0000 0000B
0x1C6~0x1CB : Reserved
0x1CC
Bits
7-3
2
Name
1
GA_ARD_EN
DP_ARD_EN
0
SRGB_ARD_EN
Default: 0000 0000B
Asynchronous Random dithering Control
R/W
Description
Reserved
Display asynchronous random dithering enable
0x1DA.4 or 0x1DA.5 must enable
Gamma asynchronous random dithering enable
0x158.2 set “1”
SRGB asynchronous random dithering enable
0x1CD~0x1CF : Reserved
2008-05-05
125
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
8.26. sRGB Control
0x1D0
Bits
7
6
sRGB Control
R/W
Name
BF_SRGB_EN
SRGB_TBL_SEL
Description
Bright frame sRGB enable
sRGB access select
0: Normal sRGB
1: Bright frame sRGB
5
SRGB_DITH_EN
sRGB dithering enable , 0X1D0.0 must set “1”
4
RANDOM_DITH_EN 0: Static dithering enable
1: Random dithering enable
3
SRGB_FORCE_UPD Force update sRGB
0: Disable
1: Force update the sRGB Coefficient to H/W , if 0x161[1:0] set “11” then
these sRGB register update on next DVS
2-1 SRGB_BK_SEL
Select sRGB 3x3 matrix Row bank
00 = Row1
01 = Row2
10 = Row3
11 = Reserved
0
SRGB_En
sRGB Enable
0: Disable
1: Enable
Default: 0000 1000B
0x1D1
sRGB Transfer Coefficient R Channel – lo
R/W
Bits
7-0
Name
Description
SRGB_COLUM_1 sRGB 3x3 matrix Column 1 coefficient LSB
[7:0]
-1024 ~ 1023
Default: 0000 0000B
0x1D2
sRGB Transfer Coefficient R Channel – hi
R/W
Bits
2-0
Name
Description
SRGB_COLUM_1 sRGB 3x3 matrix Column 1 coefficient MSB
[10:8]
Default: 0000 0001B
0x1D3
sRGB Transfer Coefficient G Channel – lo
R/W
Bits
7-0
Name
Description
SRGB_COLUM_2 sRGB 3x3 matrix Column 2 coefficient LSB
[7:0]
-1024 ~ 1023
Default: 0000 0000B
0x1D4
sRGB Transfer Coefficient G Channel – hi
R/W
Bits
2-0
Name
Description
SRGB_COLUM_2 sRGB 3x3 matrix Column 2 coefficient MSB
[10:8]
Default: 0000 0000B
0x1D5
Bits
sRGB Transfer Coefficient B Channel – lo
Name
2008-05-05
R/W
Description
126
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
SRGB_COLUM_3 sRGB 3x3 matrix Column 3 coefficient LSB
[7:0]
-1024 ~ 1023
Default: 0000 0000B
7-0
0x1D6
sRGB Transfer Coefficient B Channel – hi
R/W
Bits
2-0
Name
Description
SRGB_COLUM_3 sRGB 3x3 matrix Column 3 coefficient MSB
[10:8]
Default: 0000 0000B
0x1D7
sRGB Offset Coefficient
R/W
Bits Name
Description
7-0 SRGB_COEF_OFFSET The offset coefficient of sRGB matrix
[7:0]
-7F ~ 7F
Default: 1000 0000B
0x1D8
Bits
7
sRGB Dithering Control 1
Name
RANDOM_RST
6
5-4
DITH_10
3
2-0
DITH_01
Default: 0000 0000B
R/W
Description
Display random dither reset mode ( 0x1ED[4] must set “1” )
0: Disabel
1: Enable
Reserved
“10” dithering type , 0x1D0.4 must set “0”
Reserved
“01” dithering type , 0x1D0.4 must set “0”
0x1D9 : Reserved
0x1DA
Display Random Dithering Control
Bits
7
6
Name
RST_PERIOD
5
MIX_DITH_EN
4
3-2
RANDOM_EN
STATIC_CNT
1-0
RANDOM_CNT
R/W
Description
Reserved
Random reset period setting
0 = 1 frame
1 = if DITH_TURBO (Reg. 0x158[1]) set to “1”, the period is 4 frame
else the period is 16 frame
Display Mix mode Dithering Enable
0: Disable
1: Enable
Random dithering mode enable
Static dithering active period counter
0x1DA.5 must enable
Random dithering active period counter
0x1DA.5 must enable
Default: 0000 0111B
0x1DB
Bits
7-6
5-4
3
Gamma Dithering Control
Name
DITH_10
2008-05-05
R/W
Description
Reserved
“10” dithering type , 0x158.2 must set “0” , 0x1DB.7 set “0”
Reserved
127
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
2-0
DITH_01
Default: 0000 0000B
“01” dithering type , 0x158.2 must set “0” , 0x1DB.7 set “0”
0x1DC ~ 0x1E5 : Reserved
0x1E6
ADC test mode Control
Bits
7
Name
6
5
4-1
0
RSTB
R/W
Description
Internal LDO
0: 1.8V ( resistor )
1: 1.6V ( bandgap )
Reserved
Internal LDO
0: 1.8V ( resistor )
1: 1.6V ( bandgap )
Reserved
Reset ADC data to low
0: Reset
1: Normal
Default：0000 0001B
0x1E7
HPLL LDO
Bits
7-2
1
Name
0
PAGE3_OPTION
HPLL _LDO
R/W
Description
Reserved
HPLL LDO
0: 1.8V ( bandgap )
1: 1.6V ( resistor )
Page 3 function option
0: HDCP control
1: DVI auto equalize
Default：0100 0000B
0x1E8 ~ 0x1EC : Reserved
0x1ED
Bits
7
6
5
3
ADC Power Cotrol
Name
ADC_BIAS[3]
BW[3]
BG_SEL
2-0
Default：0000 0000B
Description
Reserved
ADC OP bios select MSB , 0x1F1 for LSB
ADC bandwidth MSB
ADC BIOS
0: Reseistor
1: Bandgap
Reserved
0x1EE
Power Down Control
Bits
7
6
5
4
3
Description
Reserved
BF bypass for power down
OSD bypass for power down
Gamma bypass for power down
Display dither bypass for power down
Name
BF_PWN
OSD_PWN
GAMMA_PWN
DIS_DITHER_PWN
2008-05-05
R/W
128
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
2
GAMMA_DITHER_PWN
1
0
sRGB_PWN
Default：0000 0010B
0x1EF
Bits
7-3
2
Gamma dither bypass for power down
Reserved
sRGB bypass for power down
LVDS Control
Name
LVDS_PWR
1-0
Default：0000 0100B
R/W
Description
Reserved
0: LVDS off
1: LVDS on
Reserved
0x1F0 : Reserved
0x1F1
ADC Control
R/W
Bits
Name
7-6
5-4
RADC_BIAS[1:0]
3-2
GADC_BIAS[1:0]
1-0
BADC_BIAS[1:0]
Default：0011 1111B
Description
Reserved
RADC OP bios select
RADC OP bios select
RADC OP bios select
0x1F2 ~ 0x1F3 : Reserved
0x1F4
LVDS Control
Bits
Name
7-0
Default：1000 0010B
Description
LVDS internal circuit control option
0x1F5
LVDS Control
Bits
7
6
5
4
Name
LVDS_OFFSET
PULL_LOW
3-0
Default：0000 0000B
R/W
R/W
Description
Reserved
LVDS offset voltage source
0: Band gap
1: Resistor
Reserved
LVDS output power down buffer control
0: Pull low output
1: Tri-state output
For internal circuit option
0x1F6
LVDS Control
Bits
Name
7-0
Default：0000 0000B
Description
LVDS internal circuit control option
0x1F7
LVDS Control
Bits
Name
2008-05-05
R/W
R/W
Description
129
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
7
PD_LV1
6
PD_LV2
5-0
Default：0010 0010B
LVDS port A power control
0: Power down
1: Power up
LVDS port B power control
0: Power down
1: Power up
Reserved
0x1F8 ~ 0x1F9 : Reserved
0x1FA
LVDS Control
R/W
Bits
Name
7
Default：0000 0000B
Description
LVDS internal circuit control option
0x1FB ~ 0x1FE : Reserved
0x1FF
Bits
7-2
1-0
Accessing Register Page Enable
R/W
Name
Description
Reserved
REG_PAGE_SEL Register Page Enable
000: Enable register Page0.
001: Enable register Page1.
010: Enable register Page2.
011: Enable register Page3.
100: Enable register Page4.
Default: 0000 0000B
0x200 ~ 0x2FE : Reserved
0x2FF
Bits
7-2
1-0
Accessing Register Page Enable
R/W
Name
Description
Reserved
REG_PAGE_SEL Register Page Enable
000: Enable register Page0.
001: Enable register Page1.
010: Enable register Page2.
011: Enable register Page3.
100: Enable register Page4.
Default: 0000 0000B
2008-05-05
130
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
8.27. High-bandwidth Digital Content Protection System
HDCP Index Port Access Control
See section 9.14 Index Port Access Control
HDCP Control Register Map
ADDRESS
0x300 ~
0x301 ~
0x302 ~
0x303 ~
0x304
R/W Register Name
R
BKSV[7:0]
BKSV[15:8]
BKSV[23:16]
BKSV[31:24]
BKSV[39:32]
0x305 ~
0x307
0x308 ~
0x309
R
RESERVED
R
Ri’[7:0]
Ri’[15:8]
2008-05-05
Description
For transmitter read only
Video receiver KSV. This value must always be available for
reading, and may be used to determine that the video receiver is
HDCP capable. Valid KSVs contain 20 ones and 20 zeros, a
characteristic that must be verified by video transmitter hardware
before encryption is enable.
Reserved All bytes read as 0x00
For transmitter read only
Link verification response. Updated every 128 th frame. It is
recommended that graphics systems protect against errors in the
I2C transmission by reading this value when unexpected values
are received. This value must be available at all times between
updates. R0’ must be available a maximum of 100ms after AKSV is
received. Subsequent Ri’ values must be available a maximum of
131
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x30A
R
Pj’
0x30B~0x30F R
0x310 ~
R
0x311 ~
0x312 ~
0x313 ~
0x314
RESERVED
AKSV[7:0]
AKSV[15:8]
AKSV[23:16]
AKSV[31:24]
AKSV[39:32]
0x315
Ainfo
R
0x316 ~0x317 R
0x318 ~
R
0x319 ~
0x31A ~
0x31B ~
0x31C ~
0x31D ~
0x31E ~
0x31F
0x320~0x33F
0x340
W
2008-05-05
RESERVED
An[7:0]
An[15:8]
An[23:16]
An[31:24]
An[39:32]
An[47:40]
An[55:48]
An[63:56]
Bcaps
128 pixel clocks following the assertion of CTL3
For transmitter read only ( for HDCP V1.1 )
Enhanced Link Verification Response. Updated upon receipt of
first video pixel received when frame counter value (j mod 16) ==
0. The value is the XOR of the decrypted byte on channel zero of
the first video pixel with the least significant byte of Rj. Rj is derived
from the output function in the same manner as Ri, but is captured
every 16th counted frame (rather than every 128th counted frame).
Reserved All bytes read as 0x00
For transmitter write only
HDCP Transmitter KSV. Writes to this multi-byte value are written
least significant byte first. The final write to 0x14 triggers the
authentication sequence in the HDCP Receiver, and the current
Ainfo value is copied from the port, takes effect, and the port is
reset to the default value of zero.
For transmitter write only
Bits 7-2: Reserved zeros.
Bit 1: ENABLE_1.1_FEATURES. This bit enables the Advance
Cipher option. If in DVI mode, it also enables the Enhanced
Encryption Status Signaling (EESS) (in HDMI mode, EESS is
enabled regardless of this bit setting). This bit resets to default
zero when the HDCP Receiver becomes attached or active, or is
reset, or the last byte of Aksv is written. A write to the last byte of
Aksv copies the port value and causes it to take effect, and then
resets the port value to the default value of zero. Thus the options
must be explicitly enabled prior to each authentication.
Bit 0: Reserved (must be zero).
Reserved All bytes read as 0x00
For transmitter write only
Session random number. This multi-byte value must be written by
the HDCP
Transmitter before the KSV is written.
Reserved
For transmitter read only
Bit 7-5: Reserved
Bit 4: FAST.
When set to one, this device supports 400 KHz transfers.
When zero, 100 KHz is the maximum transfer rate
supported. Note that 400KHz transfers are not permitted to
any device unless all devices on the I2C bus are capable of
400KHz transfer. The transmitter may not be able to
determine if the EDID ROM, present on the HDCP
Receiver, is capable of 400KHz operation. This bit does not
change while the HDCP Receiver is active.
Bits 3-2: Reserved (must be zero).
Bit 1: 1.1_FEATURES.
When set to one, this HDCP Receiver supports Enhanced
132
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Encryption Status Signaling (EESS), Advance Cipher, and
Enhanced Link Verification options. For the HDMI protocol,
Enhanced Encryption Status Signaling (EESS) capability is
assumed regardless of this bit setting. This bit does not
change while the HDCP Receiver is active.
Bit 0: FAST_REAUTHENTICATION.
When set to 1, the receiver is capable of receiving
(unencrypted) video signal during the session
re-authentication. All HDMI-capable receivers shall be
capable of performing the fast re-authentication even if this
bit is not set. This bit does not change while the HDCP
Receiver is active.
Default: 8’h11
Reserved
0x341 ~
0x342
0x343
R
0x344
R
Ri’ Frame
count
Frame Pj’
0x345
R
Frame Ri’(l)
0x346
R
Frame Ri’(h)
0x347
R
MISC CTRL
Status
0x348
R
Mi’ byte0
0x349
R
Mi’ byte1
0x34A
R
Mi’ byte2
0x34B
R
Mi’ byte3
0x34C
R
Mi’ byte4
0x34D
R
Mi’ byte5
0x34E
R
Mi’ byte6
0x34F
R
Mi’ byte7
0x350
R
Ks’ byte0
0x351
R
Ks’ byte1
0x352
R
Ks’ byte2
2008-05-05
Frame count status for Ri’ update
Default: 8’h00
Pj’ value for every frame
Default: 8’h00
Ri’ low byte value for every frame
Default: 8’h00
Ri’ high byte value for every frame
Default: 8’h00
Bit 7~ 4: Frame count status for Pj’ update
Bit 3: Authentication ok
Bit 2: Km calculation finished
Bit 1: Aksv bytes are all received
Bit 0: Ainfo in effect
Default: 8’h00
Mi’ byte0 value for every frame
Default: 8’h00
Mi’ byte1 value for every frame
Default: 8’h00
Mi’ byte2 value for every frame
Default: 8’h00
Mi’ byte3 value for every frame
Default: 8’h00
Mi’ byte4 value for every frame
Default: 8’h00
Mi’ byte5 value for every frame
Default: 8’h00
Mi’ byte6 value for every frame
Default: 8’h00
Mi’ byte7 value for every frame
Default: 8’h00
Ks’ byte0 value of session key
Default: 8’h00
Ks’ byte1 value of session key
Default: 8’h00
Ks’ byte2 value of session key
Default: 8’h00
133
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x353
0x354
0x355
0x356
0x357
0x358
0x359
0x35A
0x35B
0x35C
0x35D
0x35E
0x35F
0x360
2008-05-05
R
Ks’ byte3
Ks’ byte3 value of session key
Default: 8’h00
R
Ks’ byte4
Ks’ byte4 value of session key
Default: 8’h00
R
Ks’ byte5
Ks’ byte5 value of session key
Default: 8’h00
R
Ks’ byte6
Ks’ byte6 value of session key
Default: 8’h00
R
Ki’ byte0
Ki’ byte0 for every frame
Default: 8’h00
R
Ki’ byte1
Ki’ byte1 for every frame
Default: 8’h00
R
Ki’ byte2
Ki’ byte2 for every frame
Default: 8’h00
R
Ki’ byte3
Ki’ byte3 for every frame
Default: 8’h00
R
Ki’ byte4
Ki’ byte4 for every frame
Default: 8’h00
R
Ki’ byte5
Ki’ byte5 for every frame
Default: 8’h00
R
Ki’ byte6
Ki’ byte6 for every frame
Default: 8’h00
R/W Authentication Bit 7: Self test done ( read status )
Built in Self
Bit 6: BIST is working ( read status )
Test Status
Bit 5: R0’ fault
Bit 4: M0’ fault
Bit 3: Ks’ fault
Bit 2: Km’ fault
Bit 1: Self test fault happens due to Bit5~Bit2 faults
Bit 0: Authentication BIST enable ( use internal 2 test keys )
Default: 8’h00
R/W Key set pair
Bit7~Bit2: Reserved
select for
Bit1~0: ( for self test )
Authentication 00: A1-B1 key pair
Built in Self
01: A1-B2 key pair
Test
10: A2-B1 key pair
11: A2-B2 key pair
Default: 8’h00
R/W HDCP Input
Bit 7: HDCP clk input from
Control
1: Ref clk ( for start up load key to HDCP address from eeprom )
0: pixel clk(TMDS) for normal operate
Bit 6: HDCP clk input invert mode ( TMDS clk )
1: clk inverted
0: clk non-inverted
Bit 5~3: HDCP input DE pipe delay selection
000: no delay
001: 1T delay
010: 2T delay
011: 3T delay
100: 4T delay
others: 5T delay
134
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x361
R/W
0x362
R
0x363
R
0x364
R/W
0x365~0x367 R
0x368
R/W
0x369
R
0x36A
R/W
2008-05-05
Bit 2~0: HDCP input data pipe delay selection
000: no delay
001: 1T delay
010: 2T delay
011: 3T delay
100: 4T delay
others: 5T delay
Default: 8’h80
HDCP Input
Bit 7~4: Reserved
Sync Selection Bit 3 : HDCP Key Set Decryption ( for key set decode that from
eeprom )
Bit 2 : Reserved
Bit 1 : V Sync selection from separated sync or decomposed sync
1: decomposed sync ( for DE mode )
0: separated sync
Bit 0 : H Sync selection from separated sync or decomposed sync
1: decomposed sync
0: separated sync
default : 8’h00
SRAM Status0 Bit7~0: SRAM address[7:0] for SRAM access ( for debug only)
Default: 8’h00
SRAM_Status1 Bit0: SRAM address[8] for SRAM access (for debug only)
Bit1: SRAM Arbitration (for debug only)
1: Servicing for HDCP cipher machine request
0: Servicing for MCU read/write request ( for initial HDCP )
Default: 8’h00
Ri Update
Bit7:0 For every this (Ri_update_frame_count+1) value is
Frame Count reached, the Ri value will be updated for constantly link check, for
example, if 127 is set, then for every 128th frame count, the Ri
value will be updated
Default : 8’h7F
Reserved
HDCP Slave Bit7~1: HDCP Slave Address on DDC I2C bus
Address
Bit0 : HDCP reset , 0: Normal , 1: Reset
Defaut: 0x74
HDCP Status Bit 7: TMDS control status bit 3 ( read TMDS control bit )
Bit 6: TMDS control status bit 2
Bit 5: TMDS control status bit 1
Bit 4: TMDS control status bit 0
Bit 3: HDCP enable
1: HDCP clock enable
0: HDCP clock disable ( for power down )
Bit 2: HDCP interrupt enable
1: interrupt enable while receiver first authentication ready .
0: interrupt disable
Bit 1: Authentication done flag , write ‘1’ to this bit will clear this flag
to 0
Bit 0: AKSV transfer done flag , write ‘1’ to this but will clear this
flag to 0
Default: 8’h00
Window of
Bit 7~0: Low byte of window of opportunity lower bound for eess
135
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Opportunity
Lower Bound
0x36B
R/W Window of
Opportunity
Lower Bound
R/W Window of
Opportunity
Upper Bound
R/W Window of
Opportunity
Upper Bound
0x36C
0x36D
0x306
Bits
7-2
1-0
( EESS valid window start )
Receive TMDS control bit 3 ~ 0 at 512th ~ 528th pixel from VS start
edge , if this code is “1001” then indicate this frame is encrypted .
Default: 8’h00
Bit 7~0: High byte of window of opportunity lower bound for eess
Default: 8’h02
Bit 7~0: Low byte of window of opportunity upper bound for eess
( EESS valid window end )
Default: 8’h10
Bit 7~0: High byte of window of opportunity upper bound for eess
Default: 8’h02
DVI Auto Equalize-1
Name
DVI_AUTO_CH_SEL
R/W
Description
Reserved
Detect channel setecl , 0x1E7.0 must set “1” and read-back
from 0x317 ~ 0x31B
00 : Blue
01 : Green
10 : Red
Default: 0000 0000B
0x308
Bits
7-3
2
DVI Auto Equalize-2
Name
1
0
R
Description
Reserved
For R uality , read-back data if “1” indicate input data decode
maybe is error , 0x309.0 for enable this function
For G uality , read-back data if “1” indicate input data decode
maybe is error , 0x309.0 for enable this function
For B uality , read-back data if “1” indicate input data decode
maybe is error , 0x309.0 for enable this function
Default: 0000 0000B
0x309
Bits
7-1
0
DVI Auto Equalize-3
Name
R/W
Description
Reserved
DVI decode data check , write “1” and if read back “0” mean is
ready for 0x308 read back
0: Disable
1: Enable
Default: 0000 0000B
0x310
Bits
7-0
DVI Auto Equalize-4
Name
R/W
Description
Set 0x13 for 0x317 ~ 0x31B read-back function
Bit-0 write “1” and if read back “0” mean is ready for 0x317 ~
0x31B read back
Default: 0000 0000B
2008-05-05
136
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x311
DVI Auto Equalize-5
Bits
Name
7-0
Default: 0000 0000B
Description
Set 0x55 for 0x317 ~ 0x31B check cycle is 1V
0x317 ~0x31B
DVI Auto Equalize-6
Bits
7-0
Description
DVI eye diagram quality check , more continue “0” mean is
better signal uality .
Set 0x01E is “0x08 ~ 0x38” , “0xBF” , “0xEF” , “0xFF” to get
better setting .
Name
R/W
R
Default: 0000 0000B
0x338
Bits
7
DVI AC Couple
Name
6-4
3-0
Default: 0111 1100B
R/W
Description
DVI CLK AC couple
0: Disable
1: Enable
DVI RGB AC couple
0: Disable
1: Enable
Reserved
8.28. Dithering Function 2
0x370
Bits
7
Dither block blending control
R/W
Name
LSB10_BLEND_TYPE
Description
0: Static and dynamic ordered blending .
1: Random and dynamic ordered blending .
6
LSB01/11_BLEND_TYPE
0: Static and dynamic ordered blending .
1: Random and dynamic ordered blending .
5
LSB10_BLEND_EN
0: Disable .
1: Enable .
4-3
LSB10_BLEND_LOGIC_OP
00: Or .
01: Xor .
10: Xor .
11: And .
2
LSB01/11_BLEND_EN
0: Disable .
1: Enable .
1-0
LSB01/11_BLEND_LOGIC_OP 00: Or .
01: Xor .
10: Xor .
11: And .
Default: 0000 0000B
0x371
Bits
7
6
5
Dither Toggle / Mix Control
Name
2008-05-05
R/W
Description
Reserved
mix_3in1_dither_en(B) , 0x371.1 must set “1”
mix_3in1_dither_en® , 0x371.1 must set “1”
137
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
4
3-2
1
0
BLOCK_TOGGLE_EN
mix_3in1_dither_en(G)
Reserved
0: R/G/B control depends on G channel
1: Use separate control registers
0: Disable .
1: Enable . .( 0x370 blend must enable )
Default: 0000 0000B
0x372
Separate R Dithering Control-1
Bits
Name
7-4
3-0
Default: 0000 0000B
Description
R channel “10“ dithering option , 0x371.1 must set “1“
R channel dither mode , , 0x371.1 must set “1“
0x373
Separate R Dithering Control-2
Bits
Name
7-6
5
4
3-2
1-0
Default: 0000 0000B
Description
Reserved
Mixed dither enable
Dynamic dither
Dynnmic mode [1:0]
Static mode [1:0]
0x374
Separate R Dithering Control-3
Bits
7
Name
LSB10_BLEND_TYPE
6
LSB01_BLEND_TYPE
5
LSB10_BLEND_EN
4-3
LSB10_BLEND_LOGIC_OP
2
LSB01_BLEND_EN
1-0
LSB01_BLEND_LOGIC_OP
R/W
R/W
R/W
Description
0: Static and dynamic ordered blending .
1: Random and dynamic ordered blending .
0: Static and dynamic ordered blending .
1: Random and dynamic ordered blending .
0: Disable .
1: Enable .
00: Or .
01: Xor .
10: Xor .
11: And .
0: Disable .
1: Enable .
00: Or .
01: Xor .
10: Xor .
11: And .
Default: 0000 0000B
0x375
Separate B Dithering Control-1
Bits
Name
7-4
3-0
Default: 0000 0000B
Description
B channel “10“ dithering option , 0x371.1 must set “1“
B channel dither mode [3:0] , , 0x371.1 must set “1“
0x376
Separate B Dithering Control-2
Bits
Name
2008-05-05
R/W
R/W
Description
138
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
7-6
5
4
3-2
1-0
Default: 0000 0000B
Reserved
Mixed dither enable
Dynamic dither
Dynnmic mode [1:0]
Static mode [1:0]
0x377
Separate B Dithering Control-3
Bits
7
Name
LSB10_BLEND_TYPE
6
LSB01_BLEND_TYPE
5
LSB10_BLEND_EN
4-3
LSB10_BLEND_LOGIC_OP
2
LSB01_BLEND_EN
1-0
LSB01_BLEND_LOGIC_OP
R/W
Description
0: Static and dynamic ordered blending .
1: Random and dynamic ordered blending .
0: Static and dynamic ordered blending .
1: Random and dynamic ordered blending .
0: Disable .
1: Enable . 0x371.0 must set “1“
00: Or .
01: Xor .
10: Xor .
11: And .
0: Disable .
1: Enable . 0x371.0 must set “1“
00: Or .
01: Xor .
10: Xor .
11: And .
Default: 0000 0000B
0x378~0x37F : Reserved
2008-05-05
139
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
8.29. Horizontal Non-Linear Scaling Function
Center Point
Slope1
Slope2
Zone1
Zone2
Non-linear Position
Display Active Window
0x380
Bits
7-1
0
Horizontal non-linear scaling Control
Name
NL_SCALING_EN
R/W
Description
Reserved
0 = normal linear scaling applied to entire image.
1 = enable non-linear scaling ( 16:9 display zoom ratio )
Default: 0000 0000B
0x381
Non-linear scaling Offset Adjust
Bits
Name
7-0
NL_OFF[7:0]
Default: 0000 0000B
Description
Adjust the error for scaling factor.
0x382
Non-linear scaling Factor Zone1 end – Low Byte
Bits
7-0
Name
NL_ZONE1_END
[7:0]
Default: 0000 0000B
Description
Sets the Scaling Factor in the first non-linear scaling region (ZONE1).
0x383
Non-linear scaling Factor Zone1 end – High Byte
Bits
7-0
Description
Sets the Scaling Factor in the first non-linear scaling region (ZONE1).
Name
NL_ZONE1_END
[15:8]
Default: 0000 0000B
0x384
2008-05-05
Non-linear scaling Zone1 Slope – Low Byte
140
R/W
R/W
R/W
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits
Name
7-0
NL_SLOPE1 [7:0]
Default: 0000 0000B
Description
Sets the Slope Factor in the first non-linear scaling region (ZONE1).
0x385
Non-linear scaling Zone1 Slope – High Byte
Bits
Name
7-0
NL_SLOPE1 [15:8]
Default: 0000 0000B
Description
Sets the Slope Factor in the first non-linear scaling region (ZONE1).
0x386
Non-linear scaling Factor Zone2 end – Low Byte
R/W
R/W
Bits
Name
Description
7-0
NL_ZONE2_END [7:0] Sets the Scaling Factor in the first non-linear scaling region (ZONE2).
Default: 0000 0000B
0x387
Non-linear scaling Factor Zone2 end – High Byte
R/W
Bits
7-0
Name
NL_ZONE2_END
[15:8]
Default: 0000 0000B
Description
Sets the Scaling Factor in the first non-linear scaling region (ZONE2).
0x388
Non-linear scaling Zone2 Slope – Low Byte
Bits
Name
7-0
NL_SLOPE2 [7:0]
Default: 0000 0000B
Description
Sets the Slope Factor in the first non-linear scaling region (ZONE2).
0x389
Non-linear scaling Zone2 Slope –High
Bits
Name
7-0
NL_SLOPE2 [15:8]
Default: 0000 0000B
Description
Sets the Slope Factor in the first non-linear scaling region (ZONE2).
0x38A
Non-linear Position – Low Byte
Bits
Name
7-0
NL_CBEG [7:0]
Default: 0000 0000B
Description
Sets the Position of ZONE1 and ZONE2.
0x38B
Non-linear Position – High Byte
Bits
Name
7-0
NL_CBEG [15:8]
Default: 0000 0000B
Description
Sets the Position of ZONE1 and ZONE2. .
R/W
R/W
R/W
R/W
0x38C~0x38F : Reserved
8.30. Bright Frame Border Function
0x390
Bits
7
Bright Frame Windows Border control
Name
BF1_BORDER_ EN
2008-05-05
R/W
Description
BF1 border
0 = Disable
1 = Enable
141
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6
BF2_BORDER_ EN
BF2 border
0 = Disable
1 = Enable
5
Reserved
4
GAMMA_POSITION_SW Switching Gamma position
0: After OSD block
1: Before BF block
3
BF2_ YUV2RGB _EN
BF2 YUV to RGB color space
0 = Disable.
1 = Enable
2
BF2_RGB2YUV_ EN
BF2 RGB to YUV color space
0 = Disable.
1 = Enable
1
BF1_YUV2RGB _EN
BF1 YUV to RGB color space
0 = Disable.
1 = Enable
0
BF1_RGB2YUV_ EN
BF1 RGB to YUV color space
0 = Disable.
1 = Enable
Default: 0000 0000B
0x391
Bright Frame Border R color control
Bits
Name
7-0
BF_BORDER_R[7:0]
Default: 0000 0000B
Description
Bright frame border color R[7:0] .
0x392
Bright Frame Border G color control
Bits
Name
7-0
BF_BORDER_G[7:0]
Default: 0000 0000B
Description
Bright frame border color G[7:0] .
0x393
Bright Frame Border B color control
Bits
Name
7-0
BF_BORDER_B[7:0]
Default: 0000 0000B
Description
Bright frame border color B[7:0] .
0x394
Bright Frame Border enable control
Bits
7-3
2
R/W
R/W
R/W
R/W
Name
Description
Reserved
BF_BORDER_TOP/BO Bright frame top/bottom border enable control
T
0: Disable
1: Enable.
1
BF_BORDER_RIGHT Bright frame right border enable control
0: Disable
1: Enable.
0
BF_BORDER_LEFT
Bright frame left border enable control
0: Disable
1: Enable.
Default: 0000 0000B
0x395~0x399 : Reserved
2008-05-05
142
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x39A
Sub-Pixel Dither Control
Bits
Name
7
6-4
2
10_SUBPIXEL
1
01_SUBPIXEL
0
MIX_ENABLE
Default: 0000 0000B
Description
Pattern 025_1 enable
Pattern 025_0 enable
Pattern 05 sub-pixel enable , 0x371.4 set “1”
Pattern 025 sub-pixel enable , 0x371.4 set “1”
Enable mix mode
0x39B
Sub-Pixel Dither Control
Bits
Name
7-5
4-2
1
0
Default: 0000 0000B
Description
Pattern 025_3 enable
Pattern 025_2 enable
Pattern 025_1 enable
Pattern 025_1 enable
0x39C
Sub-Pixel Dither Control
Bits
Name
7-0
Default: 0000 0000B
Description
Pattern 05 enable
0x39D
Mix Dither Mode Control
Bits
7-6
5
Name
STATIC_CNT[2]
4
RANDOM_CNT[2]
3
STATIC_CNT[2]
2
RANDOM_CNT[2]
1
STATIC_CNT[2]
0
RANDOM_CNT[2]
R/W
R/W
R/W
R/W
Description
Reserved
Static dithering active period counter for B channel
0x376[5:4] set “11”
0x376[3:2] for STATIC_CNT[1:0]
0x371[1] must set “1”
Random dithering active period counter for B channel
0x376[5:4] set “11”
0x376[1:0] for RANDOM _CNT[1:0]
0x371[1] must set “1”
Static dithering active period counter for G channel
0x1DA[5:4] set “11”
0x1DA[3:2] for STATIC_CNT[1:0]
Random dithering active period counter for G channel
0x1DA[5:4] set “11”
0x1DA[1:0] for RANDOM _CNT[1:0]
Static dithering active period counter for R channel
0x373[5:4] set “11”
0x373[3:2] for STATIC_CNT[1:0]
0x371[1] must set “1”
Random dithering active period counter for R channel
0x373[5:4] set “11”
0x373[1:0] for RANDOM _CNT[1:0]
0x371[1] must set “1”
Default: 0000 0000B
0x39E
2008-05-05
Mix 3 in 1Dither Mode Control
143
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Bits
7-6
5-4
Name
R_MIX3_TYPE
3-2
1-0
G_MIX3_TYPE
Description
Reserved
Mix 3 in 1 dithering mode random type for R channel
0x373 set “0x00”
0x371 set “0x72”
00: original (4/16 random)
01: 1/16 random
10: 2/16 random
11: Reserved
Reserved
Mix 3 in 1 dithering mode random type for G channel
0x1DA set “0x00”
0x371 set “0x72”
00: original (4/16 random)
01: 1/16 random
10: 2/16 random
11: Reserved
Default: 0000 0000B
0x39F
Mix 3 in 1Dither Mode Control
Bits
7-2
1-0
Name
R/W
Description
Reserved
Mix 3 in 1 dithering mode random type for B channel
0x376 set “0x00”
0x371 set “0x72”
00: original (4/16 random)
01: 1/16 random
10: 2/16 random
11: Reserved
B_MIX3_TYPE
Default: 0000 0000B
8.31. Y/C Peaking Control
High Pass Filter
Throshold
Gain
+
Y/C peaking Block
0x3A0
Y/C Peaking Function Control
Bits
7-6
5
CHROMA_PEAK_MEDIAN_EN
4
CHROMA_PEAK_EN
Description
Reserved
These bits set the chroma median peaking control. (average
Cb,Cr high pass value)
0: Disabled
1: Enabled
These bits set the chroma peaking control. (Cb,Cr high pass)
0: Disabled
Name
2008-05-05
144
R/W
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
3-2
1
TEXT_ENHANCE
0
LUMA_PEAK_EN
1: Enabled
Reserved
Text enhance , the priority higher than LUMA_PEAK_EN
0: disabled
1: enabled
This bit enables the luma horizontal peaking control ,
0: Disabled
1: Enabled
Default: 0010 0000B
0x3A1
Bits
7-4
3-2
Luma Peaking Range Control
Name
YCORING[3:0]
YGAIN[1:0]
1-0
YFREQ[1:0]
Default: 0000 0000B
Description
To control Luma Signal throshold ( coring )
Luma Gain range control
Y peaking : 1/2 , 1, 2 , 4
To control Luma freq range .
0x3A2
Chroma Peaking Range Control
Bits
Name
7-4
CCORING[3:0]
3-2
CGAIN[1:0]
1-0
CFREQ[1:0]
Default: 0000 0000B
Description
To control Chroma Signal throshold .
To control Chroma Gain range .
To control Chroma freq range .
0x3A3
Text Enhance Control
Bits
7-0
Name
LUM_NOISE_THD[7:0]
R/W
R/W
R/W
Description
Luminace Noise Threshold
Recommended value to 20h (10 bits)
Default: 0010 0000B
0x3A4
Bits
7
6-4
1-0
Text Enhance Control
Name
DOUBLE_TEXT_ENHANCE
LUMA_GAIN
CHROMA_THD[1:0]
R/W
Description
Text Enhance double effect
Luminance gain level
Chrominance Threshold Level, higher level enhances more
color pixels
00: 128
01: 256
10: 512
11: 1024
Default: XXXX XX11B
0x3A5~0x3AF : Reserved
8.32. ACE Control
0x3B0
Bits
7
6
5
ACE Function Control
Name
NON_LINEAR_MODE
DATA_PORT_SEL[1]
2008-05-05
R/W
Description
Reserved
Enable non-linear histogram mode ( Only support BF1 )
Data port access selection, This bit setting will reference to
Reg. 0x3B1[4], {3B0[5], 3B1[4]}
145
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
4
HIST_MODE
3-2
ACE_MODE[1:0]
1
BF1_I-GAMMA_EN
0
BF2_I-GAMMA_EN
00 : histogram read,
01 : I-Gamma curve R/W
1x : Non-linear histogram point R/W
0: Mode 0 , pixel number accumulation mode .
1: Mode 1 ,frame number accumulation mode .
00: 4 area histogram / I – Gamma curve .
01: 8 area histogram / I – Gamma curve .
10: 16 area histogram / I – Gamma curve .
11: Reserved
BF1 , I-Gamma function
0: Disable
1: Enable
BF2 , I-Gamma function
0: Disable
1: Enable
Default: 0000 0000B
0x3B1
ACE Function Control
Bits
7
6
Name
I-GAMMA_UPDATE
I-GAMMA_RW
5
WINSEL
4
DATA_PORT_SEL
3-1
0
FRAME_MODE[2:0]
HIST_EN/HIST_RDY
R/W
Description
1: for update I-Gamma curve data .
0: Read I-Gamma curve .
1: Write I-Gamma curve .
0 : For BF1 access .
1 : For BF2 access .
If reg. 0x3B0[5] set to 0
1: for I-Gamma curve R/W, 0: for histogram read.
If reg. 0x3B0[5] set to 1, the data port will access Non-linear
histogram point R/W
000 ~ 111: for 1 to 255 frame calculation .
0: Histogram Read ready
1: Enable histogram
Default: 0000 0000B
Histogram read : 4 or 8 or 16 area pixel counts in entire frame , if HIST_MODE set “0”
Histogram read : 4 or 8 or 16 area over threshold frame counts in 256 frame , if HIST_MODE set “1”
0x3B2
ACE R/W Data port
Bits
Name
7-0
DATA_PORT[7:0]
Default: 0000 0000B
Description
Ace r/w data port[7:0]
0x3B3
Frame mode threshold – Low Byte
Bits
Name
7-0
FRAME_THRESHOLD[7:0]
Default: 0000 0000B
Description
Mode 1 threshold [7:0]
0x3B4
Frame mode threshold – Mid Byte
Bits
7-0
Name
FRAME_THRESHOLD[15:8]
2008-05-05
R/W
R/W
R/W
Description
Mode 1 threshold [15:8]
146
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Default: 0000 0000B
0x3B5
Frame mode threshold – High Byte
R/W
Bits
Name
Description
7-0
FRAME_THRESHOLD[23:16] Mode 1 threshold[23:16]
Default: 0000 0000B
0x3B6~0x3BF : Reserved
8.33. Color Management
0x3C0
Bits
7
CM Color Adjustment Control
R/W
Name
CM_UPDATE_FLAG
Description
The status of updating new coefficients to controller right after any
write to brightness, contrast, intensity, hue, and saturation. This flag is
read-only bit.
0: Done
1: Busy
6
CM_BRIGHT_EN
Brightness Adjust Function Enable, update adjustment in Vsync
0: Disable
1: Enable
5
CM_CONTRAST_EN Contrast Adjust Function Enable, update adjustment in Vsync
0: Disable
1: Enable
4
CM_HUE_EN
Hue Adjust Function Enable, update adjustment in Vsync
0: Disable
1: Enable
3
CM_SATURATION_EN Saturation Adjust Function Enable, update adjustment in Vsync
0: Disable
1: Enable
2
CM_INTENSITY_EN
Intensity Adjust Function Enable, update adjustment in Vsync
0: Disable
1: Enable
1-0
Reserved
Default: 0000 0000B
0x3C1
Bits
7-0
CM Brightness coefficient for Red
Name
CM_BRIGHTNESS_R
R/W
Description
This parameter is active when CM_BRIGHT_EN is active. The value is
from –128 to 127 in 2’s complement, power on default is 0.
R Display color = (Original value * Contrast coef.) + Brightness coef.
Default: 0000 0000B
0x3C2
Bits
7-0
CM Brightness coefficient for Green
Name
CM_BRIGHTNESS_G
R/W
Description
This parameter is active when CM_BRIGHT_EN is active. The value is
from –128 to 127 in 2’s complement, power on default is 0.
G Display color = (Original value * Contrast coef.) + Brightness coef.
Default: 0000 0000B
0x3C3
Bits
CM Brightness coefficient for Blue
Name
2008-05-05
R/W
Description
147
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
7-0
CM_BRIGHTNESS_B
This parameter is active when CM_BRIGHT_EN is active. The value is
from –128 to 127 in 2’s complement, power on default is 0.
B Display color = (Original value * Contrast coef.) + Brightness coef.
Default: 0000 0000B
0x3C4
Bits
7-0
CM Contrast Ratio coefficient for R
Name
CM_CONTRAST_R
R/W
Description
This parameter is active when CM_CONTRAST_EN is active. The
value is from 0(00 h) to2 (FF h), power on default is 1 (80h)..
Default: 1000 0000B
0x3C5
Bits
7-0
CM Contrast Ratio coefficient for G
Name
CM_CONTRAST_G
R/W
Description
This parameter is active when CM_CONTRAST_EN is active. The
value is from 0(00 h) to2 (FF h), power on default is 1 (80h).
Default: 1000 0000B
0x3C6
Bits
7-0
CM Contrast Ratio coefficient for B
Name
CM_CONTRAST_B
R/W
Description
This parameter is active when CM_CONTRAST_EN is active. The
value is from 0(00 h) to2 (FF h), power on default is 1 (80h).
Default: 1000 0000B
0x3C7
Bits
7-0
CM Hue coefficient
Name
CM_HUE
R/W
Description
This parameter is active when CM_HUE_EN is active. The value is
from 00h to 7Fh, one step means 180/128 degree. Bit 7 is sign bit:
0: clockwise (negative rotation),
1: counterclockwise (positive rotation)
Default: 0000 0000B
0x3C8
Bits
7-0
CM Hue coefficient
Name
CM_SATURATION
R/W
Description
This parameter is active when CM_SATURATION_EN is active. The
value is from 00 h to FF h.
Default: 1000 0000B
0x3C9
Bits
7-0
CM Hue coefficient
Name
CM_INTENSITY
R/W
Description
This parameter is active when CM_INTENSITY_EN is active. The
value is from 00 h to FF h. (0~2)
Default: 1000 0000B
0x3CA~0x3CB : Reserved
0x3CC
Bits
7
CM Color Enhancement Configuration
Name
HH_MAP_EN
2008-05-05
R/W
Description
Hue-Hue map
0: disable
1: enable
148
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
6
HS_MAP_EN
5
SS_MAP_EN
4-2
1
MAP_LOAD_EN
0
CM_CE_EN
Hue-Saturation map
0: disable
1: enable
Saturation-Saturation map
0: disable
1: enable
Reserved
Mapping table load enable
0: Disable
1: enable
CM Color Enhancement enable ,
0: Disable
1: Enable
Default: 0000 0000B
0x3CD
Bits
7-2
1-0
CM Index Access Port Control
Name
R/W
Description
Reserved
Table Select:
00: no access,
01: Hue-Hue Table,
10: Hue-Saturation Table
11: Saturation-Saturation Table
CM_INDEX_SEL
Default: 0000 0000B
0x3CE
Bits
7-5
4-0
CM Index Access Port Address
Name
CM_INDEX_ ADDR
R/W
Description
Reserved
Table Address:
Hue-Hue address: 0~23 (24 entries), each step means 15 degree
Hue-Saturation address: 0~23 (24 entries), each step means 15
degree
Saturation-Saturation address: 0~16 (17 entries), each step means
1/16 full saturation scale
Default: 0000 0010B
0x3CF
Bits
7-0
CM Index Access Port
R/W
Name
CM_INDEX_PORT
Description
Hue-Hue Data Port:
The value is from 00h to 7Fh, one step means 30/128 degree.
Bit 7: 0 is clockwise, 1 is counterclockwise. Power on default is 00h.
Hue-Saturation Data Port:
The value is from 00h to FFh. (0~2). Power on default is 80h (1).
Saturation-Saturation Data Port:
The value is from 00 h to FF h. (0~1). Power on default is FFh (1).
Default: 0000 0000B(HH), 1000 0000B(HS),1111 1111B(SS)
0x3D0~0x3FE : Reserved
0x3FF
Bits
Accessing Register Page Enable
Name
2008-05-05
R/W
Description
149
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
7-2
1-0
Reserved
REG_PAGE_SEL Register Page Enable
000: Enable register Page0.
001: Enable register Page1.
010: Enable register Page2.
011: Enable register Page3.
100: Enable register Page4.
Default: 0000 0000B
0x400~0x42F : Reserved
8.34. DBC
0x430
DBC Control
Bits
7-4
Name
ABRUPT_THD[3:0]
3
ABRUPT_EN
2
DBC_DITH_EN
1
DBC_DATA_EN
0
DBC_BL_CON_EN
R/W
Description
When Abrupt_Change_Enable =1, if the differences of the current and
previous frame statistics are bigger than Abrupt_TH*16, it will
considered as un-stable immediately.
Abrupt_Change_Enable:
1: Abrupt Change function enabele
0: Abrupt Change function disabled
DBC_dither_enable:
1: DBC dither is disabled.
0: DBC dither is disabled
Modify RGB value according to PWM value
1: Enable Modification
0: Disable (No Change)
Dynamic Backlight Control Enable (PIN Selection by REG0EE[5])
1:Enable
0:Disable
Default: 1111 0100B
0x431
DBC Adjust
Bits
7-4
Name
DUTY_ADJ_RATE
3-0
DUTY_ADJ_STEP
R/W
Description
Dynamic backlight control adjustment rate. PWM and color values will
adjusted according to frame statistics at every (Adjust_Rate+1) stable
frames
PWM duty adjustment step size: the maximum step size when adjust
the PWM duty at the adjust frame rate
Default: 1000 0011B
0x432
Bits
7-0
PWM Min
Name
DBC_PWM_MIN
R/W
Description
The lower bond of PWM duty cycle. No matter how PWM duty is
modified according to frame statistics. The duty cycle will never lower
than PWM_min/256. PWM_min must be no smaller than 8’h40.
Default: 1000 0000B
0x433
Bits
PWM Divider 1
Name
2008-05-05
R/W
Description
150
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
DBC_PWM_DUTY_MSB Used to add , 0/4, 1/4, 2/4,3/4 with duty[7:0]/1024
[1:0]
5
DBC_PWM_POL
PWM polarity control
1: Invert
0: Normal
4
REG_VSYNC_MODE
Load PWM control register on display Vsync leading edge
3-0
DBC_PWM_DIV1
First divider-- PWM clock divide of the selected clock by
0000 = 1; 0001 = 2; 0010 = 4; 0011 = 8; 0100 = 16; 0101 = 32;0110
= 64; 0111 = 128; 1000 = 256; 1001 = 512;1010 = 1024; 1011 = 2048;
1100 = 4096; 1101 = 8192; 1110 = 16384;11=16384;
Default: 0000 0111B
7-6
0x434
PWM Divider 2
Bits
Name
7-0
DBC_PWM_DIV2
Default: 0101 0100B
Description
DBC PWM period counter value. 1~256
0x435
PWM Divider 2
Bits
7-0
Name
DBC_PWM_DUTY
[7:0]
Default: 1111 1111B
Description
DBC PWM Duty.
0.39% ~ 100% , (PWMB_DUTY[7:0] + 1)/256x100%
0x436
DBC PWM Control
Bits
7
6
5
4
Name
DBC_PWM_EN
PWMA (PWM0)
PWMB (PWM1)
AVE_SAVING_MODE
3-0
ALLOW_DISTORT
R/W
R/W
R/W
Description
DBC PWM function enable
DBC PWM function apply to PWMA
DBC PWM function apply to PWMB
When AVE_Saving_Mode=1, the power saving ratio is determined by
average and maximum color in the frame
When DISTORT is not “00”, the color value of “255-DISTORTX2” to
255 might to mapping to the same value
Default: 0000 0000B
0x437
PWM Offset
Bits
Name
7-0
PWM_OFFSET
Default: XXXX XXXXB
Description
DBC PWM offset control
0x438
Y AVE
Bits
7-0
Name
Y_AVEARGE
R
R
Description
The average value of luminance of the current frame. It is updated
every frame and used for image stable criterion
Default: XXXX XXXXB
0x439
Effective Color Value
Bits
Name
7-0
EFFE_COLOR
Default: XXXX XXXXB
Description
Effective color value for DBC control
2008-05-05
151
R
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
0x43A
RGB Compensator Value
Bits
Name
7-0
RGB_COMPEN[7:0]
Default: XXXX XXXXB
Description
RGB compensator
0x43B
PWM ACT
Bits
7-0
Name
PWM_ACT[7:0]
R
R
Description
It is the final duty cycle value of PWM after dynamic backlight control.
In fact PWM_act = PWM_set * max_color/256
Default: 0000 0000B
0x43E
DBC Index Port Control
Bits
7-6
5-4
Name
DBC_TABLE_SEL
3-1
0
PORT_RW
R/W
Description
Reserved
00: None
01: Y gray to Lightness mapping table
10: PWM to Lightness mapping table
11: PWM ration to Multiplier mapping table
Reserved
Port Read/Write
0: Write
1: Read
Default: 0000 0000B
0x43F
DBC Index Data Port
Bits
Name
7-0
PORT_DATA[7:0]
Default: 0000 0000B
Description
DBC Table R/W Data port [7:0]
R/W
0x440 ~ 0x4FE: Reserved Register
0x4FF
Bits
7-3
2-0
Accessing Register Page Enable
Name
REG_PAGE_SEL
2008-05-05
R/W
Description
Reserved
Register Page Enable
000: Enable register Page0.
001: Enable register Page1.
010: Enable register Page2.
011: Enable register Page3.
100: Enable register Page4.
152
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
9.
Ordering Information
Order Code
Package
Note
NT68667FG
NT68667HFG
NT68667UFG
QFP 128L
QFP 128L
QFP 128L
Pb Free
Pb Free
Pb Free
2008-05-05
153
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
Package Information
D
D1
102
B
65
WITH PLATING
103
64
C
128
E
E1
BASE METAL
DETAIL A
0~8 degree (4x)
39
G
GAGE PLANE
e
B
38
G
0~8 degree (4x)
SEE DETAIL "F"
L
L1
0.25MM
1
A1
A
A2
DETAIL F
0.10 y
SEATING PLANE
DETAIL "A"
QFP 128L Outline Dimensions
unit: inches/mm
Dimensions in
Dimensions in mm
Symbol inches
Min Nom Max Min Nom Max
A
--- 0.134 --3.40
A1
0.010 --0.25
--A2
0.101 0.112 0.117 2.57 2.85 2.97
B
0.005 0.009 0.011 0.13 0.22 0.27
C
0.004 -- 0.008 0.09
-0.20
D
0.906 0.913 0.921 23.00 23.20 23.40
D1
0.783 0.787 0.791 19.90 20.00 20.10
E
0.669 0.667 0.685 17.00 17.20 17.40
E1
0.547 0.551 0.555 13.90 14.00 14.10
e
0.020 BSC
0.5 BSC
L
0.029 0.035 0.041 0.73 0.88 1.03
L1
0.063 BSC
1.60 BSC
Y
--- 0.004 --0.10
0°
-7°
0°
-7°
Notes: 1.Dimensions D & E do not include resin fins.
2.Dimensions F, GD & GE are for PC Board surface mount pad pitch design reference only
2008-05-05
154
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.
NT68667H/ NT68667 Scaler
1 Trail : 66 pcs
1 Box : 10 Trail
1 Carton : 6 Box
2008-05-05
155
Ver. 1.5
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness
for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.