NVP2010 Data Sheet CCD Image Signal Processor Information contained here is subject to change without notice. Make sure to check and use an updated version of the Data Sheet. www.nextchip.com 2007.03.12 REV 0.0 N V P 2010 CCD Image Signal Processor CCD Image Signal Processor NVP2010 outputs CVBS or S-Video after receiving CFA patterns from the color-interlaced CCD, which are processed through an internal encoder and DAC. Equipped with built-in AE/AWB algorithms, timing generation module, NVP2010 can be operated without MICOM. NVP2010 can support high resolution output of 520 TV lines and has enhanced BLC function and motion detection function in 64 areas. Ordering Information Features -. Input : NTSC/PAL, 510H/760H CCD format -. output : NTSC/PAL Analog S-Video or CVBS Device Package Temperature Range NVP2010 -. 3-line color processing -. Programmable GAMMA processing -. H/V Aperture 64-LQFP 0 ~ 70 Applications CONFIDENTIAL -. Video adjustment (brightness, contrast, saturation and hue) -. CCD Camera -. High quality color processing -. Door Phone Camera -. Horizontal MIRROR -. Blemish Compensation 32 points(Manual) -. color rolling suppress. -. Breathing suppress. -. Support Horizontal Resolution 520TV Lines -. Motion detection (64 area) -. On-chip AE/AWB -. Video Phone Camera -. CCD : SONY, SHARP , PANASONIC CCD -. On-chip CCD timing generator -. AFE : AD9806,AD9943 (Analog Device) -. On-chip NTSC/PAL video encoder -. On-chip DAC(S-video or CVBS) -. V-Driver : NVD2014 (NEXTCHIP) -. Rear-view Monitoring Camera Related Products SWITRON (510H/760H) 2 -. I C interface for EEPROM (MICOM less camera) -. Serial interface for AFE -. 3.3V operation Functional Block Diagram Data sheet 03.12.2007 (REV 0.0) 2/40 N V P 2010 CCD Image Signal Processor [[ Table of Contents ]] 1. Pin Information .......................................................................................................................................... 4 1.1 Pin Assignments ............................................................................................................................4 1.2 Pin Description ...............................................................................................................................5 2. Register Description ...................................................................................................................................... 7 2.1 Register map...................................................................................................................................7 2.1 Register Description ......................................................................................................................15 3. Electrical characteristics ............................................................................................................................... 35 3.1 Absolute Maximum Ratings ..........................................................................................................35 3.2 Recommended Operating Condition ............................................................................................35 3.3 DC Characteristics .........................................................................................................................35 CONFIDENTIAL 4. System Application ........................................................................................................................................36 4.1 Circuit Guide ..................................................................................................................................36 4.2 Package Information ......................................................................................................................39 5. Revision History ...........................................................................................................................................40 6. Contact Information ........................................................................................................................................40 SWITRON Data sheet 03.12.2007 (REV 0.0) 3/40 N V P 2010 1. CCD Image Signal Processor Pin Information SHD SHP VDD3 ADCLK VSS CFAIN[0] CFAIN[1] CFAIN[2] CFAIN[3] CFAIN[4] CFAIN[5] CFAIN[6] CFAIN[7] CFAIN[8] CFAIN[9] VSSUB 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VSS 1 48 VREF VDD5 2 47 IREF H2 3 46 COMP H1 4 45 VSSA XRG 5 VSS 6 VDD3 7 VDD3 CONFIDENTIAL 44 AVDD3 43 DAC2 42 VSSA 8 41 AVDD3 VSS 9 40 DAC1 VDDi 10 39 VDD3 XSUB 11 38 VDDi V2 12 37 RSTB 36 EXP_I_3 XSG1 14 35 EXP_I_2 V3 15 34 EXP_I_1 XSG2 16 33 VSS SWITRON NVP2010 LQFP64 Data sheet 03.12.2007 (REV 0.0) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AFE_SCL AFE_SDA AFE_SLD EXP_IO_1 EXP_IO_2 EXP_IO_3 VDD3 XTALI XTALO VSS VSS EXP_IO_4 I2C_SCL I2C_SDA TST0 V1 13 V4 . 64 1.1 Pin Assignments 4/40 N V P 2010 CCD Image Signal Processor 1.2 Pin Description PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SYMBOL I/O DESCRIPTION VSS VDD5 H2 H1 XRG VSS VDD3 VDD3 VSS VDDi XSUB V2 V1 XSG1 V3 XSG2 V4 AFE_SCL AFE_SDA AFE_SLD EXP_IO_1 EXP_IO_2 EXP_IO_3 VDD3 XTALI XTALO VSS VSS EXP_IO_4 I2C_SCL I2C_SDA TST0 VSS EXP_I_1 EXP_I_2 EXP_I_3 RSTB VDDi VDD3 DAC1 AVDD3 VSSA DAC2 AVDD3 G P O O O G P P G P O O O O O O O O I/O O I/O I/O I/O P I O G G I/O I/O I/O I G I I I I P P O P G O P Digital Ground (for SHP, SHD) 5V Digital Power (for XRG, H1, H2 pulse) CCD Horizontal Driving pulse 2 CCD Horizontal Driving pulse 1 CCD Reset gate pulse Digital Ground (for XRG, H1, H2 pulse) 3.3V Digital Power 3.3V Digital Power Digital Ground 1.8V Internal Core Power(Connect to VSS via external capacitor) CCD shutter speed control pulse CCD vertical driving pulse phase-2 CCD vertical driving pulse phase-1 CCD Read out pulse 1 CCD vertical driving pulse phase-3 CCD Read out pulse 2 CCD vertical driving pulse phase-4 3-wire Serial interface clock output (for AFE control) 3-wire Serial data input/output (for AFE control) 3-wire Serial Enable output (for AFE control) External input/output control Pin External input/output control Pin External input/output control Pin 3.3V Digital Power X-tal input(NTSC:28.6363MHz : PAL:28.375MHz) X-tal output Digital Ground Digital Ground External input/output control Pin I2C Serial Clock (EEPROM/MICOM interface) I2C Serial Data (EEPROM/MICOM interface) Chip Test pin Digital Ground External input control Pin External input control Pin External input control Pin System Reset (active low) 1.8V Internal Core Power(Connect to VSS via external capacitor) 3.3V Digital Power DAC Output (LUMA/CHROMA/CVBS/IRIS/GND signal Output) 3.3V DAC Analog Power DAC Analog Ground DAC Output (LUMA/CHROMA/CVBS/IRIS/GND signal Output) 3.3V DAC Analog Power CONFIDENTIAL Data sheet 03.12.2007 (REV 0.0) SWITRON 5/40 N V P 2010 PIN NO. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 CCD Image Signal Processor SYMBOL I/O DESCRIPTION VSSA COMP IREF VREF VSSUB CFAIN[9] CFAIN[8] CFAIN[7] CFAIN[6] CFAIN[5] CFAIN[4] CFAIN[3] CFAIN[2] CFAIN[1] CFAIN[0] VSS ADCLK VDD3 SHP SHD G G I I I I I I I I I I G O P O O DAC Analog Ground DAC comparator reference DAC current reference DAC Voltage reference DAC Analog Ground CCD CFA pattern input 9 CCD CFA pattern input 8 CCD CFA pattern input 7 CCD CFA pattern input 6 CCD CFA pattern input 5 CCD CFA pattern input 4 CCD CFA pattern input 3 CCD CFA pattern input 2 CCD CFA pattern input 1 CCD CFA pattern input 0 Digital Ground ADC sampling clock 3.3V Digital Power (for SHP, SHD) CDS sample & hold pulse for pre-charge CDS sample & hold pulse for data CONFIDENTIAL SWITRON Data sheet 03.12.2007 (REV 0.0) 6/40 N V P 2010 CCD Image Signal Processor 2. Register Information 2.1 Register Map BANK 0 ADDR ISP 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E EEPROM 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 RESISTER [7] [6] [5] [4] [3] [2] [1] [0] DEF. 0xAA 0x55 0xAA 0x55 H1_P H2_P SHP_P SHD_P RG_P ADCLK_P XSUB_P PBLK_P CLPOB_P CLPDM_P NTSC HIGH CCD_TYPE[1:0] 1'b0 SEL_27M H1_HW H2_HW H1_DELAY[5:0] H2_DELAY[5:0] SHP_DELAY[5:0] SHD_DELAY[5:0] RG_DELAY[5:0] ADCLK_DELAY[5:0] H1_WIDTH[2:0] H2_WIDTH[2:0] SHD_WIDTH[2:0] SHP_WIDTH[2:0] SHP_HW SHD_HW RG_HW RG_WIDTH[2:0] AFE_00[15:8] AFE_00[07:0] AFE_01[15:8] AFE_01[07:0] AFE_02[15:8] AFE_02[07:0] AFE_03[15:8] AFE_03[07:0] AFE_04[15:8] AFE_04[07:0] PGA_LENGTH[2:0] PGA_DUMMY[1:0] PGA_LOC[2:0] CLAMP AFE_PCON PGA_ADDR[5:0] CLAMP_REG[4:0] DAY_IR_P CLAMP_LEVEL[1:0] H_OFFSET SHPD_TYPE HP_DLL_EN BPF_SEL[1:0] H_SIZE[3:0] Y_GAIN H_EDGE_OFF Y_CLIP[6:0] 1'b0 DAY_EX[1:0] 1'b0 MIRROR_POS[3:0] Y_GAMMA0 Y_GAMMA1 Y_GAMMA2 Y_GAMMA3 Y_GAMMA4 Y_GAMMA5 Y_GAMMA6 Y_GAMMA7 HAP_SLICE1[3:0] HAP_SLICE2[3:0] VAP_SLICE[3:0] VAP_GAIN[3:0] 8‘b0 PEAK_GAIN[2:0] HAP_GAIN1[4:0] 1'b0 1'b0 1'b0 HAP_GAIN2[4:0] BF_DLY[3:0] PEAK_SLICE[3:0] SUE_AGC_LEVEL SUC_AGC_GAIN[3:0] SUE_AGC_GAIN[3:0] SUC_AGC_LEVEL SUC_HL_HLEVEL[3:0] SUC_HL_LLEVEL[3:0] SUC_HL_GAIN[3:0] SUC_EDGE_GAIN[3:0] C_GAMMA0 CONFIDENTIAL Data sheet 03.12.2007 (REV 0.0) SWITRON 0x00 0x00 0x00 0x00 0x00 0x80 0x00 0x00 0x00 0x00 0x20 0x82 0x00 0x40 0x00 0xC0 0x00 0x00 0x00 0x04 0x70 0x43 0x40 0x80 0x4C 0xB1 0x00 0x01 0x10 0x25 0x41 0x68 0x9E 0xE7 0xFF 0x45 0x45 0x00 0x0A 0x09 0x63 0x22 0x28 0x30 0x90 0x31 0x01 7/40 N V P 2010 CCD Image Signal Processor BANK 0 ADDR ISP 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 EEPROM 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A RESISTER [7] [6] [5] [4] [3] [2] [1] [0] C_GAMMA1 C_GAMMA2 C_GAMMA3 C_GAMMA4 C_GAMMA5 C_GAMMA6 C_GAMMA7 GAIN_RS1 GAIN_RS2 GAIN_BS1 GAIN_BS2 CCY_GAIN CCR_GAIN CCB_GAIN 1'b0 CFIR_SEL CCRB_ID S1_ID TEST_PATTERN[1:0] YFIR_SEL[1:0] CLP_RS1[5:0] CLP_RS2[5:0] CLP_BS1[5:0] CLP_BS2[5:0] CONFIDENTIAL CCORR CCORG CCORB CCOGR CCOGG CCOGB CCOBR CCOBG CCOBB RWB GWB BWB RBLK GBLK BBLK CR_GAIN CB_GAIN HUE1 HUE2 HUE3 HUE4 HUE5 HUE6 UV_GAIN1 UV_GAIN2 UV_GAIN3 UV_GAIN4 UV_GAIN5 UV_GAIN6 SWITRON BLC BLC_AREA_VIEW MOTION_AGC[3:0] DAY_EXT_IN_P Data sheet 03.12.2007 (REV 0.0) 1'b0 1'b0 ESS_ZONE[3:0] BLC_GAIN[5:0] MOTION_HIGH[3:0] AE_LEVEL BLC_LEVEL MOTION_THL IRIS_LG_ON 1'b0 MAX1_AGC MAX2_AGC IRIS_DAC_PORT 1'b0 AED_ZONE[3:0] 1'b0 DEF. 0x10 0x25 0x41 0x68 0x9E 0xE7 0xFF 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x3F 0xBF 0xFF 0x3F 0xA0 0x2E 0x4E 0x6C 0x87 0xAC 0xC6 0x52 0xC4 0x5A 0x4A 0x51 0x00 0x00 0x00 0x80 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x80 0x80 0x80 0x80 0x80 0x95 0x40 0x54 0x40 0x0F 0x08 0xD0 0x00 0x75 8/40 N V P 2010 CCD Image Signal Processor BANK 0 ADDR ISP 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E EEPROM 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 RESISTER [7] [6] [5] [4] [3] [2] [1] [0] ESS_SDLY[3:0] AGC_SDLY[3:0] AE_DG_REG[9:8] AGC_REG[9:8] AE_SPD[3:0] AE_DG_REG[7:0] AGC_REG[7:0] MOTION_TEST AE_MODE[1:0] SSM[2:0] IRIS_LENS[1:0] BTN_REPT_ON 1'b0 1'b0 ME_ESS[12:8] ME_ESS[7:0] R_MAX B_MAX R_MIN B_MIN AWB_HIGH AWB_MODE[1:0] AWB_DIP[1:0] 1'b0 1'b0 1'b0 1'b0 AWB_LOW R_CLP[3:0] B_CLP[3:0] INTVAL_H[3:0] INTVAL_L[3:0] AWB_SPD[3:0] STA_ZONE[3:0] STA_IN_LMT[3:0] STA_OUT_LMT[3:0] 8'b0 AWB_R0 AWB_R1 AWB_R2 AWB_R3 AWB_B0 AWB_B1 AWB_B2 AWB_B3 AWB_R_OFFSET AWB_B_OFFSET DAY_NIGHT_START DAY_NIGHT_END DAY_ON[1:0] DAY_DLY[5:0] SEL_EXPO_02[3:0] SEL_EXPO_01[3:0] SEL_EXPO_04[3:0] SEL_EXPO_03[3:0] 8'b0 1'b0 1'b0 1'b0 SC_OFFSET[4:0] DAY_EXT_IN_REG DEF_M_SEL[4:0] 1'b0 1'b0 HXV_OFFSET PRE_Y_GAIN EDGE_S[3:0] EDGE_E[3:0] DAY_BURST_ON MOTION_EN M_VIEW_ON 1'b0 1'b0 1'b0 1'b0 1'b0 CONFIDENTIAL Data sheet 03.12.2007 (REV 0.0) SWITRON Fix '1'b0' DEF. 0x00 0x4F 0x00 0x00 0x42 0x80 0x15 0x8D 0x43 0x64 0xCB 0xF0 0x40 0x07 0xFF 0x44 0xF4 0x11 0x00 0x40 0x04 0x6D 0x42 0x40 0x00 0xEE 0x3C 0x10 0x08 0xC3 0x97 0x41 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x02 0x50 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 9/40 N V P 2010 CCD Image Signal Processor BANK 0 ADDR ISP 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0XB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0XC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 EEPROM 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA RESISTER [7] [6] [5] [4] [3] [2] [1] [0] 8'b0 POWER_FRE [1:0] IRIS_P MOTION_TH_AREA[3:0] HVAP_GAIN[4:0] SEL_IRIS_LENS[3:0] 8'b0 MIRROR M_CURSOR_ON BTN_DLY U_BURST[9:8] V_BURST[9:8] IRIS_DC[1:0] DAC1_OUT[3:0] M_CURSOR[5:0] AWB_M_R AWB_M_B IRIS_LEVEL IRIS_GAIN 1'b0 1'b0 1'b0 1'b0 Y_OFFSET SYNC_REG[5:0] BLACK_REG[5:0] U_BURST[7:0] V_BURST[7:0] IRIS_BLC_OFFSET[4:0] DAC_P DAC2_OUT[3:0] MOTION_TH SLPF_SEL AE_OUT_LMT[2:0] MOTION_AREA[63:56] MOTION_AREA[55:48] MOTION_AREA[47:40] MOTION_AREA[39:32] MOTION_AREA[31:24] MOTION_AREA[23:16] MOTION_AREA[15:8] MOTION_AREA[7:0] BLC_AREA_SEL[63:56] BLC_AREA_SEL[55:48] BLC_AREA_SEL[47:40] BLC_AREA_SEL[39:32] BLC_AREA_SEL[31:24] BLC_AREA_SEL[23:16] BLC_AREA_SEL[15:8] BLC_AREA_SEL[7:0] SEL_MIRROR[3:0] SEL_AGC[3:0] SEL_AE0[3:0] SEL_SSM0[3:0] SEL_SSM2[3:0] IRIS_GMIN[3:0] IR_GAIN[7:0] CONFIDENTIAL Data sheet 03.12.2007 (REV 0.0) MOTION_THF[3:0] SWITRON SEL_DAY_EXT[3:0] SEL_BLC[3:0] SEL_AE1[3:0] SEL_SSM1[3:0] 4'b0 IRIS_GMAX[3:0] Fix '1'b0' DEF. 0x00 0x50 0x00 0x00 0x00 0x40 0x40 0x40 0x80 0x50 0x00 0xCE 0x15 0x9F 0x00 0x09 0x00 0x22 0x08 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 10/40 N V P 2010 CCD Image Signal Processor BANK 0 ADDR ISP 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA EEPROM 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE RESISTER [7] [6] [5] [4] [3] [2] [1] [0] Fix '1'b0' 1'b0 1'b0 DAY_PULSE_SEL[1:0] 1'b0 1'b0 1'b0 1'b0 BLK_TH[1:0] NEGATIVE_IMG BLK_GAIN[1:0] HPF_SEL HAP_CLIP1[1:0] 1'b0 VAP_CLIP[1:0] AWB_AE_DETECT AWB_METHOD1[1:0] AWB_TR_CLIP AWB_METHOD2[1:0] AWB_METHOD3 AE_GMAX[1:0] HAP_SUP_SEL 1'b0 1'b0 1'b0 1'b0 1'b0 AFE_DAC2_ON 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 Y_CLIP_TH[1:0] MOTION_DELAY[1:0] 1'b0 CLPOB_SIZE[3:0] MAX_AGC_SEL DAY_MOTOR_P Fix '1'b0' CONFIDENTIAL CLPOB_POS[3:0] Fix '1'b0' SWITRON AFE_DAC1_ON IRIS_AFE_DC INIT_SCR ADC_SET bank_reg SLAVE_ADDR[3:0] Fix '1'b0' SD_H1[1:0] SD_RG[1:0] Data sheet 03.12.2007 (REV 0.0) test1 SL_H1 SL_RG SD_H2[1:0] DAC1_SL DAC2_SL 1'b0 SL_H2 HAP_SUPPRESS[4:0] 1'b0 1'b0 DEF. 0x00 0x00 0x00 0x00 0x00 0x80 0x80 0x00 0x00 0x00 0xE0 0x60 0x80 0xF0 0x40 0x20 0x00 0x00 0x00 0x00 0x80 0x88 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x18 0x00 0x00 11/40 N V P 2010 CCD Image Signal Processor BANK 1 ADDR ISP 0x01 0x02 0x03 0x04 0x05 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A EEPROM 0x01 0x02 0x03 0x04 0x05 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A RESISTER [7] [6] [5] [4] [3] [2] [1] [0] 8'b0 COMPEN_START 1'b0 Fix '1'b0' DEF_V_00[9:8] DEF_H_00[9:8] DEF_H_01[9:8] DEF_H_02[9:8] DEF_H_03[9:8] DEF_V_04[9:8] DEFECT_MANUAL 1'b0 DEF_V_01[9:8] DEF_V_02[9:8] DEF_H_00[7:0] DEF_V_00[7:0] DEF_D_00[5:0] DEF_H_01[7:0] DEF_V_01[7:0] DEF_D_01[5:0] DEF_H_02[7:0] DEF_V_02[7:0] DEF_D_02[5:0] DEF_H_03[7:0] DEF_V_03[7:0] DEF_D_03[5:0] DEF_V_05[9:8] DEF_V_06[9:8] DEF_H_04[7:0] DEF_V_04[7:0] DEF_D_04[5:0] DEF_H_05[7:0] DEF_V_05[7:0] DEF_D_05[5:0] DEF_H_06[7:0] DEF_V_06[7:0] DEF_D_06[5:0] DEF_H_07[7:0] DEF_V_07[7:0] DEF_D_07[5:0] DEF_V_09[9:8] DEF_V_10[9:8] DEF_H_08[7:0] DEF_V_08[7:0] DEF_D_08[5:0] DEF_H_09[7:0] DEF_V_09[7:0] DEF_D_09[5:0] DEF_H_10[7:0] DEF_V_10[7:0] DEF_D_10[5:0] DEF_H_11[7:0] DEF_V_11[7:0] DEF_D_11[5:0] DEF_V_13[9:8] DEF_V_14[9:8] DEF_H_12[7:0] DEF_V_12[7:0] DEF_D_12[5:0] DEF_H_13[7:0] DEF_V_13[7:0] DEF_D_13[5:0] DEF_H_14[7:0] DEF_V_14[7:0] DEF_D_14[5:0] DEF_H_15[7:0] DEF_V_15[7:0] 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 DEF_V_03[9:8] CONFIDENTIAL DEF_H_04[9:8] DEF_H_05[9:8] DEF_V_07[9:8] SWITRON DEF_H_06[9:8] DEF_H_07[9:8] DEF_V_08[9:8] DEF_H_08[9:8] DEF_H_09[9:8] DEF_H_10[9:8] DEF_H_11[9:8] DEF_V_12[9:8] DEF_H_12[9:8] DEF_H_13[9:8] DEF_H_14[9:8] Data sheet 03.12.2007 (REV 0.0) DEF_V_11[9:8] DEF_V_15[9:8] DEF. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 12/40 N V P 2010 CCD Image Signal Processor BANK 1 ADDR ISP EEPROM 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x72 RESISTER [7] [6] [5] [4] [3] [2] [1] DEF_H_15[9:8] DEF_V_16[9:8] [0] DEF_D_15[5:0] DEF_V_17[9:8] DEF_V_18[9:8] DEF_V_19[9:8] DEF_H_16[7:0] DEF_V_16[7:0] DEF_H_16[9:8] DEF_D_16[5:0] DEF_H_17[7:0] DEF_V_17[7:0] DEF_H_17[9:8] DEF_D_17[5:0] DEF_H_18[7:0] DEF_V_18[7:0] DEF_H_18[9:8] DEF_D_18[5:0] DEF_H_19[7:0] DEF_V_19[7:0] DEF_H_19[9:8] DEF_D_19[5:0] DEF_V_20[9:8] DEF_V_21[9:8] DEF_V_22[9:8] DEF_V_23[9:8] DEF_H_20[7:0] DEF_V_20[7:0] DEF_H_20[9:8] DEF_D_20[5:0] DEF_H_21[7:0] DEF_V_21[7:0] DEF_H_21[9:8] DEF_D_21[5:0] DEF_H_22[7:0] DEF_V_22[7:0] DEF_H_22[9:8] DEF_D_22[5:0] DEF_H_23[7:0] DEF_V_23[7:0] DEF_H_23[9:8] DEF_D_23[5:0] DEF_V_24[9:8] DEF_V_25[9:8] DEF_V_26[9:8] DEF_V_27[9:8] DEF_H_24[7:0] DEF_V_24[7:0] DEF_H_24[9:8] DEF_D_24[5:0] DEF_H_25[7:0] DEF_V_25[7:0] DEF_H_25[9:8] DEF_D_25[5:0] DEF_H_26[7:0] DEF_V_26[7:0] DEF_H_26[9:8] DEF_D_26[5:0] DEF_H_27[7:0] DEF_V_27[7:0] DEF_H_27[9:8] DEF_D_27[5:0] DEF_V_28[9:8] DEF_V_29[9:8] DEF_V_30[9:8] DEF_V_31[9:8] DEF_H_28[7:0] DEF_V_28[7:0] DEF_H_28[9:8] DEF_D_28[5:0] DEF_H_29[7:0] DEF_V_29[7:0] DEF_H_29[9:8] DEF_D_29[5:0] DEF_H_30[7:0] DEF_V_30[7:0] DEF_H_30[9:8] DEF_D_30[5:0] DEF_H_31[7:0] DEF_V_31[7:0] DEF_H_31[9:8] DEF_D_31[5:0] AED_SPD V_OFFSET[2:0] 1'b0 1'b0 1'b0 1'b0 SEL_IRISL[3:0] SEL_IRISR[3:0] CONFIDENTIAL SWITRON 1'b0 Data sheet 03.12.2007 (REV 0.0) 1'b0 1'b0 1'b0 SEL_MOTION[3:0] DEF. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x00 0x00 13/40 N V P 2010 CCD Image Signal Processor Read only register BANK 0x81 ADDR ISP RESISTER [7] 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D [6] [5] [4] [3] [2] [1] ACC_BLC_MSB ACC_BLC_LSB ACC_NBLC_MSB ACC_NBLC_LSB AE_ES_MSB AE_ES_LSB AGC AE_DIGT_GAIN AE_ACC AWB_R AWB_B AWB_TARGET_R AWB_TARGET_B [0] DEF. - CONFIDENTIAL SWITRON Data sheet 03.12.2007 (REV 0.0) 14/40 N V P 2010 CCD Image Signal Processor 2.2 Register Explanation ADDR 0x00 0x01 0x02 0x03 0x04 0x05 bit NAME [7] H1_P [6] H2_P [5:0] H1_DELAY [7] SHP_P [6] SHD_P [5:0] H2_DELAY [7] RG_P [6] ADCLK_P ㆍ ㆍ ㆍ ㆍ ㆍ ㆍ ㆍ BANK 0 DESCRIPTION H1 pulse phase change 0 : Normal 1: change H2 pulse phase change 0 : Normal 1: change H1 pulse delay adjustment range : 0 ~ 63ns SHP pulse phase change ㆍ 0 : Normal 1: change ㆍ SHD pulse phase change ㆍ 0 : Normal 1: change ㆍ H2 pulse delay adjustment SHP_DELAY [7] XSUB_P [6] PBLK_P [5:0] SHD_DELAY [7] CLPOB_P [6] CLPDM_P [5:0] RG_DELAY [7] NTSC [6] HIGH [5:0] ADCLK_DELAY [7:6] CCD_TYPE 0x06 [5:3] H1_WIDTH [2:0] H2_WIDTH Data sheet 03.12.2007 (REV 0.0) R/W 0x00 R/W 0x00 ㆍ range : 0 ~ 63ns ㆍ RG pulse phase change ㆍ 0 : Normal 1: change ㆍ ADCLK pulse phase change CONFIDENTIAL [5:0] status default ㆍ 0 : Normal 1: change ㆍ SHP pulse delay adjustment R/W 0x00 ㆍ range : 0 ~ 63ns ㆍ XSUB pulse phase change ㆍ 0 : Normal 1: change ㆍ PBLK pulse phase change SWITRON ㆍ 0 : Normal 1: change ㆍ SHD pulse delay adjustment R/W 0x00 ㆍ range : 0 ~ 63ns ㆍ CLPOB pulse phase change ㆍ 0 : Normal 1: change ㆍ CLPDM pulse phase change ㆍ 0 : Normal 1: change ㆍ XRG pulse delay adjustment R/W 0x00 ㆍ range : 0 ~ 63ns ㆍ NTSC ㆍ 0 : PAL 1: NTSC ㆍ CCD resolution selection ㆍ 0 : NORMAL(270K) 1 : HI8(410K) ㆍ ADCLK pulse delay adjustment R/W 0x80 ㆍ range : 0 ~ 63ns ㆍ CCD type selection ㆍ 0: SONY 1 : SHARP 2: PANASONIC ㆍ H1 pulse width adjustment. ㆍ range : 0 ~ 7ns ㆍ H2 pulse width adjustment. R/W 0x00 ㆍ range : 0 ~ 7ns 15/40 N V P 2010 ADDR 0x07 CCD Image Signal Processor BANK 0 DESCRIPTION bit NAME [7] Fix [6] SEL_27M [5:3] SHD_WIDTH ㆍ SHD pulse width adjustment (0 ~ 7ns) [2:0] SHP_WIDTH ㆍ SHP pulse width adjustment (0 ~ 7ns) [7] H1_HW ㆍ Select H1 pulse width (0: High band 1: Low band ) [6] H2_HW ㆍ Select H2 pulse width (0: High band 1: Low band ) [5] SHP_HW ㆍ Select SHP pulse width ( 0: High band 1: Low band ) [4] SHD_HW ㆍ Select SHD pulse width ( 0: High band 1: Low band ) [3] RG_HW ㆍ Select RG pulse width ( 0: High band 1: Low band ) 0x08 [2:0] 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 RG_WIDTH AFE_00[15:8] AFE_00[07:0] AFE_01[15:8] AFE_01[07:0] AFE_02[15:8] AFE_02[07:0] AFE_03[15:8] AFE_03[07:0] AFE_04[15:8] AFE_04[07:0] status default ㆍ Fix at 1'b0. ㆍ System clock selection ㆍ 0 : CCD(NTSC :28.6363MHz or PAL :28.375MHz) 1 : 27MHz R/W 0x00 R/W 0x00 ㆍ RG pulse width adjustment (0 ~ 7ns) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ㆍ 1st AFE internal setting register CONFIDENTIAL ㆍ 2nd AFE internal setting register ㆍ 3rd AFE internal setting register ㆍ 4th AFE internal setting register SWITRON ㆍ 5th AFE internal setting register 0x00 0x20 0x82 0x00 0x40 0x00 0xC0 0x00 0x00 0x00 [2:0] PGA_LENGTH ㆍ Select PGA length. 0x13 [1:0] 0x14 PGA_DUMMY [2:0] PGA_LOC [7] CLAMP ㆍ Fill 1 or 2 bits if PGA is not 10 bits. ㆍ Change address order of PGA. ㆍ Auto Clamp On/Off ㆍ 0 : OFF 1 : ON R/W 0x70 [6] AFE_PCON ㆍ Change the bit order of PGA. [5:0] PGA_ADDR ㆍ Assign PGA address to each address. R/W PGA_LOC=0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 PGA_LOC=1 AD0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 PGA_LOC=2 AD0 AD1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 PGA_LOC=3 AD0 AD1 AD2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 PGA_LOC=4 AD0 AD1 AD2 AD3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 PGA_LOC=5 AD0 AD1 AD2 AD3 AD4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 AD5 PGA_LOC=6 AD0 AD1 AD2 AD3 AD4 AD5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 * AD0 = PGA_ADDR[0], AD3 = PGA_ADDR[3], Data sheet 03.12.2007 (REV 0.0) R/W 0x04 AD1 = PGA_ADDR[1], AD4 = PGA_ADDR[4], AD0 AD1 AD2 AD3 AD4 AD5 AD1 AD2 AD3 AD4 AD5 AD2 AD3 AD4 AD5 AD3 AD4 AD5 AD4 AD5 AD2 = PGA_ADDR[2] AD5 = PGA_ADDR[5] 16/40 N V P 2010 ADDR 0x15 bit CCD Image Signal Processor BANK 0 DESCRIPTION NAME [7:3] CLAMP_REG [2] DAY_IR_P status default ㆍ Manual clamp value ㆍ Apply clamp with CLAMP_REG value if Auto Clamp is off. ㆍ Day&Night output pulse phase change ㆍ 0 : Normal R/W 0x43 1 : Change [1:0] CLAMP_LEVEL ㆍ Set the weight of clamp value if Auto clamp is on. 0x16 [7:0] H_OFFSET [7:6] BPF_SEL [5] SHPD_TYPE 0x17 [4:1] [0] 0x18 [7:0] [7] 0x19 [6:0] [7] H_SIZE HP_DLL_EN Y_GAIN ㆍ Modify horizontal timing. (default : 0x00) R/W 0x40 ㆍ range : -128 ~ 127 ㆍ Band pass filter selection ㆍ Set the relation between SHP, SHD pulse and H1 pulse R/W 0x80 ㆍ Encoder horizontal active size control ㆍ Pulse delay method selection ㆍ 0 : DELAY CELL 1 : ANALOG DLL ㆍ Second Y gain ㆍ Range : x0 ~ x2 CONFIDENTIAL H_EDGE_OFF Y_CLIP R/W 0x4C ㆍ Remove Edge on right and left side of the screen. ㆍ 0 : Edge On 1: Edge Off R/W 0xB1 ㆍ Assign maximal Y value for output ㆍ Fix at 1'b0. Fix SWITRON ㆍ Select criteria for the control of day & night in the Day&Night function [6:5] DAY_EX ㆍ 0 : Internal (Only AGC) 0x1A 1 : External CDS input 2 : External CDS input + AGC [4] R/W 0x00 ㆍ Fix at 1'b0. Fix [3:0] MIRROR_POS ㆍ Horizontal position setting at time of mirror screen 0x1B [7:0] Y_GAMMA0 ㆍ 1st Y GAMMA value R/W 0x01 0x1C [7:0] Y_GAMMA1 ㆍ 2nd Y GAMMA vaue R/W 0x10 0x1D [7:0] Y_GAMMA2 ㆍ 3 rd Y GAMMA vlue R/W 0x25 0x1E [7:0] Y_GAMMA3 ㆍ 4 th Y GAMMA vlue R/W 0x41 0x1F [7:0] Y_GAMMA4 ㆍ 5 th Y GAMMA vlue R/W 0x68 ㆍ 6 th Y GAMMA vlue R/W 0x9E Y GAMMA vlue R/W 0xE7 Y GAMMA vlue R/W 0xFF 0x20 [7:0] Y_GAMMA5 0x21 [7:0] Y_GAMMA6 ㆍ 7 th 0x22 [7:0] Y_GAMMA7 ㆍ 8 th O U TP U T GAM M A7 GAM M A6 GAM M A5 GAM M A4 GAM M A3 GAM M A2 GAMM A1 GAMM A0 IN P U T Data sheet 03.12.2007 (REV 0.0) 17/40 N V P 2010 ADDR 0x23 0x24 bit CCD Image Signal Processor HAP_SLICE1 [3:0] HAP_SLICE2 ㆍ High-frequency bandwidth horizontal aperture slice [7:4] VAP_SLICE ㆍ Vertical aperture slice [3:0] VAP_GAIN [7:5] PEAK_GAIN [4:0] HAP_GAIN1 [7:5] Fix [4:0] HAP_GAIN2 [7:4] BF_DLY 0x27 [3:0] 0x29 [7:0] SUE_AGC_LEVEL 0x2A ㆍ Standard of the size of the edge that could become an aperture ㆍ Vertical aperture gain 0x2D R/W 0x45 ㆍ Peaking filter gain ㆍ Range : x0 ~ x4 ㆍ Low-frequency bandwidth horizontal aperture gain R/W 0x0A ㆍ Range : x0 ~ x4 ㆍ Fix at 1'b0. ㆍ High-frequency bandwidth horizontal aperture gain R/W 0x09 ㆍ Range : x0 ~ x4 ㆍ Adjust BURST position ㆍ Peaking slice. ㆍ Set AGC level for the start of edge suppress in low illumination ㆍ If AGC value is above the value set, edge suppress will be applied. [7:4] SUC_AGC_GAIN ㆍ Set ratio for color suppress in low illumination. [3:0] SUE_AGC_GAIN ㆍ Set ratio for edge suppress in low illumination. SWITRON 0x2B [7:0] SUC_AGC_LEVEL ㆍ Set AGC level for the start of color suppress in low illumination 0x2C R/W 0x45 ㆍ Range : x0 ~ x2 CONFIDENTIAL PEAK_SLICE status default ㆍ Low-frequency bandwidth horizontal aperture slice [7:4] 0x26 0x28 BANK 0 DESCRIPTION NAME [7:4] SUC_HL_HLEVEL ㆍ Set Y level for the start of highlight color suppress (bright range) [3:0] SUC_HL_LLEVEL ㆍ Set Y level for the start of highlight color suppress (dark range) [7:4] SUC_HL_GAIN ㆍ Set ratio for highlight color suppress. [3:0] SUC_EDGE_GAIN ㆍ Set ratio for the suppression of color component at edge. R/W 0x63 R/W 0x22 R/W 0x28 R/W 0x30 R/W 0x90 R/W 0x31 0x2E [7:0] C_GAMMA0 ㆍ 1st C GAMMA value 0x2F [7:0] C_GAMMA1 ㆍ 2 nd C GAMMA value R/W 0x10 ㆍ 3 rd C GAMMA value R/W 0x25 0x30 [7:0] C_GAMMA2 R/W 0x01 0x31 [7:0] C_GAMMA3 ㆍ 4 th C GAMMA value R/W 0x41 0x32 [7:0] C_GAMMA4 ㆍ 5 th C GAMMA value R/W 0x68 ㆍ 6 th C GAMMA value R/W 0x9E th 0x33 [7:0] C_GAMMA5 0x34 [7:0] C_GAMMA6 ㆍ 7 C GAMMA value R/W 0xE7 0x35 [7:0] C_GAMMA7 ㆍ 8th C GAMMA value R/W 0xFF 0x36 [7:0] GAIN_RS1 0x37 [7:0] GAIN_RS2 0x38 [7:0] GAIN_BS1 0x39 [7:0] GAIN_BS2 Data sheet 03.12.2007 (REV 0.0) ㆍ CCR = s2*GAIN_RS2-s1*GAIN_RS1 ㆍ Range : x0 ~ x2 ㆍ CCR = s2*GAIN_RS2-s1*GAIN_RS1 ㆍ Range : x0 ~ x2 ㆍ CCB = s1*GAIN_BS1-s2*GAIN_BS2 ㆍ Range : x0 ~ x2 ㆍ CCB = s1*GAIN_BS1-s2*GAIN_BS2 ㆍ Range : x0 ~ x2 R/W 0x80 R/W 0x80 R/W 0x80 R/W 0x80 18/40 N V P 2010 ADDR bit CCD Image Signal Processor 0x3A [7:0] CCY_GAIN 0x3B [7:0] CCR_GAIN 0x3C [7:0] CCB_GAIN 0x3D 0x3E 0x3F ㆍ CCY gain ㆍ CCR gain R/W 0x80 ㆍ Range : x0 ~ x4 ㆍ CCB gain R/W 0x80 ㆍ Range : x0 ~ x4 ㆍ Fix at 1'b0. Fix [6] CFIR_SEL ㆍ LPF selection on CHROMA path [5:0] CLP_RS1 ㆍ Clip of GAIN_RS1*s1 [7] CCRB_ID ㆍ Switch CCR and CCB lines at time of color calculation. [6] S1_ID [5:0] CLP_RS2 [7:6] TEST_PATTERN [7:6] [5:0] ㆍ Switch S1 and S2. R/W 0xBF ㆍ Internal test pattern selection ㆍ 0 ~ 2 : Internal test Pattern 3 : CCD Input. CONFIDENTIAL ㆍ Clip of GAIN_BS1*s1 YFIR_SEL ㆍ LPF selection on LUMA path CLP_BS2 ㆍ Clip of GAIN_BS2*s2 CCORR 0x42 [7:0] CCORG 0x43 [7:0] CCORB 0x44 [7:0] CCOGR 0x45 [7:0] CCOGG 0x46 [7:0] CCOGB 0x47 [7:0] CCOBR 0x48 [7:0] CCOBG 0x49 [7:0] CCOBB 0x4A [7:0] RWB 0x4B [7:0] GWB 0x4C [7:0] BWB 0x4D [7:0] RBLK Data sheet 03.12.2007 (REV 0.0) R/W 0x3F ㆍ CLIP of GAIN_RS2*s2 CLP_BS1 0x41 [7:0] status default R/W 0x80 ㆍ Range : x0 ~ x2 [7] [5:0] 0x40 BANK 0 DESCRIPTION NAME ㆍ R' = CCR*CCORR+CCY*CCORG+CCB*CCORB ㆍ Gain range : x0(0x00) ~ x2(0xFF) SWITRON ㆍ R' = CCR*CCORR+CCY*CCORG+CCB*CCORB ㆍ Gain range : -x0.5 ~ x0.5 (2's complement) ㆍ R' = CCR*CCORR+CCY*CCORG+CCB*CCORB ㆍ Gain range : -x0.5 ~ x0.5 (2's complement) ㆍ G' = CCY*CCOGG-(CCR*CCOGR+CCB*CCOGB) ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ G' = CCY*CCOGG-(CCR*CCOGR+CCB*CCOGB) ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ G' = CCY*CCOGG-(CCR*CCOGR+CCB*CCOGB) ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ B' = CCR*CCOBR+CCY*CCOBG+CCB*CCOBB ㆍ Gain range : -x0.5 ~ -x0.5 (2's complement) ㆍ B' = CCR*CCOBR+CCY*CCOBG+CCB*CCOBB ㆍ Gain range : -x0.5 ~ -x0.5 (2's complement) ㆍ B' = CCR*CCOBR+CCY*CCOBG+CCB*CCOBB ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ RED gain ㆍ Gain range : x0(0x00) ~ x4(0xFF) ㆍ GREEN gain ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ BLUE gain ㆍ Gain range : x0(0x00) ~ x4(0xFF) ㆍ RED offset ㆍ Gain range : -128 ~ 127 (2's complement) R/W 0xFF R/W 0x3F R/W 0xA0 R/W 0x2E R/W 0x4E R/W 0x6C R/W 0x87 R/W 0xAC R/W 0xC6 R/W 0x52 R/W 0xC4 R/W 0x5A R/W 0x4A R/W 0x51 R/W 0x00 19/40 N V P 2010 ADDR bit CCD Image Signal Processor 0x4E [7:0] GBLK 0x4F [7:0] BBLK 0x50 [7:0] CR_GAIN 0x51 [7:0] CB_GAIN 0x52 [7:0] HUE1 0x53 [7:0] HUE2 0x54 [7:0] HUE3 0x55 [7:0] 0x56 [7:0] BANK 0 DESCRIPTION NAME ㆍ GREEN offset ㆍ Gain range : -128 ~ 127 (2's complement) ㆍ BLUE offset ㆍ Gain range : -128 ~ 127 (2's complement) ㆍ CR GAIN ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ CB GAIN ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ 1 st area HUE control ㆍ Data range : -45° ~ 45° (2's complement) ㆍ 2 nd area HUE control ㆍ Data range : -45° ~ 45° (2's complement) ㆍ 3rd area HUE control ㆍ Data range : -45° ~ 45° (2's complement) CONFIDENTIAL HUE4 HUE5 0x57 [7:0] HUE6 0x58 [7:0] UV_GAIN1 0x59 [7:0] UV_GAIN2 0x5A [7:0] UV_GAIN3 0x5B [7:0] UV_GAIN4 0x5C [7:0] UV_GAIN5 0x5D [7:0] UV_GAIN6 ㆍ 4th area HUE control ㆍ Data range : -45° ~ 45° (2's complement) ㆍ 5th area HUE control ㆍ Data range : -45° ~ 45° (2's complement) ㆍ 6th area HUE control ㆍ Data range : -45° ~ 45° (2's complement) SWITRON ㆍ 1st area UV gain ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ 2nd area UV gain ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ 3 rd area UV gain ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ 4 th area UV gain ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ 5 th area UV gain ㆍ Gain range : x0(0x00) ~ x2(0xFF) ㆍ 6 th area UV gain ㆍ Gain range : x0(0x00) ~ x2(0xFF) status default R/W 0x00 R/W 0x00 R/W 0x80 R/W 0x80 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x80 R/W 0x80 R/W 0x80 R/W 0x80 R/W 0x80 R/W 0x80 E Area 2 Area 1 Area 3 Area 6 Area 4 Area 5 Data sheet 03.12.2007 (REV 0.0) 20/40 N V P 2010 ADDR 0x5E CCD Image Signal Processor bit NAME [7] BLC [6] BLC_AREA_VIEW [5:0] BLC_GAIN BANK 0 DESCRIPTION ㆍ BLC(Back Light Compensation) On/Off ㆍ 0 : OFF 1 : ON ㆍ BLC AREA VIEW On/Off ㆍ 0 : OFF status default R/W 0x95 1 : ON ㆍ Adjust ratio of screen brightness in the BLC area ㆍ Apply different motion threshold values for low illumination and [7:4] MOTION_AGC 0x5F [3:0] MOTION_HIGH general conditions so that motion can be detected. ㆍ Set the criteria of low illumination for motion detection. ㆍ Motion detection is not to be performed when the screen is as 0x60 [7:0] AE_LEVEL bright as it is set in the MOTION_HIGH or brighter ㆍ Standard value for Auto Exposure when BLC is OFF 0x61 [7:0] BLC_LEVEL ㆍ Standard value for Auto Exposure when BLC is ON 0x62 [7:0] MOTION_THL ㆍ Low luminous motion threshold value [7] DAY_EXT_IN_P [6:4] Fix 0x63 [3] [2] R/W 0x54 R/W 0x40 R/W 0x0F ㆍ Day&Night external input pulse phase change ㆍ 0 : Normal 1 : Change CONFIDENTIAL IRIS_LG_ON R/W 0x40 ㆍ Fix at 1'b0. ㆍ Select the iris level ㆍ 0 : IRIS_LEVEL R/W 0x08 1 : IRIS_LEVEL*gain IRIS_DAC_PORT ㆍ Set DAC sleep mode register assign Fix ㆍ Fix at 1'b0. 0x64 [7:0] MAX1_AGC ㆍ MAX AGC1 R/W 0xD0 0x65 [7:0] MAX2_AGC ㆍ MAX AGC2 R/W 0x00 [7:4] ESS_ZONE ㆍ Electronic shutter stable zone [3:0] AED_ZONE ㆍ Digital gain stable zone [7:4] ESS_SDLY [3:0] AGC_SDLY ㆍ Delay time from when the AGC is operated until the electronic shutter works ㆍ Delay time from when the electronic shutter is operated until the AGC [1:0] 0x66 0x67 SWITRON R/W 0x75 R/W 0x00 functions [7:6] AE_DG_REG[9:8] ㆍ Manual digital gain MSB[9:8] 0x68 [5:4] AGC_REG[9:8] ㆍ Manual AGC MSB[9:0] [3:0] AE_SPD ㆍ AE speed control R/W 0x4F ㆍ 0 : slow ~ 7 : fast 0x69 [7:0] AE_DG_REG[7:0] ㆍ Manual digital gain LSB[7:0] R/W 0x00 0x6A [7:0] AGC_REG[7:0] ㆍ Manual AGC LSB[7:0] R/W 0x00 Data sheet 03.12.2007 (REV 0.0) 21/40 N V P 2010 ADDR bit [7:6] CCD Image Signal Processor BANK 0 DESCRIPTION NAME AE_MODE status default ㆍ AE Mode selection ㆍ 0 : Fixed(SSM) 1 : Auto 2 : Manual(256 steps) 3 : Manual ㆍ Output predefined values of the electronic shutter. [5:3] SSM 0x6B [2] MOTION_TEST [1:0] IRIS_LENS [7] 0x6C [6:5] [4:0] SSM 0 1 2 3 4 5 6 7 NTSC 1/60 1/100 1/250 1/500 1/2,000 1/5,000 1/10,000 1/100,000 PAL 1/50 1/120 1/250 1/500 1/2,000 1/5,000 1/10,000 1/100,000 R/W 0x42 ㆍ Motion area view On/Off ㆍ 0 : OFF 1 : ON ㆍ IRIS output type selection ㆍ 0 : VIDEO 1 : DC else : Manual CONFIDENTIAL BTN_REPT_ON ㆍ Select whether the button remained pressed is recognized as successive entry Fix ㆍ Fix at 1'b0. R/W 0x80 ME_ESS[12:8] ㆍ Manual ess value[12:8] (It functions only when the AE_MODE value is 3) ㆍ Manual ess value[7:0] R/W 0x15 R_MAX ㆍ Set Maximal RED value in color temperature R/W 0x8D 0x6F [7:0] B_MAX ㆍ Set Maximal BLUE value in color temperature R/W 0x43 0x70 [7:0] R_MIN ㆍ Set Minimal RED value in color temperature R/W 0x64 0x71 [7:0] B_MIN ㆍ Set Minimal BLUE value in color temperature R/W 0xCB 0x72 [7:0] AWB_HIGH ㆍ Maximal Y value for the operation of AWB R/W 0xF0 0x6D [7:0] ME_ESS[7:0] 0x6E [7:0] 0x73 [7:6] AWB_MODE [5:4] AWB_DIP [3:0] Fix 0x74 [7:0] 0x75 0x76 0x77 AWB_LOW SWITRON ㆍ AWB / ATW / DIP mode selection ㆍ 0 : AWB 1 : ATW 2: DIP 3 : MANUAL ㆍ Select four color temperature predefined. ㆍ Fix at 1'b0. ㆍ Minimal Y value required for the operation of AWB [7:4] R_CLP ㆍ CLIP maximal RED value in AWB tracking area. [3:0] B_CLP ㆍ CLIP maximal BLUE value in AWB tracking area. [7:4] [3:0] INTVAL_H INTVAL_L [7:4] AWB_SPD [3:0] STA_ZONE ㆍ Set the size of stabilization zone at time of AWB tracking. ㆍ If the time in the STA_ZONE is higher than the value set [7:4] STA_IN_LMT when the AWB Tracking pointer is inside the STA_ZONE, no more 0x78 [3:0] STA_OUT_LMT Data sheet 03.12.2007 (REV 0.0) R/W 0x40 ㆍ Set the size of upper section in the AWB tracking area. ㆍ Set the size of lower section in the AWB tracking area. ㆍ AWB tracking speed ㆍ 0x00(slow) ~ 0x0F(fast) AWB Tracking is to done. ㆍ Tracking is to done when white continues to exist in the area R/W 0x07 R/W 0xFF R/W 0x44 R/W 0xF4 R/W 0x11 outside the STA_ZONE for a period longer than what is set. 22/40 N V P 2010 CCD Image Signal Processor ADDR bit 0x7A [7:0] NAME AWB_R0 BANK 0 DESCRIPTION ㆍ DIP_MODE == 0, AWB RED gain status default 0x7B [7:0] AWB_R1 ㆍ DIP_MODE == 1, AWB RED gain R/W 0x04 0x7C [7:0] AWB_R2 ㆍ DIP_MODE == 2, AWB RED gain R/W 0x6D 0x7D [7:0] AWB_R3 ㆍ DIP_MODE == 3, AWB RED gain R/W 0x42 0x7E [7:0] AWB_B0 ㆍ DIP_MODE == 0, AWB BLUE gain R/W 0x40 0x7F [7:0] AWB_B1 ㆍ DIP_MODE == 1, AWB BLUE gain R/W 0x00 0x80 [7:0] AWB_B2 ㆍ DIP_MODE == 2, AWB BLUE gain R/W 0xEE 0x81 [7:0] AWB_B3 ㆍ DIP_MODE == 3, AWB BLUE gain R/W 0x3C 0x82 [7:0] AWB_R_OFFSET 0x83 [7:0] AWB_B_OFFSET 0x84 [7:0] DAY_NIGHT_START R/W 0x40 ㆍ AWB RED offset ㆍ Data range : -128 ~ 127 (2's complements) ㆍ AWB BLUE offset ㆍ Data range : -128 ~ 127 (2's complements) ㆍ Set the brightness level where the DAY & NIGHT function starts to operate 0x85 [7:0] DAY_NIGHT_END ㆍ ㆍ [7:6] DAY_ON ㆍ 0x86 ㆍ [5:0] DAY_DLY ㆍ Set the brightness level where the DAY & NIGHT function stops operating CONFIDENTIAL 0x87 0x88 Delay time when the Day&Night function starts or stops [3:0] SEL_EXPO_01 ㆍ Assign an output pulse to the pin number 21 SWITRON [7:4] SEL_EXPO_04 ㆍ Assign an output pulse to the pin number 29 [3:0] SEL_EXPO_03 ㆍ Assign an output pulse to the pin number 23 2 : day IR 3 : power pulse 4 : motion detection 5 : IRIS_LENS[0] 6 : eeprom wr 7 : pblk 8 : clpdm 9 : clpob Fix [4:0] SC_OFFSET ㆍ Scaler offset(only 27MHz) [7:3] DEF_M_SEL ㆍ Manual defect point selection [2] Fix Fix HXV_OFFSET 0x8D [7:0] PRE_Y_GAiN R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 ㆍ Fix at 1'b0. ㆍ Modify the pulse timing (at 27MHz) ㆍ Range : -128 ~ 127 ㆍ First Y gain ㆍ Range : x0 ~ x2 [7:4] EDGE_S ㆍ Remove noise generated on the left side of video [3:0] EDGE_E ㆍ Remove noise generated on the right side of video Data sheet 03.12.2007 (REV 0.0) R/W 0x41 ㆍ Fix at 1'b0. [1] DAY_EXT_IN_REG ㆍ Day&Night external enable signal 0x8C [7:0] 0x8E ㆍ Fix at 1'b0. [7:5] [0] R/W 0x97 0 sec ~ 15 sec 1 : day motor 0x8B R/W 0xC3 0 : B/W, 1: Color 2 : Auto 0 : none. 0x8A R/W 0x08 Set Day&Night function [7:4] SEL_EXPO_02 ㆍ Assign an output pulse to the pin number 22 ※ output pulse R/W 0x10 R/W 0x00 R/W 0x80 R/W 0x02 23/40 N V P 2010 ADDR 0x8F BANK 0 DESCRIPTION bit NAME [7] Fix [6] MOTION_EN [5] M_VIEW_ON [4] 0xA0 CCD Image Signal Processor status default ㆍ Fix at 1'b0. ㆍ Motion detection On/Off ㆍ 0 : Off 1 : On ㆍ Motion view On/Off (Display the motion area on the screen.) ㆍ 0 : Motion view Off R/W 0x58 1 : Motion view On DAY_BURST_ON ㆍ BURST signal On/Off(Day&Night) ㆍ Fix at 1'b0. [3:0] Fix [7:6] POWER_FRE [5] IRIS_P [4:0] HVAP_GAIN ㆍ Adjust the frequency of the power pulse. ㆍ IRIS output phase change R/W 0x50 ㆍ 0 : Normal. 1 : Change. ㆍ Sharpness gain ㆍ Generate motion detection pulse when the number of areas where 0xA1 [7:4] MOTION_TH_AREA motions occur (out of 64 areas) is greater than what is set at R/W 0x00 MOTION_TH_AREA. [3:0] SEL_IRIS_LENS ㆍ Select the input pin for the IRIS_LENS signal [7] 0xA3 CONFIDENTIAL MIRROR [6] M_CURSOR_ON [5:0] M_CURSOR ㆍ MIRROR On/Off ㆍ Set the cursor On/Off indicating one of the 64 areas at time of setting the MOTION AREA ㆍ Set the cursor location indicating one of the 64 areas at time of R/W 0x00 setting the MOTION AREA SWITRON 0xA4 [7:0] AWB_M_R ㆍ AWB manual adjust RED gain R/W 0x40 0xA5 [7:0] AWB_M_B ㆍ AWB manual adjust BLUE gain R/W 0x40 0xA6 [7:0] IRIS_LEVEL ㆍ IRIS output level R/W 0x40 0xA7 [7:0] IRIS_GAIN ㆍ IRIS output gain R/W 0x80 [7:4] BTN_DLY ㆍ Button input delay [3:0] Fix 0xA8 0xA9 [7:0] 0xAA 0xAB [7:6] [5:0] R/W 0x05 ㆍ Fix at 1'b0. ㆍ Adjust the Y offset Y_OFFSET R/W 0x00 ㆍ Range : -128 ~ +127(2's complement) U_BURST[9:8] ㆍ U_BURST[9:8] value. SYNC_REG R/W 0xCE ㆍ Adjust the SYNC level of the video signal [7:6] V_BURST[9:8] ㆍ V_BURST[9:8] value. [5:0] BLACK_REG R/W 0x15 ㆍ Adjust the BLACK level of the video signal 0xAC [7:0] U_BURST[7:0] ㆍ Set the U_BURST value. R/W 0x9F 0xAD [7:0] V_BURST[7:0] ㆍ Set the V_BURST value. R/W 0x00 [7:6] 0xAE [5:1] ㆍ IRIS output selection IRIS_DC ㆍ 0 : VIDEO IRIS_BLC_OFFSET 1 : DC ㆍ Set the offset value at time of MANUAL IRIS output ㆍ DAC clock DAC_P [7:4] DAC1_OUT ㆍ DAC 1 output selection [3:0] DAC2_OUT ※ DAC output mode ㆍ DAC 2 output selection 0 : CVBS 1 : LUMA Data sheet 03.12.2007 (REV 0.0) ㆍ 0 : Normal 2 : CHROMA R/W 0x09 phase change [0] 0xAF else : MANUAL 3 : IRIS 1: Change R/W 0x00 4 : IRIS volume 5 : HIGH 6 : LOW 24/40 N V P 2010 ADDR bit 0xB0 [7:0] 0xB1 CCD Image Signal Processor NAME MOTION_TH [7:4] MOTION_THF [3] SLPF_SEL [2:0] AE_OUT_LMT BANK 0 DESCRIPTION ㆍ High luminous motion threshold value status default R/W 0x22 ㆍ Generate motion detection pulse when consecutive motions are detected as much as set at MOTION_THF or above. ㆍ Encoder sync low pass filter On/Off ㆍ 0 : Off 1 : On ㆍ Start to operate AE after a certain time set at AE_OUT_LMT has R/W 0x08 passed once the brightness of input screen changes 0xB2 [7:0] MOTION_AREA[63:56] R/W 0xFF 0xB3 [7:0] MOTION_AREA[55:48] R/W 0xFF 0xB4 [7:0] MOTION_AREA[47:40] R/W 0xFF 0xB5 [7:0] MOTION_AREA[39:32] 0xB6 [7:0] MOTION_AREA[31:24] 0xB7 [7:0] MOTION_AREA[23:16] R/W 0xFF 0xB8 [7:0] MOTION_AREA[15:8] R/W 0xFF 0xB9 [7:0] MOTION_AREA[7:0] R/W 0xFF ㆍ Set the MOTION area CONFIDENTIAL R/W 0xFF R/W 0xFF 0xBA [7:0] BLC_AREA[63:56] R/W 0xFF 0xBB [7:0] BLC_AREA[55:48] R/W 0xFF 0xBC [7:0] BLC_AREA[47:40] R/W 0xFF 0xBD [7:0] BLC_AREA[39:32] 0xBE [7:0] BLC_AREA[31:24] 0xBF [7:0] BLC_AREA[23:16] 0xC0 [7:0] BLC_AREA[15:8] 0xC1 [7:0] BLC_AREA[7:0] Data sheet 03.12.2007 (REV 0.0) ㆍ Set the BLC area SWITRON R/W 0xFF R/W 0xFF R/W 0xFF R/W 0xFF R/W 0xFF 25/40 N V P 2010 ADDR 0xC2 0xC3 0xC4 0xC5 0xC6 CCD Image Signal Processor BANK 0 bit NAME DESCRIPTION [7:4] SEL_DAY_EXT ㆍ Select the input pin for the Day&Night external signal [3:0] SEL_MIRROR ㆍ Select the input pin for the MIRROR control signal [7:4] SEL_BLC ㆍ Select the input pin for the BLC control signal [3:0] SEL_AGC ㆍ Select the input pin for the AGC control signal [7:4] SEL_AE1 ㆍ Select the input pin for the AE_MODE[1] signal [3:0] SEL_AE0 ㆍ Select the input pin for the AE_MODE[0] signal [7:4] SEL_SSM1 ㆍ Select the input pin for the SSM[1] signal [3:0] SEL_SSM0 ㆍ Select the input pin for the SSM[0] signal [7:4] Fix ㆍ Fix at 1'b0. ㆍ Select the input pin for the SSM[2] signal [3:0] SEL_SSM2 ※ selection input pin 0x0 : none 0x1 : #34 0x2 : #35 0x3 : #36 0x4 :not use [7] 0xDC [6:0] CONFIDENTIAL IR_GAIN[7:0] MAX_AGC_SEL Fix [7] DAY_MOTOR_P 0xDD [7] 0xDF [6:5] 0xE0 ㆍ Set the INFRARED gain value ㆍ 0 : MAX1_AGC 1 : MAX2_AGC SWITRON ㆍ 0 : Normal 1: Change ㆍ Day&Night output pulse type selection Fix ㆍ Fix at 1'b0. Fix [7] NEGATIVE_IMG [6:5] BLK_GAIN [4:0] Fix [7] 0xE1 [6:5] [4:0] [7] 0xE2 [6:5] [4:0] HPF_SEL HAP_CLIP1 ㆍ Black level horizontal aperture threshold ㆍ 0 : Off 1 : On ㆍ Black level horizontal aperture gain R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x80 R/W 0x00 R/W 0x00 ㆍ Fix at 1'b0. ㆍ High frequence horizontal aperture filter selection ㆍ Low frequence horizontal aperture clip ㆍ Fix at 1'b0. Fix ㆍ Fix at 1'b0. Fix R/W 0x00 ㆍ Fix at 1'b0. ㆍ Negative image On/Off Fix VAP_CLIP R/W 0x00 ㆍ Day&Night motor control pulse phase change ㆍ 0 : Maximum ~ 3 : Minimum ㆍ Fix at 1'b0. [4:0] R/W 0x00 ㆍ Fix at 1'b0. Fix BLK_TH R/W 0x00 ㆍ MAX_AGC selection [6:5] DAY_PULSE_SEL ㆍ Adjust the brightness of IR [4:0] R/W 0x00 0x5 :not use 0x6 :not use 0x7 :not use 0x8 :not use 0x9 : #21 0xA : #22 0xB : #23 0xC : #29 [7:4] IRIS_GMAX ㆍ Set the maximal value of IRIS_GAIN 0xC7 [3:0] IRIS_GMIN ㆍ Set the minimal value of IRIS_GAIN 0xC8 [7:0] status default ㆍ Vertical aperture clip R/W 0xE0 R/W 0x60 ㆍ Fix at 1'b0. ㆍ Set the point of starting AWB [7] AWB_AE_DETECT ㆍ 0 : Start AWB irrespective of AE 0xE3 1 : Start AWB once AE gets stabilized [6:5] AWB_METHOD1 ㆍ AWB method1 selection [4:0] Fix Data sheet 03.12.2007 (REV 0.0) R/W 0x80 ㆍ Fix at 1'b0. 26/40 N V P 2010 ADDR bit CCD Image Signal Processor BANK 0 DESCRIPTION NAME status default ㆍ Clip more than what is set as R_MAX/R_MIN, B_MAX/B_MIN in the [7] AWB_TR_CLIP AWB tracking area. ㆍ 0 : Clip Off 0xE4 1 : Clip On R/W 0xE0 [6:5] AWB_METHOD2 ㆍ AWB method2 selection [4:0] Fix ㆍ Fix at 1'b0. [7] AWB_METHOD3 ㆍ AWB method3 selection 0xE5 [6:5] AE_GMAX ㆍ AE digital gain maximum value selection [4:0] POS_CID ㆍ OSD menu [CAMERA ID] item position(*OSD MENU) [7:6] Fix 0xE6 [5] [4:0] [7] 0xE8 ㆍ Fix at 1'b0. HAP_SUP_SEL ㆍ Horizontal edge suppress mode selection Fix AFE_DAC2_ON ㆍ AFE DAC2 output On/Off R/W 0x00 Fix ㆍ Fix at 1'b0. [7] Fix ㆍ Fix at 1'b0. ㆍ Standards for processing when the output Y value is bigger than [4:0] R/W 0x20 ㆍ Fix at 1'b0. [6:0] 0xEA [6:5] R/W 0x4C CONFIDENTIAL Y_CLIP_TH Fix Y_CLIP. ㆍ 0 : clip 1: 1/8 ㆍ Fix at 1'b0. 2: 1/4 R/W 0x00 3 : 1/2 [7:6] MOTION_DELAY ㆍ Set the time for alarm signal of motion detection 0xEB 0xEC SWITRON ㆍ Fix at 1'b0. [5:0] Fix [7:4] CLPOB_SIZE ㆍ Set CLPOB pulse width [3:0] CLPOB_POS [7] AFE_DAC1_ON ㆍ Set CLPOB position ㆍ AFE DAC1 output On/Off [6] IRIS_AFE_DC R/W 0x80 R/W 0x88 ㆍ 0 : OFF 1 : ON ㆍ Set the AFE DAC1 output value ㆍ 0: Internal register (IRIS_GAIN) 1 : Iris out 0xF0 [5] INIT_SCR ㆍ Display initial screen (blue screen). 0 : Initial screen display Off R/W 0x05 1: Initial screen display On ㆍ Set the Internal register of AFE. [4] ADC_SET ㆍ The register saved at AFE_00 ~ AFE_03 is registered as the internal register of AFE when 0 is changed into 1. [3:0] 0xF1 [7:0] SLAVE_ADDR ㆍ Set I2C communication slave address bank_reg [7:3] test1 [2] DAC1_SL 0xF8 [1] DAC2_SL [0] Fix Data sheet 03.12.2007 (REV 0.0) ㆍ Set internal register bank R/W 0x00 ㆍ Test register ㆍ DAC1 sleep mode On/Off ㆍ 0 : Normal operation 1: Power down mode ㆍ DAC2 sleep mode On/Off ㆍ 0 : Normal operation R/W 0x18 1: Power down mode ㆍ Fix at 1'b0. 27/40 N V P 2010 ADDR bit NAME [7:6] SD_H1 [5] SL_H1 0xF9 [4:3] 0xFA CCD Image Signal Processor SD_H2 [2] Fix [1] SL_H2 [0] Fix [7:6] SD_RG [5] SL_RG BANK 0 DESCRIPTION ㆍ Driving option selection ㆍ 0 : 12mA 1 : 14mA ㆍ Slew rate selection status default 2 : 16mA 3 : 18mA 2 : 16mA 3 : 18mA 2 : 16mA 3 : 18mA ㆍ 0 : Fast 1 : Slow ㆍ Driving option selection ㆍ 0 : 12mA 1 : 14mA ㆍ Fix at 1'b0. ㆍ Slew rate selection R/W 0x00 ㆍ 0 : Fast 1 : Slow ㆍ Fix at 1'b0. ㆍ Driving option selection ㆍ 0 : 12mA 1 : 14mA ㆍ Slew rate selection R/W 0x00 ㆍ 0 : Fast 1 : Slow [4:0] HAP_SUPPRESS ㆍ Horizontal edge suppress CONFIDENTIAL SWITRON Data sheet 03.12.2007 (REV 0.0) 28/40 N V P 2010 ADDR bit CCD Image Signal Processor NAME 0x02 [7:0] COMPEN_START 0x04 [7:3] Fix [2] DEFECT_MANUAL [1:0] Fix BANK 1 DESCRIPTION ㆍ Starting point to correct a defect. ㆍ The higher the value, correction starts when the screen gets dark. ㆍ Manually search for defect. R/W 0x00 ㆍ Fix at 1'b0. st [5:4} DEF_V_01[9:8] ㆍ 2 nd Vertical defect position [3:2] DEF_V_02[9:8] ㆍ 3 rd Vertical defect position [1:0] DEF_V_03[9:8] ㆍ 4 th Vertical Defect Position 0x09 [7:0] DEF_H_00[7:0] ㆍ 1 st Horizontal defect position Vertical defect position 0x0A [7:0] DEF_V_00[7:0] ㆍ 1st Vertical defect position 0x0B R/W 0x0A ㆍ Fix at 1'b0. [7:6] DEF_V_00[9:8] ㆍ 1 0x08 status default [7:6] DEF_H_00[9:8] ㆍ 1 st Horizontal defect position [5:0] DEF_D_00[5:0] ㆍ 1st Defect value 0x0C [7:0] DEF_H_01[7:0] ㆍ 2nd Horizontal defect position CONFIDENTIAL R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 0x0D [7:0] DEF_V_01[7:0] ㆍ 2 nd Vertical defect position [7:6] DEF_H_01[9:8] ㆍ 2 nd Horizontal defect position [5:0] DEF_D_01[5:0] ㆍ 2 nd Defect value 0x0F [7:0] DEF_H_02[7:0] ㆍ 3 rd Horizontal defect position R/W 0x00 0x10 [7:0] DEF_H_02[7:0] ㆍ 3 rd Vertical defect position R/W 0x00 0x0E 0x11 SWITRON [7:6] DEF_H_02[9:8] ㆍ 3 rd Horizontal defect position [5:0] DEF_D_02[5:0] ㆍ 3 rd Defect value 0x12 [7:0] DEF_H_03[7:0] 0x13 [7:0] DEF_V_03[7:0] [7:6] DEF_H_03[9:8] 0x14 [5:0] DEF_D_03[5:0] [7:6] DEF_V_04[9:8] ㆍ ㆍ ㆍ ㆍ ㆍ 4th 4th th 4 4th th 5 Horizontal defect position Vertical defect position Horizontal defect position Defect value Vertical defect position R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 [5:4] DEF_V_05[9:8] ㆍ 6 th Vertical defect position [3:2] DEF_V_06[9:8] ㆍ 7 th Vertical defect position [1:0] DEF_V_07[9:8] ㆍ 8 th Vertical defect position 0x16 [7:0] DEF_H_04[7:0] ㆍ 5 th Horizontal defect position R/W 0x00 0x17 [7:0] DEF_V_04[7:0] ㆍ 5 th Vertical defect position R/W 0x00 [7:6] DEF_H_04[9:8] ㆍ 5 th Horizontal defect position [5:0] DEF_D_04[5:0] ㆍ 5 th Defect value 0x19 [7:0] DEF_H_05[7:0] ㆍ 6 th Horizontal defect position R/W 0x00 0x1A [7:0] DEF_V_05[7:0] ㆍ 6 th Vertical defect position R/W 0x00 0x15 0x18 0x1B [7:6] DEF_H_05[9:8] ㆍ 6th Horizontal defect position [5:0] DEF_D_05[5:0] ㆍ 6th Defect value R/W 0x00 R/W 0x00 R/W 0x00 0x1C [7:0] DEF_H_06[7:0] ㆍ 7th Horizontal defect position R/W 0x00 0x1D [7:0] DEF_H_06[7:0] ㆍ 7th Vertical defect position R/W 0x00 0x1E [7:6] DEF_H_06[9:8] ㆍ 7 th Horizontal defect position [5:0] DEF_D_06[5:0] ㆍ 7 th Defect value Data sheet 03.12.2007 (REV 0.0) R/W 0x00 29/40 N V P 2010 CCD Image Signal Processor BANK 1 ADDR bit NAME DESCRIPTION 0x1F [7:0] DEF_H_07[7:0] ㆍ 8th Horizontal defect position 0x20 [7:0] DEF_V_07[7:0] ㆍ 8 th Vertical defect position [7:6] DEF_H_07[9:8] ㆍ 8 th Horizontal defect position 0x21 [5:0] DEF_D_07[5:0] ㆍ 8th Defect value status default R/W 0x00 R/W 0x00 R/W 0x00 [7:6] DEF_V_08[9:8] ㆍ 9th Vertical defect position 0x22 [5:4} DEF_V_09[9:8] ㆍ 10th Vertical defect position [3:2] DEF_V_10[9:8] ㆍ 11 th Vertical defect position [1:0] DEF_V_11[9:8] ㆍ 12 th Vertical defect position R/W 0x00 0x23 [7:0] DEF_H_08[7:0] ㆍ 9 th Horizontal defect position R/W 0x00 0x24 [7:0] DEF_V_08[7:0] ㆍ 9 th Vertical defect position R/W 0x00 [7:6] DEF_H_08[9:8] ㆍ 9 th Horizontal defect position [5:0] DEF_D_08[5:0] ㆍ 9 th Defect value 0x25 0x26 [7:0] DEF_H_09[7:0] ㆍ 10th Horizontal defect position 0x27 [7:0] DEF_V_09[7:0] ㆍ 10 0x28 th Vertical defect position CONFIDENTIAL [7:6] DEF_H_09[9:8] ㆍ 10th Horizontal defect position [5:0] DEF_D_09[5:0] ㆍ 10th Defect value R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 0x29 [7:0] DEF_H_10[7:0] ㆍ 11th Horizontal defect position R/W 0x00 0x2A [7:0] DEF_H_10[7:0] ㆍ 11th Vertical defect position R/W 0x00 [7:6] DEF_H_10[9:8] ㆍ 11 th Horizontal defect position [5:0] DEF_D_10[5:0] ㆍ 11 th Defect value 0x2C [7:0] DEF_H_11[7:0] ㆍ 12 th Horizontal defect position R/W 0x00 0x2D [7:0] DEF_V_11[7:0] ㆍ 12 th Vertical defect position R/W 0x00 [7:6] DEF_H_11[9:8] ㆍ 12 th Horizontal defect position [5:0] DEF_D_11[5:0] ㆍ 12 th Defect value 0x2B 0x2E SWITRON R/W 0x00 R/W 0x00 [7:6] DEF_V_12[9:8] ㆍ 13th Vertical defect position 0x2F [5:4} DEF_V_13[9:8] ㆍ 14th Vertical defect position [3:2] DEF_V_14[9:8] ㆍ 15th Vertical defect position R/W 0x00 [1:0] DEF_V_15[9:8] ㆍ 16th Vertical defect position 0x30 [7:0] DEF_H_12[7:0] ㆍ 13th Horizontal defect position R/W 0x00 0x31 [7:0] DEF_V_12[7:0] ㆍ 13th Vertical defect position R/W 0x00 [7:6] DEF_H_12[9:8] ㆍ 13 th Horizontal defect position [5:0] DEF_D_12[5:0] ㆍ 13 th Defect value 0x33 [7:0] DEF_H_13[7:0] ㆍ 14 th Horizontal defect position R/W 0x00 0x34 [7:0] DEF_V_13[7:0] ㆍ 14 th Vertical defect position R/W 0x00 [7:6] DEF_H_13[9:8] ㆍ 14 th Horizontal defect position [5:0] DEF_D_13[5:0] ㆍ 14 th Defect value 0x32 0x35 0x36 [7:0] DEF_H_14[7:0] ㆍ 15th Horizontal defect position 0x37 [7:0] DEF_H_14[7:0] ㆍ 15 0x38 th Vertical defect position [7:6] DEF_H_14[9:8] ㆍ 15th Horizontal defect position [5:0] DEF_D_14[5:0] ㆍ 15th Defect value Data sheet 03.12.2007 (REV 0.0) R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 30/40 N V P 2010 CCD Image Signal Processor BANK 1 ADDR bit NAME DESCRIPTION 0x39 [7:0] DEF_H_15[7:0] ㆍ 16th Horizontal defect position 0x3A [7:0] DEF_V_15[7:0] ㆍ 16 th Vertical defect position [7:6] DEF_H_15[9:8] ㆍ 16 th Horizontal defect position 0x3B [5:0] DEF_D_15[5:0] ㆍ 16th Defect value status default R/W 0x00 R/W 0x00 R/W 0x00 [7:6] DEF_V_16[9:8] ㆍ 17th Vertical defect position 0x3C [5:4} DEF_V_17[9:8] ㆍ 18th Vertical defect position R/W 0x00 [3:2] DEF_V_18[9:8] ㆍ 19 th Vertical defect position [1:0] DEF_V_19[9:8] ㆍ 20 th Vertical defect position 0x3D [7:0] DEF_H_16[7:0] ㆍ 17 th Horizontal defect position R/W 0x00 0x3E [7:0] DEF_V_16[7:0] ㆍ 17 th Vertical defect position R/W 0x00 [7:6] DEF_H_16[9:8] ㆍ 17 th Horizontal defect position [5:0] DEF_D_16[5:0] ㆍ 17 th Defect value 0x3F 0x40 [7:0] DEF_H_17[7:0] ㆍ 18th Horizontal defect position 0x41 [7:0] DEF_V_17[7:0] ㆍ 18 0x42 th Vertical defect position CONFIDENTIAL [7:6] DEF_H_17[9:8] ㆍ 18th Horizontal defect position [5:0] DEF_D_17[5:0] ㆍ 18th Defect value R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 0x43 [7:0] DEF_H_18[7:0] ㆍ 19th Horizontal defect position R/W 0x00 0x44 [7:0] DEF_H_18[7:0] ㆍ 19th Vertical defect position R/W 0x00 [7:6] DEF_H_18[9:8] ㆍ 19 th Horizontal defect position [7:0] DEF_D_18[5:0] ㆍ 19 th Defect value 0x46 [7:0] DEF_H_19[7:0] ㆍ 20 th Horizontal defect position R/W 0x00 0x47 [7:0] DEF_V_19[7:0] ㆍ 20 th Vertical defect position R/W 0x00 [7:6] DEF_H_19[9:8] ㆍ 20 th Horizontal defect position [5:0] DEF_D_19[5:0] ㆍ 20 th Defect value 0x45 0x48 SWITRON R/W 0x00 R/W 0x00 [7:6] DEF_V_20[9:8] ㆍ 21th Vertical defect position 0x49 [5:4} DEF_V_21[9:8] ㆍ 22th Vertical defect position [3:2] DEF_V_22[9:8] ㆍ 23th Vertical defect position R/W 0x00 [1:0] DEF_V_23[9:8] ㆍ 24th Vertical defect position 0x4A [7:0] DEF_H_20[7:0] ㆍ 21th Horizontal defect position R/W 0x00 0x4B [7:0] DEF_V_20[7:0] ㆍ 21th Vertical defect position R/W 0x00 [7:6] DEF_H_20[9:8] ㆍ 21 th Horizontal defect position [5:0] DEF_D_20[5:0] ㆍ 21 th Defect value 0x4D [7:0] DEF_H_21[7:0] ㆍ 22 th Horizontal defect position R/W 0x00 0x4E [7:0] DEF_V_21[7:0] ㆍ 22 th Vertical defect position R/W 0x00 [7:6] DEF_H_21[9:8] ㆍ 22 th Horizontal defect position [5:0] DEF_D_21[5:0] ㆍ 22 th Defect value 0x4C 0x4F 0x50 [7:0] DEF_H_22[7:0] ㆍ 23th Horizontal defect position 0x51 [7:0] DEF_H_22[7:0] ㆍ 23 0x52 th Vertical defect position [7:6] DEF_H_22[9:8] ㆍ 23th Horizontal defect position [5:0] DEF_D_22[5:0] ㆍ 23th Defect value Data sheet 03.12.2007 (REV 0.0) R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 31/40 N V P 2010 CCD Image Signal Processor BANK 1 ADDR bit NAME DESCRIPTION 0x53 [7:0] DEF_H_23[7:0] ㆍ 24th Horizontal defect position 0x54 [7:0] DEF_V_23[7:0] ㆍ 24 th Vertical defect position [7:6] DEF_H_23[9:8] ㆍ 24 th Horizontal defect position 0x55 [7:0] DEF_D_23[5:0] ㆍ 24th Defect value status default R/W 0x00 R/W 0x00 R/W 0x00 [7:6] DEF_V_24[9:8] ㆍ 25th Vertical defect position 0x56 [5:4] DEF_V_25[9:8] ㆍ 26th Vertical defect position R/W 0x00 [3:2] DEF_V_26[9:8] ㆍ 27 th Vertical defect position [1:0] DEF_V_27[9:8] ㆍ 28 th Vertical defect position 0x57 [7:0] DEF_H_24[7:0] ㆍ 25 th Horizontal defect position R/W 0x00 0x58 [7:0] DEF_V_24[7:0] ㆍ 25 th Vertical defect position R/W 0x00 [7:6] DEF_H_24[9:8] ㆍ 25 th Horizontal defect position [5:0] DEF_D_24[5:0] ㆍ 25 th Defect value 0x59 0x5A [7:0] DEF_H_25[7:0] ㆍ 26th Horizontal defect position 0x5B [7:0] DEF_V_25[7:0] ㆍ 26 0x5C th Vertical defect position CONFIDENTIAL [7:6] DEF_H_25[9:8] ㆍ 26th Horizontal defect position [5:0] DEF_D_25[5:0] ㆍ 26th Defect value R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 0x5D [7:0] DEF_H_26[7:0] ㆍ 27th Horizontal defect position R/W 0x00 0x5E [7:0] DEF_H_26[7:0] ㆍ 27th Vertical defect position R/W 0x00 [7:6] DEF_H_26[9:8] ㆍ 27 th Horizontal defect position [5:0] DEF_D_26[5:0] ㆍ 27 th Defect value 0x60 [7:0] DEF_H_27[7:0] ㆍ 28 th Horizontal defect position R/W 0x00 0x61 [7:0] DEF_V_27[7:0] ㆍ 28 th Vertical defect position R/W 0x00 [7:6] DEF_H_27[9:8] ㆍ 28 th Horizontal defect position [5:0] DEF_D_27[5:0] ㆍ 28 th Defect value 0x5F 0x62 SWITRON R/W 0x00 R/W 0x00 [7:6] DEF_V_28[9:8] ㆍ 29th Vertical defect position 0x63 [5:4} DEF_V_29[9:8] ㆍ 30th Vertical defect position [3:2] DEF_V_30[9:8] ㆍ 31th Vertical defect position R/W 0x00 [1:0] DEF_V_31[9:8] ㆍ 32th Vertical defect position 0x64 [7:0] DEF_H_28[7:0] ㆍ 29th Horizontal defect position R/W 0x00 0x65 [7:0] DEF_V_28[7:0] ㆍ 29th Vertical defect position R/W 0x00 [7:6] DEF_H_28[9:8] ㆍ 29 th Horizontal defect position [5:0] DEF_D_28[5:0] ㆍ 29 th Defect value 0x67 [7:0] DEF_H_29[7:0] ㆍ 30 th Horizontal defect position R/W 0x00 0x68 [7:0] DEF_V_29[7:0] ㆍ 30 th Vertical defect position R/W 0x00 [7:6] DEF_H_29[9:8] ㆍ 30 th Horizontal defect position [5:0] DEF_D_29[5:0] ㆍ 30 th Defect value 0x66 0x69 0x6A [7:0] DEF_H_30[7:0] ㆍ 31th Horizontal defect position 0x6B [7:0] DEF_H_30[7:0] ㆍ 31 0x6C th Vertical defect position [7:6] DEF_H_30[9:8] ㆍ 31th Horizontal defect position [5:0] DEF_D_30[5:0] ㆍ 31th Defect value Data sheet 03.12.2007 (REV 0.0) R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 32/40 N V P 2010 CCD Image Signal Processor BANK 1 ADDR bit NAME DESCRIPTION 0x6D [7:0] DEF_H_31[7:0] ㆍ 32th Horizontal defect position 0x6E [7:0] DEF_V_31[7:0] ㆍ 32 th Vertical defect position [7:6] DEF_H_31[9:8] ㆍ 32 th Horizontal defect position 0x6F [5:0] DEF_D_31[5:0] ㆍ ㆍ [7] AED_SPD ㆍ 0x70 [6:4] V_OFFSET ㆍ [3:0] 0x71 0x72 OSD_ROMRAM_POS 32th Defect value AE digital gain speed selection 0 : Normal 1 : Fast Encoder vertical direction offset status default R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x35 ㆍ Set delay for timing on font display [7:4] SEL_IRISL ㆍ Select the input pin for the IRIS control left button signal [3:0] SEL_IRISR ㆍ Select the input pin for the IRIS control right button signal [7:4] Fix [3:0] SEL_MOTION ㆍ Fix at 1'b0. ㆍ Select the input pin for the MOTION enable signal R/W 0x00 R/W 0x00 CONFIDENTIAL SWITRON Data sheet 03.12.2007 (REV 0.0) 33/40 N V P 2010 CCD Image Signal Processor ADDR bit NAME 0x81 [5:0] ACC_BLC_MSB 0x82 [7:0] ACC_BLC_LSB 0x83 [5:0] ACC_NBLC_LSB 0x84 [7:0] ACC_NBLC_LSB BANK 0x81 DESCRIPTION ㆍ Accumulated value at the BLC area ㆍ Accumulated value outside the Non-BLC area AE_ES_MSB ㆍ Electronic shutter value [7:0] AE_ES_LSB [7:0] AGC ㆍ AGC value [7:0] AE_DIGT_GAIN ㆍ AE digital gain value [7:0] AE_ACC ㆍ Average brightness of the input video [7:0] AWB_R ㆍ AWB R value [7:0] AWB_B ㆍ AWB B value [7:0] AWB_TARGET_R ㆍ Target R for AWB [7:0] AWB_TARGET_B ㆍ Target B for AWB status default R - R - R - R - 0x85 [4:0] R - 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D R R R R R R R R - CONFIDENTIAL SWITRON Data sheet 03.12.2007 (REV 0.0) 34/40 N V P 2010 CCD Image Signal Processor 3. Electrical Characteristics 3.1. Absolute Maximum Ratings Parameter Min Max Unit Power supply voltage -0.5 6 V Voltage on any 3.3V input pin 3.0 3.6 V Voltage on any 5V input pin 4.5 5.5 V Storage temperature -40 125 ℃ 3.2. Recommended Operating Condition Parameter Symbol Min Typ Max Unit 3.3V Digital power supply voltage VDD3 3.0 3.3 3.6 V 3.3V Analog power supply voltage AVDD3 3.0 3.3 3.6 V 5.0V Digital power supply voltage Commercial temperature range Industrial temperature range VDD5 TA TA 4.5 0 -40 5.0 - 5.5 70 85 V ℃ ℃ Symbol Min Typ Max Unit - 0.3VDD3 V 3.3. CONFIDENTIAL DC Characteristics Parameter 3.3V Pins *Note1 Input low voltage SWITRON VIL3 VSS-0.3 VIH3 0.7VDD3 - VDD3+0.3 V IIL3 - - -10 uA IIH3 - - 10 uA Input capacitance (f = 1Mhz, VIN3= 2.4V) CIN - - 10 pF Output low voltage (IOH3 = 3.2mA) VOL3 - - 0.4 V Output high voltage (IOH3 = -400uA) VOH3 2.4 - VDD3 V COUT - - 10 pF V Input high voltage Input low current (VIN3 = VSS) Input high current (VIN3 = VDD3) Output capacitance 5.0V Pins *Note2 Input low voltage VIL5 VSS-0.5 - 0.8 Input high voltage VIH5 2.0 - VDD5+0.5 V Input low current (VIN5 = VSS) IIL5 - - -10 uA Input high current (VIN5 = VDD5) IIH5 - - 10 uA Input capacitance (f = 1Mhz, VIN5 = 2.4V) CIN - - 10 pF Output low voltage (IOH5 = 3.2mA) VOL5 - - 0.4 V Output high voltage (IOH5 = -400uA) VOH5 2.4 - VDD5 V Output capacitance COUT - - 10 pF *Note2 : 3.3V data pins expect 5V data pins *Note3 : 5V data pins XRG, H1, H2 pins(#5, #4, #3) Data sheet 03.12.2007 (REV 0.0) 35/40 N V P 2010 CCD Image Signal Processor 4. System Application 4.1.1 Circuit Guide (NVP2010) L1 10uH L2 +3.3V 10uH 1 R1 NC 1 +5.0V R2 0 TC1 T10/10V(A) C1 0.1u(F) C2 0.1u(F) + TC2 T22/6.3V(A) 2 2 +3.3V + L3 C3 0.1u(F) 10uH + TC3 T22/6.3V(A) 2 +3.3_VDD3 +3.3V 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 ADCLK SHP SHD U1 L5 H2 H1 XRG C9 0.1u(F) C10 0.1u(F) XSUB V2 V1 XSG1 V3 XSG2 U2 NVP2010 C7 0.1u(F) R5 2K 1 5 + TC6 T22/6.3V(A) C6 NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VREF IREF COMP VSSA AVDD3C DAC2 VSSA AVDD3Y DAC1 VDD3 VDDI RSTB EXP_I_3 EXP_I_2 EXP_I_1 VSS 6 10uH 2 VSS VDD5 H2 H1 XRG VSS VDD3 VDD3 VSS VDDI XSUB V2 V1 XSG1 V3 XSG2 V4 AFE_SCL AFE_SDA AFE_SLD EXP_IO_1 EXP_IO_2 EXP_IO_3 VDD3 XTALI XTALO VSS VSS EXP_IO_4 I2C_SCL ISC_SDA TSTO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SHD SHP VDD3 ADCLK VSS CF AIN-0 CF AIN-1 CF AIN-2 CF AIN-3 CF AIN-4 CF AIN-5 CF AIN-6 CF AIN-7 CF AIN-8 CF AIN-9 VSSUB 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 +3.3V C5 0.1u(F) 4 VCC P/S GND VOUT VIN VSAG 1 2 TC5 T100/6.3V(B2) 1 2 3 1 NJM2575F1 R4 1K C8 R6 IRIS_SIGNAL 2 R3 75 TC7 T22/6.3V(A) 0.1u(B) 4.7K C11 0.1u(F) R7 200 EXP_I_3 EXP_I_2 EXP_I_1 2 1 C17 D3 KDS160E R9 100K C15 0.1u(F) 0.1u(F) GND 2 1 10uH + 2 TC13 T22/6.3V(A) VCC C20 1u(F) L7 +3.3V 1 RESET 3 EXP_IO_4 SCK SDATA SL EXP_IO_1 EXP_IO_2 EXP_IO_3 TC9 T22/6.3V(A) C13 0.1u(F) 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2 C14 0.1u(F) V4 +3.3V + TC10 T22/6.3V(A) 2 1 CONFIDENTIAL + U4 KIA7029AT(TSM) R13 SWITRON C22 0.1u(F) 1M R14 150 L8 10uH +3.3V 1 X1 R15 4.7K C25 NC R16 4.7K C26 20p(B) + TC14 T22/6.3V(A) 2 T1 20pF C23 0.1u(F) 4 3 2 1 GND SDA AO2 SCL AO1 WP AO0 VCC 5 6 7 8 NTSC:28.63636MHZ PAL:28.375MHZ U5 AT24C16N (SOP) CN4 SDA SCL 4 3 2 1 4P_1.25mm Circuit Guide Ref. Desg. Value Maker L1~L8 10uH TDK TC1~8 Stanrd Type (Size) NLFV25T-100K-PF 2520 NLCV32T-100K-PF 3225 Partsnic TLMOJ226ASSR 3216 SAMSUNG TCSCSOJ226MA 3216 22/6.3V C1~C23 0.1uF SAMSUNG CL10F104ZB8 1608 R1~R23 10K ~ SAMSUNG RC1608J103CS 1608 Data sheet 03.12.2007 (REV 0.0) 36/40 VIDEO N V P 2010 CCD Image Signal Processor D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 ADCLK 4.1.2 Circuit Guide (AD9943) L5 10uH 1 +3.3V + 8 7 6 5 4 3 2 1 C6 0.1u(F) D7 D6 D5 D4 D3 D2 D1 D0 2 TC7 T22/6.3V(A) 9 10 11 12 13 14 15 16 L6 10uH 1 +3.3V U3 AD9943 NC NC NC NC NC SCK SDATA SL 32 31 30 29 28 27 26 25 SCK SDATA SL CLPOB SHP SHD AVDD AVSS CCDIN REFT REFB + D8 D9 DRVDD DRVSS DVDD DATACLK DVSS PBLK CONFIDENTIAL C12 0.1u(F) 17 18 19 20 21 22 23 24 2 TC8 T22/6.3V(A) C16 0.1u(F) + C19 NC 2 C18 NC 1 SWITRON 82 82 + 2 R10 R11 1 CLPOB SHP SHD TC11 T22/6.3V(A) TC12 T22/6.3V(A) CCD IN C21 0.1u(B) Data sheet 03.12.2007 (REV 0.0) 37/40 N V P 2010 CCD Image Signal Processor H1 H2 XRG CCD_OUT 4.1.3 Circuit Guide (CCD) C24 0.1u(F) D4 L9 1 10 10 47uH 2 -8.0V R17 10 C27 0.1u(F) R21 NC 1 +15V_A L10 47uH 1 +15V R20 1M R18 R19 + TC15 T4.7/16V(A) 2 NC TC16 T10/25V(B2) D5 R22 C28 0.1u(F) 2 100 C30 R23 1M C31 270p(B) D6 KDS160E R24 100K 1 VOUT NC NC GND VQ1 VQ2 VQ3 VQ4 D Q1 KTK5132U 1u / 2012(F) 8 7 6 5 4 3 2 1 R25 100 2 VDD GND SUB VL RG NC HQ1 HQ2 2 U7 RJ2351/2361BA 1 NC 9 10 11 12 13 14 15 16 + C29 0.1u(F) U6 16 15 14 13 12 11 10 9 VHH2 VSUB VEE φV2 φV1 VME φV3 φV4 GND XSUB XV2 XV1 XSG1 XV3 XSG2 XV4 1 2 3 4 5 6 7 8 XSUB V2 V1 XSG1 V3 XSG2 V4 NVD2014 CONFIDENTIAL S G R26 4.7K SWITRON Data sheet 03.12.2007 (REV 0.0) 38/40 N V P 2010 4.2. CCD Image Signal Processor Package Information CONFIDENTIAL SWITRON Type Pin pitch Size(WxD) 64 - LQFP 0.40mm 7x7mm Package Data sheet 03.12.2007 (REV 0.0) 39/40 N V P 2010 CCD Image Signal Processor 5. Revision History REVISION DATE DESCRIPTION 6. Contact Information -. Homepage : www.nextchip.com -. E-mail : [email protected] -. Tel : 82-2-3460-4700 CONFIDENTIAL SWITRON Data sheet 03.12.2007 (REV 0.0) 40/40