MICROSEMI NX2142CUTR

NX2142/2142A
SINGLE CHANNEL PWM CONTROLLER WITH FEEDFORWARD
AND 5V BIAS REGULATOR
ADVANCE DATA SHEET
Pb Free Product
FEATURES
DESCRIPTION
n
The NX2142/2142A controller IC is a compact synchron
nous Buck controller IC with 10 lead MSOP package
n
designed for step down DC to DC converter applications with voltage feedforward functionality. Voltage
n
feedforward provides fast response, good line regulan
tion and nearly constant power stage gain under wide
n
voltage input range. The NX2142/2142A controller is
n
optimized to convert single supply up to 24V bus voltn
age to as low as 0.8V output voltage. NX2142/2142A
n
can function as a single supply controller with its 5V
bias regulator. Internal UVLO keeps the regulator off
until the supply voltage exceeds 7V where internal digital soft starts get initiated to ramp up output. The n
NX2142/2142A employs fixed current limiting and FB n
UVLO followed by hiccup feature. Other features in- n
cludes: 5V gate drive capability , Converter Shutdown
by pulling COMP pin to Gnd, Adaptive dead band con- n
trol.
Bus voltage operation from 7V to 24V
5V bias regulator available
Excellent dynamic response with input voltage
feed-forward and voltage mode control
Fixed 600kHz, 1MHz switching frequency
Internal Digital Soft Start Function
Fixed internal hiccup current limit
FB UVLO followed by hiccup feature
Shutdown by pulling COMP pin low
Pb-free and RoHS compliant
APPLICATIONS
Graphic Card on board converters
Vddq Supply in mother board applications
On board DC to DC such as
12V to 3.3V, 2.5V or 1.8V
Set Top Box and LCD Display
TYPICAL APPLICATION
Vin
+8 to 20V
47uF
1uF
MMBT3904
BAT54A
1uF
7
6
5
25TQC33M
VCC
REGOUT
1
0.1uF
BST
Hdrv
2
AO4800(half)
VIN
9
COMP
20k
27pF
NX2142
0.1uF
DO3316P-682
SW
1000uF,30mohm
Ldrv
5.2nF
8
Vout
+3.3V /3A
10
4
AO4800(half)
1k
FB
Gnd
3
324
Figure1 - Typical application of NX2142
ORDERING INFORMATION
Device
NX2142CUTR
NX2142ACUTR
Rev. 1.1
10/28/07
Temperature
0 to 70o C
0 to 70o C
Package
MSOP-10L
MSOP-10L
Frequency
600kHz
1MHz
Pb-Free
Yes
Yes
1
NX2142/2142A
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V
VIN to GND ........................................................ -0.3V to 30V
BST to GND Voltage .......................................... -0.3V to 35V
SW to GND ....................................................... -2V to 35V
REGOUT to GND ................................................ 0.2 to 16V
All other pins ..................................................... -0.3V to 6.5V
Storage Temperature Range ................................ -65oC to 150oC
Operating Junction Temperature Range ................ -40oC to 125oC
ESD Susceptibility ............................................ 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
10-LEAD PLASTIC MSOP
θJA ≈ 200o C/W
BST 1
10 SW
HDrv 2
9 COMP
GND 3
8 FB
LDrv 4
7 VCC
VIN 5
6 REGOUT
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA = 0 to 70oC. Typical
values refer to TA = 25oC.
PARAMETER
Reference Voltage
Ref Voltage
Ref Voltage line regulation
Supply Voltage(Vcc)
VCC Voltage Range
Operating quiescent current
Vcc UVLO
VCC-Threshold
VCC-Hysteresis
Supply Voltage(Vin)
Vin Voltage Range
Input Voltage Current
Vin UVLO
Vin-Threshold
Rev. 1.1
10/28/07
SYM
Test Condition
Min
TYP
MAX
Units
VREF
0.8
0.2
V
%
VCC
IQ
5
3
V
mA
4.4
0.2
V
V
EN=HIGH
VCC_UVLO VCC Rising
VCC_Hyst VCC Falling
Vin
Vin_UVLO
Vin=24V
9
V
mA
Vin Rising
6
V
7
25
2
NX2142/2142A
PARAMETER
Vin-Hysteresis
Oscillator (Rt)
Frequency
Frequency Over Vin
Ramp Peak to Peak Voltage
Ramp Valley Voltage
Ramp Peak to Peak/Vin Gain
Max Duty Cycle
Min Duty Cycle
Min Controllable on time
Error Amplifiers
Transconductance
Input Bias Current
Comp SD threshold
Soft Start
Soft Start time
High Side Driver
(CL=3300pF)
Output Impedance , Sourcing
Current
Output Impedance , Sinking
Current
Rise Time
Fall Time
Deadband Time
SYM
Vin_Hyst
Test Condition
Vin Falling
FS
NX2142
NX2142A
VRAMP
Vin=20V
FS=600kHz
Min
TYP
0.5
MAX
600
1000
1
2
0.8
0.1
77
0
150
2500
0.3
3.4
2
mS
mS
100
NX2142
NX2142A
KHz
KHz
%
V
V
V/V
%
%
nS
umho
nA
V
Ib
Tss
Units
V
Rsource(Hdrv)
I=200mA
1
ohm
Rsink(Hdrv)
I=200mA
0.8
ohm
THdrv(Rise)
10% to 90%
THdrv(Fall)
90% to 10%
Tdead(L to Ldrv going Low to Hdrv going
High, 10% to 10%
H)
50
50
30
ns
ns
ns
Rsource(Ldrv)
I=200mA
1
ohm
Rsink(Ldrv)
I=200mA
0.5
ohm
50
50
30
ns
ns
ns
320
mV
70
%
150
20
°C
°C
N
Low Side Driver
(CL=3300pF)
Output Impedance, Sourcing
Current
Output Impedance, Sinking
Current
Rise Time
Fall Time
Deadband Time
Fixed OCP
OCP voltage threshold
FBUVLO
Feedback UVLO threshold
Over temperature
Threshold
Hysteresis
Rev. 1.1
10/28/07
TLdrv(Rise)
10% to 90%
TLdrv(Fall)
90% to 10%
Tdead(H to SW going Low to Ldrv going
L)
High, 10% to 10%
percent of nominal
3
NX2142/2142A
PIN DESCRIPTIONS
PIN SYMBOL
PIN DESCRIPTION
VCC
This pin supplies the internal 5V bias circuit. A 1uF high frequency ceramic X5R
capacitor must be placed as close as possible to this pin and ground pin to provide
high frequency bypass and to make the 5V regulator stable.
BST
This pin supplies voltage to high side FET driver. A minimum 0.1uF ceramic high
frequency capacitor is placed as close as possible to and connected to this pin and
SW pin.
GND
Power ground.
FB
COMP
SW
This pin is the error amplifiers inverting input. It is connected via resistor divider to
the output of the switching regulator to set the output DC voltage.
This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. You can shutdown the switching regulator by
pulling this pin below 0.3V.
This pin is connected to source of high side FETs and provides return path for the
high side driver. This pin also provides input for the OCP comparator by sensing the
RDSON of the lower MOSFET. When this pin is below ground by 320mV, both drivers
are shutdown and enter hiccup mode.
HDRV
High side gate driver output.
LDRV
Low side gate driver output.
REGOUT
VIN
The output of the 5V regulator controller that drives a low current low cost external
bipolar transistor or an external MOSFET to regulate the voltage at Vcc pin derived
from bus voltage. This eliminates an otherwise external regulator needed in applications where 5V is not available. This regulator request a 1uF ceramic X5R type output
capacitor in order to be stable.
This pin provides the input voltage to the 5V regulator controller as well as the
oscillator for the PWM feed forward to work. When VIN exceeds 6V, the converter
starts to operate.
Rev. 1.1
10/28/07
4
NX2142/2142A
BLOCK DIAGRAM
VIN
Ref
Regout
4.4/4.2V
Bias
Generator
VCC
1.25V
0.8V
BST
POR
UVLO
START
6V/
5.5V
HDRV
COMP
0.3V
SW
OC
VIN
Control
Logic
START 0.8V
OSC
Digital
start Up
PWM
VCC
ramp
S
R
LDRV
Q
OC
FB
0.6V
CLAMP
COMP
START
POR
1.3V
CLAMP
320mV
Hiccup Logic
OCP
comparator
SS_half_done
70%*Vp
FB
GND
Figure 2 - Simplified block diagram of the NX2142
Rev. 1.1
10/28/07
5
NX2142/2142A
TYPICAL APPLICATION CIRCUIT
BUS
BUS(8-20V)
C10
47u
C2
1u
D1
BAT54A
VDD
C6
0.1u
U _VCC
U _VIN
GNDBUS
7
BST
1
BST
1u
EN/REG_OUT
HDRV
2
U_HDRV
10
U_SW
M5A
STM6912
HDRV 2
1
6
7
8
C1
0.1u
EN_REGOUT
Ci1
25TQC33M
C14
VCC
VIN
U1
5
Q1
2N3904
SW
SW
Lo
1
2
DO3316P-682
VOUT
OUT(5V)
5
6
LDRV
U_LDRV
4
M6B
STM6912
FB
8
GNDOUT
R15
10
LDRV 4
C9
470p
3
NX2142CUTR
Co1
1000uF, 6.3v,30mohm
C5
FB
R8
1.2k
25n
R7
10k
R10
953
C4
52p
R9
4.99k
COMP
9
COMP
3
GND
C3
3.3n
Figure 3- Demo board schematic(VIN=8-20V,VOUT=5V,IOUT=3A)
Rev. 1.1
10/28/07
6
NX2142/2142A
Bill of Materials
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Rev. 1.1
10/28/07
Quantity
1
1
2
3
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
Reference
Ci1
Co1
C1,C6
C2,C14
C3
C4
C5
C9
C10
D1
Lo
M5,M6
Q1
R7
R8
R9
R10
R15
U1
Value
25TQC33M
6MV1000W G
0.1u
1u
3.3n
52p
25n
470p
47u
BAT54A
DO3316P-682
AO4800
MMBT3904
10k
1.2k
4.99k 1%
953 1%
10
NX2142CUTR
Manufacture
SANYO
SANYO
Fairchild
Coilcraft
AOS
Fairchild
NEXSEM INC.
7
NX2142/2142A
Demoboard waveforms
Figure 5 - Output voltage transient response
(VIN=12V, IOUT=3A)
Figure 4 - Output ripple (VIN=12V)
Figure 6 - Over current protection
Figure 7 - Startup
100.00%
95.00%
90.00%
85.00%
Eff(%)
80.00%
75.00%
70.00%
65.00%
60.00%
55.00%
50.00%
0
500
1000
1500
2000
2500
3000
3500
Iout(mA)
Figure 8 - Output Efficiency(VIN=12V, VOUT=5V)
Rev. 1.1
10/28/07
8
NX2142/2142A
Current Ripple is calculated as
APPLICATION INFORMATION
IRIPPLE =
Symbol Used In Application Information:
VIN
=
- Input voltage
VOUT
- Output voltage
IOUT
- Output current
- Switching frequency
DIRIPPLE
- Inductor current ripple
...(2)
20V-5V 5V
1
×
×
= 0.919A
6.8uH 20V 600kHz
Output Capacitor Selection
DVRIPPLE - Output voltage ripple
FS
VIN -VOUT VOUT
1
×
×
LOUT
VIN FS
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during
steady state(DC) load condition as well as specification for the load transient. The optimum design may
Design Example
VINMIN=8V
require a couple of iterations to satisfy both condition.
Based on DC Load Condition
The amount of voltage ripple during the DC load
VINMAX=20V
condition is determined by equation(3).
Power stage design requirements:
VOUT=5V
∆VRIPPLE = ESR × ∆IRIPPLE +
IOUT =3A
DVRIPPLE <=50mV
∆IRIPPLE
8 × FS × COUT
...(3)
Where ESR is the output capacitors' equivalent
DVTRAN<=150mV @ 1.5A step
series resistance,COUT is the value of output capaci-
FS=600kHz
tors.
Typically when large value capacitors are selected
Output Inductor Selection
such as Aluminum Electrolytic,POSCAP and OSCON
The selection of inductor value is based on in-
types are used, the amount of the output voltage ripple
ductor ripple current, power rating, working frequency
is dominated by the first term in equation(3) and the
and efficiency. Larger inductor value normally means
second term can be neglected.
smaller ripple current. However if the inductance is
For this example, Aluminum Electrolytic is cho-
chosen too large, it brings slow response and lower
sen as output capacitor, the ESR and inductor current
efficiency. Usually the ripple current ranges from 20%
typically determines the output voltage ripple.
to 40% of the output current. This is a design freedom
which can be decided by design engineer according to
ESRdesire =
various application requirements. The inductor value
can be calculated by using the following equations:
V
-V
V
1
LOUT = INMAX OUT × OUT ×
IRIPPLE
VINMAX FS
IRIPPLE =k ×IOUTPUT
∆VRIPPLE
50mV
=
= 54m Ω
∆IRIPPLE
0.919A
...(4)
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 50mV output ripple, Electrolytic
...(1)
where k is between 0.2 to 0.4.
Select k=0.3, then
6ME1000WG with 30mΩ are chosen.
N =
E S R E × ∆ IR I P P L E
∆ VR IPPLE
...(5)
Number of Capacitor is calculated as
20V-5V 5V
1
LOUT =
×
×
0.3 × 3A 20V 600kHz
LOUT =6.9uH
Choose LOUT=6.8uH, then coilcraft inductor
DO3316P-682HC is a good choice.
N=
30mΩ× 0.919A
50mV
N =0.55
The number of capacitor has to be round up to a
integer. Choose N =1.
Rev. 1.1
10/28/07
9
NX2142/2142A
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evalu-
tance of each capacitor if multiple capacitors are used
in parallel.
ated to determine the overall ripple. Usually when this
The above equation shows that if the selected
type of capacitors are selected, the amount of capaci-
output inductor is smaller than the critical inductance,
tance per single unit is not sufficient to meet the tran-
the voltage droop or overshoot is only dependent on
sient specification, which results in parallel configura-
the ESR of output capacitor.
tion of multiple capacitors.
pacitor such as electrolytic capacitor, the product of
For example, one 100uF, X5R ceramic capacitor with 2mΩ ESR is used. The amount of output ripple
is
∆VRIPPLE
0.919A
= 2mΩ× 0.919A +
8 × 600kHz ×100uF
= 1.838mV + 1.9mV = 3.738mV
For low frequency ca-
ESR and capacitance is high and L ≤ L crit is true. In
that case, the transient spec is mostly like to dependent on the ESR of capacitor.
Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
One ceramic capacitors are needed. Although
this can meet DC ripple spec, however it needs to be
studied for transient requirement.
N=
ESR E × ∆Istep
∆Vtran
+
VOUT
× τ2
2 × L × C E × ∆Vtran
...(9)
where
Based On Transient Requirement
Typically, the output voltage droop during transient is specified as
∆V droop < ∆V tran @step load DISTEP
0 if L ≤ L crit

τ =  L × ∆Istep
− ESR E × CE
 V
 OUT
if
L ≥ L crit
...(10)
During the transient, the voltage droop during
the transient is composed of two sections. One sec-
For example, assume voltage droop during tran-
tion is dependent on the ESR of capacitor, the other
sient is 150mV for 1.5A load step.
section is
If the Electrolytic 6ME1000WG(1000uF, 30mohm
ESR) is used, the crticial inductance is given as
a function of the inductor, output capacitance as well
as input, output voltage. For example, for the
overshoot when load from high load to light load
with a DISTEP transient load, if assuming the bandwidth of system is high enough, the overshoot can
be estimated as the following equation.
∆Vovershoot
where
VOUT
= ESR × ∆Istep +
× τ2
2 × L × COUT
...(6)
τ is the a function of capacitor,etc.
0 if L ≤ L crit

τ =  L × ∆Istep
− ESR × COUT
 V
 OUT
if
L ≥ L crit
...(7)
where
L crit =
ESR × COUT × VOUT ESR E × C E × VOUT
=
...(8)
∆Istep
∆Istep
where ESRE and CE represents ESR and capaci-
L crit =
ESR E × C E × VOUT
=
∆Istep
30mΩ × 1000µF × 5V
= 100µH
1.5A
The selected inductor is 6.8uH which is much
smaller than critical inductance. In that case, the output voltage transient not only dependent on the ESR,
but also capacitance.
number of capacitor is
N=
ESR E × ∆Istep
∆Vtran
30mΩ ×1.5A
200mV
= 0.225
=
The number of capacitors has to satisfy both ripple
and transient requirement. Overall, we choose N=1.
Rev. 1.1
10/28/07
10
NX2142/2142A
It should be considered that the proposed equa-
following figures and equations show how to realize
tion is based on ideal case, in reality, the droop or over-
the type III compensator by transconductance ampli-
shoot is typically more than the calculation. The equa-
fier.
tion gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for
high frequency capacitor such as high quality POSCAP
especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the
ESR of capacitors is so low that the PCB parasitic can
affect the results tremendously. More capacitors have
to be selected to compensate these parasitic param-
Compensator Design
1
2 × π × (R 2 + R3 ) × C3
...(12)
FP1 =
1
2 × π × R3 × C3
...(13)
1
2 × π × R4 ×
...(14)
C1 × C2
C1 + C2
The transfer function of type III compensator for
transconductance amplifier is given by:
Ve
1 − gm × Z f
=
VOUT
1 + gm × Zin + Z in / R1
sponse, compensator is employed to provide highest
possible bandwidth and enough phase margin. Ideally,
frequency between 1/10 and 1/5 of the switching fre-
FZ2 =
the compensator.
shift , and therefore, is unstable by itself. In order to
the Bode plot of the closed loop system has crossover
...(11)
where FZ1,FZ2,FP1 and FP2 are poles and zeros in
Due to the double pole generated by LC filter of
achieve accurate output voltage and fast transient re-
1
2 × π × R 4 × C2
FP2 =
eters.
the power stage, the power system has 180o phase
FZ1 =
For the voltage amplifier, the transfer function of
compensator is
quency, phase margin greater than 50o and the gain
capacitors usually decide the compensator type. If
Ve
−Z f
=
VOUT
Zin
electrolytic capacitors are chosen as output capacitors,
To achieve the same effect as voltage amplifier,
type II compensator can be used to compensate the
the compensator of transconductance amplifier must
system, because the zero caused by output capacitor
satisfy this condition: R4>>2/gm. And it would be de-
ESR is lower than crossover frequency. Otherwise type
sirable if R1||R2||R3>>1/gm can be met at the same
III compensator should be chosen.
time,
crossing 0dB with -20dB/decade. Power stage output
Voltage feedforward compensation is used in
NX2142 to compensate the output voltage variation
caused by input voltage changing. The feedforward
Zin
Zf
C1
Vout
funtion is realized by using VIN pin voltage to program
the oscillator ramp voltage VOSC at about 1/10 of VIN
R3
R2
voltage, which provides nearly constant power stage
gain under wide voltage input range.
A. Type III compensator design
For low ESR output capacitors, typically such as
C3
C2
R4
Fb
gm
Ve
R1
Vref
Sanyo oscap and poscap, the frequency of ESR zero
caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compensate the system with type III compensator. The
Rev. 1.1
10/28/07
Figure 9 - Type III compensator using
transconductance amplifier
11
NX2142/2142A
Case 1:
FLC<FO<FESR(for most ceramic or low
ESR POSCAP, OSCON)
2. Set R4 equal to 10kΩ.
3. Calculate C2 with zero Fz1 at 50% of the LC
Gain(db)
double pole by equation (11).
1
2 × π × FZ1 × R 4
C2 =
power stage
FLC
1
2 × π × 0.5 × 9.2kHz × 10k Ω
= 3.5nF
=
40dB/decade
Choose C2=3.9nF.
4. Calculate C1 by equation (14) with pole Fp2 at
loop gain
FESR
20dB/decade
half the switching frequency.
1
2 × π × R 4 × FP2
C1 =
1
2 × π × 10k Ω × 300kHz
= 53pF
=
compensator
Choose C1=52pF.
5. Calculate C3 with the crossover frequency at
FZ1 FZ2
FO FP1
FP2
1/10~ 1/5 of the switching frequency. Set FO=60kHz.
C3 =
Figure 10 - Bode plot of Type III compensator
1 2 × π × 60kHz × 6.8uH
×
× 44uF
10
10k Ω
=1.1nF
(FLC<FO<FESR)
Typical design example of type III compensator
=
in which the crossover frequency is selected as
FLC<FO<FESR and FO<=1/10~1/5Fs is shown as the
following steps. Here two X5R 22uF ceramic capacitor
with3m Ω is chosen as output capacitor, output inductor
Choose C3=1.2nF.
6. Set zero FZ2 = 0.75FLC and Fp1 =0.5Fs, calculate R2.
is 6.8uH.
1. Calculate the location of LC double pole FLC
and ESR zero FESR.
FLC =
=
1
2 × π × L OUT × C OUT
1
1
2 × π × ESR × C OUT
1
2 × π × 1.5m Ω × 44uF
= 241kHz
=
Rev. 1.1
10/28/07
R2 =
1
1 1
×( - )
2 ×π× C3 Fz2 Fp1
1
1
1
×(
)
2 ×π× 1.2nF 0.75*9.2kHz 300kHz
=18kΩ
=
2 × π × 6.8uH × 44uF
= 9.2kHz
FESR =
VOSC 2 × π × FO × L
×
× C out
Vin
R4
Choose R2=20kΩ.
7. Calculate R3 by equation (13) with Fp1 =Fs.
R3 =
1
2 × π × FP1 × C3
1
2 × π × 600kHz × 1.2nF
= 221Ω
=
Choose R3 =300Ω.
12
NX2142/2142A
8. Calculate R1.
R × VREF
20k Ω × 0.8V
R1 = 2
=
= 5.7k Ω
VOUT -VREF
5V-0.8V
FESR =
1
2 × π × ESR × COUT
1
2 × π × 30mΩ × 1000uF
= 5.3kHz
=
Choose R1=5.7kΩ.
2. Set R4 equal to 10kΩ.
Gain(db)
Case 2:
FLC<FESR<FO(for electrolytic capacitors)
3. Calculate C2 with zero Fz1 at 75% of the LC
double pole by equation (11).
power stage
FLC
40dB/decade
C2 =
1
2 × π × FZ1 × R 4
1
2 × π × 0.75 × 1.93kHz × 10k Ω
= 10nF
=
FESR
loop gain
Choose C2=10nF.
4. Calculate C1 by equation (14) with pole Fp2 at
20dB/decade
half the switching frequency.
C1 =
compensator
1
2 × π × R 4 × FP2
1
2 × π × 10k Ω × 300kHz
= 53pF
=
FZ1 FZ2 FP1 FO
FP2
Figure 11 - Bode plot of Type III compensator
Choose C1=52pF.
5. Calculate C3 with the crossover frequency at
1/10~ 1/5 of the switching frequency. Set FO=60kHz.
(FLC<FESR<FO)
C3 =
If electrolytic capacitors are used as output
1
60kHz × 6.8uH
×
10 30m Ω × 10kΩ × 5.3kHz
=25nF
=
capacitors, typical design example of type III
compensator in which the crossover frequency is
selected as FLC<FESR<FO and F O<=1/10~1/5Fs is shown
VOSC
FO × L
×
V in
E S R × R 4 × FP 1
as the following steps. Here one SANYO 6ME-WG1000
Choose C3=25nF.
with 30 mΩ is chosen as output capacitor, output
6. Set zero FZ2 = FLC and Fp1 =FESR, calculate R2.
inductor is 6.8uH.
1. Calculate the location of LC double pole FLC
and ESR zero FESR.
FLC =
=
1
1 1
×(
)
2 × π × C3
Fz2 Fp1
1
1
1
×(
)
2 × π × 25nF 1.93kHz 5.3kHz
=2kΩ
=
1
2 × π × LOUT × COUT
1
2 × π × 6.8uH × 1000uF
= 1.93kHz
Rev. 1.1
10/28/07
R2 =
Choose R2=20kΩ.
7. Calculate R3 by equation (13) with Fp1 =FESR.
13
NX2142/2142A
R3 =
1
2 × π × FP1 × C3
power stage
1
2 × π × 5.3kHz × 25nF
= 1.2k Ω
Gain(db)
=
Choose R3 =1.2kΩ.
8. Calculate R1.
R1 =
40dB/decade
loop gain
R 2 × VREF
1.2k Ω × 0.8V
=
= 381Ω
VOUT -VREF
5V-0.8V
20dB/decade
Choose R1=381Ω.
B. Type II compensator design
compensator
If the electrolytic capacitors are chosen as
Gain
power stage output capacitors, usually the Type II
compensator can be used to compensate the system.
FZ FLC FESR
For this type of compensator, FO has to satisfy
FO FP
FLC<FESR<<FO<=1/10~1/5Fs.
Figure 12 - Bode plot of Type II compensator
Case 1:
C2
Type II compensator can be realized by simple
RC circuit as shown in figure 13. R3 and C1 introduce a
zero to cancel the double pole effect. C2 introduces a
pole to suppress the switching noise.
To achieve the same effect as voltage amplifier,
the compensator of transconductance amplifier must
satisfy this condition: R3>>1/gm and R1||R2>>1/gm.
The following equations show the compensator pole
Vout
R3
C1
R2
Fb
gm
R1
Ve
Vref
zero location and constant gain.
R
Gain= 3
R2
Fz =
1
2 × π × R3 × C1
1
Fp ≈
2 × π × R 3 × C2
... (15)
... (16)
Figure 13 - Type II compensator with
transconductance amplifier(case 1)
The following parameters are used as an
example for type II compensator design, three
... (17)
1500uF with 19mohm Sanyo electrolytic CAP
6MV1500WGL are used as output capacitors.
Coilcraft DO5010P-152HC 1.5uH is used as output
inductor. The power stage information is that:
VIN=12V, VOUT=1.2V, IOUT =12A, FS=600kHz.
1.Calculate the location of LC double pole FLC
and ESR zero FESR.
Rev. 1.1
10/28/07
14
NX2142/2142A
FLC =
Case 2:
1
2 × π × L OUT × COUT
1
=
2 × π × 1.5uH × 4500uF
= 1.94kHz
FESR =
1
2 × π × ESR × COUT
1
=
2 × π × 6.33m Ω × 4500uF
= 5.6kHz
2.Set crossover frequency FO=60kHz>>FESR.
3. Set R2 equal to 4kΩ. Based on output
Type II compensator can also be realized by
simple RC circuit without feedback as shown in figure
15. R3 and C1 introduce a zero to cancel the double
pole effect. C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero location and constant gain.
Gain=gm ×
Fz =
R1
× R3
R1 +R 2
1
2 × π × R3 × C1
Fp ≈
1
2 × π × R 3 × C2
... (18)
... (19)
... (20)
voltage, using equation 21, the final selection of R1 is
8kΩ.
4.Calculate R3 value by the following equation.
VOSC
2 × π × FO × L
×
×R2
V in
ESR
R3=
1
2 × π × 60kHz × 1.5uH
×
× 4kΩ
10
6.33m Ω
=36kΩ
=
Vout
R2
Fb
gm
R1
Ve
R3
Vref
C2
Choose R3 =37.4kΩ.
C1
5. Calculate C1 by setting compensator zero FZ
at 75% of the LC double pole.
1
2 × π × R3 × Fz
C1=
1
2 × π × 37.4kΩ × 0.75 × 1.94kHz
=2.7nF
Figure 14 - Type II compensator with
transconductance amplifier(case 2)
=
Choose C1=2.7nF.
6. Calculate C2 by setting compensator pole Fp
at half the swithing frequency.
The following is parameters for type II compensator design. Input voltage is 12V, output voltage is
2.5V, output inductor is 2.2uH, output capacitors are
two 680uF with 41mΩ electrolytic capacitors.
1.Calculate the location of LC double pole FLC
1
C2=
π × R 3 × Fs
1
π × 3 7 .4k Ω × 6 0 0 k H z
=14pF
=
Choose C2=15pF.
Rev. 1.1
10/28/07
and ESR zero FESR.
FLC =
=
1
2 × π × L OUT × COUT
1
2 × π × 2.2uH × 1360uF
= 2.9kHz
15
NX2142/2142A
FESR =
1
2 × π × ESR × COUT
1
2 × π × 20.5m Ω × 1360uF
= 5.7kHz
=
2.Set R2 equal to10kΩ. Using equation 18, the
final selection of R1 is 4.7kΩ.
3. Set crossover frequency at 1/10~ 1/5 of the
Output Voltage Calculation
Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
at 0.8V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.8V
when the output voltage is at the desired value. The
following equation applies to figure 15, which shows
the relationship between
VOUT , VREF and voltage di-
vider.
swithing frequency, here FO=60kHz.
4.Calculate R3 value by the following equation.
R3 =
VOSC 2 × π × FO × L 1 VOUT
×
×
×
Vin
RESR
gm VREF
1 2 × π × 60kHz × 2.2uH
1
×
×
10
20.5m Ω
2.5mA/V
2.5V
×
0.8V
=5kΩ
=
Vout
R2
Fb
R1
Vref
Figure 15 - Voltage divider
Choose R3 =5kΩ.
5. Calculate C1 by setting compensator zero FZ
at 75% of the LC double pole.
1
2 × π × R 3 × Fz
C1 =
1
2 × π × 5k Ω × 0.75 × 2.9kHz
=14nF
=
Choose C1=15nF.
6. Calculate C2 by setting compensator pole Fp
at half the swithing frequency.
C
2
=
R 1=
R 2 × VR E F
V O U T -V R E F
...(21)
where R2 is part of the compensator, and the value
of R1 value can be set by voltage divider.
Input Capacitor Selection
Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and
bulk capacitors supply switching current to the
MOSFETs. Usually 1uF ceramic capacitor is chosen
to decouple the high frequency noise.The bulk input
1
× Fs
capacitors are decided by voltage rating and RMS cur-
1
π × 5kΩ × 600kH z
=54pF
rent rating. The RMS current in the input capacitors
π × R
3
=
Choose C2=52pF.
can be calculated
as:
IRMS = IOUT × D × 1- D
D=
VOUT
VINMIN
...(22)
VINMIN = 8V, VOUT=1.05V, IOUT=10A, the result of
input RMS current is 3.4A.
For higher efficiency, low ESR capacitors are
recommended. One Sanyo OSCON CAP 25SVP56M
Rev. 1.1
10/28/07
16
NX2142/2142A
25V 56uF 28mΩ with 3.8A RMS rating are chosen
as input bulk capacitors.
where QHGATE is the high side MOSFETs gate
charge,Q LGATE is the low side MOSFETs gate
charge,VHGS
Power MOSFETs Selection
is the high side gate source voltage, and VLGS is the
The NX2142 requires two N-Channel power
MOSFETs. The selection of MOSFETs is based on
maximum drain source voltage, gate source voltage,
low side gate source voltage.
This power dissipation should not exceed maximum power dissipation of the driver device.
maximum current rating, MOSFET on resistance and
power dissipation. The main consideration is the power
Over Current Limit Protection
Over current Limit for step down converter is
loss contribution of MOSFETs to the overall converter
efficiency. In this design example, two STM6912 are
used. They have the following parameters: VDS=30V, ID
achieved by sensing current through the low side
=6A,RDSON =57mΩ,QGATE =6.3nC.
the RDSON of the low side mosfet. When synchronous
There are two factors causing the MOSFET
power loss:conduction loss, switching loss.
calculated by the following equation.
ISET = 320mV/R DSON
PHCON =IOUT 2 × D × RDS(ON) × K
PTOTAL =PHCON + PLCON
FET is on, and the voltage on SW pin is below 320mV,
the over current occurs. The over current limit can be
Conduction loss is simply defined as:
PLCON =IOUT 2 × (1 − D) × RDS(ON) × K
MOSFET. For NX2142, the current limit is decided by
...(23)
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature
The MOSFET RDSON is calculated in the worst
case situation, then the current limit for MOSFET
STM6912 is
ISET =
320mV
320mV
=
= 4.6A
RDSON 1.2 × 57mΩ
dependency. As a result, RDS(ON) should be selected
for the worst case, in which K approximately equals to
Layout Considerations
1.4 at 125oC according to datasheet. Conduction loss
The layout is very important when designing high
should not exceed package rating or overall system
frequency switching converters. Layout will affect noise
thermal budget.
pickup and can cause a good design to perform with
Switching loss is mainly caused by crossover conduction at the switching transition. The total switching
less than expected results.
There are two sets of components considered in
loss can be approximated.
the layout which are power components and small sig-
1
× VIN × IOUT × TSW × FS
...(24)
2
where IOUT is output current, TSW is the sum of TR
and TF which can be found in mosfet datasheet, and
FS is switching frequency. Swithing loss PSW is frequency dependent.
Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined
as:
nal components. Power components usually consist of
PSW =
Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS
Rev. 1.1
10/28/07
...(25)
input capacitors, high-side MOSFET, low-side
MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due
to the switching power. Small signal components are
connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
17
NX2142/2142A
to reduce the EMI radiated by the power loop due to
the high switching currents through them.
2. Low ESR capacitor which can handle input
RMS ripple current and a high frequency decoupling
ceramic cap which usually is 1uF
need to be practi-
cally touching the drain pin of the upper MOSFET, a
plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is required.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a
plane ans as close as possible. A snubber nedds to be
placed as close to this junction as possible.
5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to
the output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other bypassing capacitor needs to be placed first around the
IC and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals.
9. All GNDs need to go directly thru via to GND
plane.
10. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC.
11. In multilayer PCB, separate power ground and
analog ground. These two grounds must be connected
together on the PC board layout at a single point. The
goal is to localize the high current path to a separate
loop that does not interfere with the more sensitive analog control function.
Rev. 1.1
10/28/07
18