INTEGRATED CIRCUITS 80CL410/83CL410 Low voltage/low power single-chip 8-bit microcontroller with I2C Product specification IC20 Data Handbook 1995 Jan 20 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 FEATURES • Single supply voltage 1.8V to 6.0V • Frequency from DC to 12MHz • 80C51 based architecture PIN CONFIGURATION The 80CL410/83CL410 (hereafter generically referred to as 8XCL410) is manufactured in an advanced CMOS process that allows the part to operate at supply voltages down to 1.8V and oscillator frequencies down to DC. The 8XCL410 has the same instruction set as the 80C51. The 8XCL410 features a 4k byte ROM (83CL410), 128 bytes RAM (both ROM and RAM are externally expandable to 64k bytes), four 8-bit ports, two 16-bit timer/counters, an I2C serial interface, a thirteen source, two priority level nested interrupt structure, and on-chip oscillator circuitry suitable for quartz crystal, ceramic resonator, RC, or LC. The 8XCL410 has two reduced power modes that are the same as those on the standard 80C51. The special reduced power feature of this part is that it can be stopped and then restarted. Running from an external clock source, the clock can be stopped and after a period of time restarted. The 8XCL410 will resume operation from where it was when the code stopped with no loss of internal state, RAM contents, or Special Function Register contents. If the internal oscillator is used the part cannot be stopped and started, but the power-down mode, which can be terminated via an interrupt, can be used to achieve similar power savings and then restart without loss of on-chip RAM and Special Function Register values. 40 V DD INT3/P1.1 2 39 P0.0/AD0 – 4k × 8 ROM (64k external) INT4/P1.2 3 38 P0.1/AD1 – 128 × 8 RAM (64k external) INT5/P1.3 4 37 P0.2/AD2 – Four 8-bit I/O ports INT6/P1.4 5 36 P0.3/AD3 INT7/P1.5 6 35 P0.4/AD4 – A thirteen-source, two-level, nested priority interrupt structure SCL/INT8/P1.6 7 34 P0.5/AD5 – 10 external interrupts SDA/INT9/P1.7 8 33 P0.6/AD6 – Two 16-bit timer/counters DESCRIPTION INT2/P1.0 1 • Fully static 80C51 CPU • I2C Serial Interface • Two power control modes 32 P0.7/AD7 RST 9 P3.0 10 DIP 31 EA P3.1 11 VSO 30 ALE – Idle mode INT0/P3.2 12 29 PSEN – Power-down mode – can be terminated by reset or external interrupt INT1/P3.3 13 28 P2.7/A15 T0/P3.4 14 27 P2.6/A14 T1/P3.5 15 26 P2.5/A13 WR/P3.6 16 25 P2.4/A12 RD/P3.7 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 • Wake-up via external interrupts at port 1 • Single supply voltage 1.8V to 6.0V • Frequency range of DC to 12MHz • On-chip oscillator (quartz crystal, ceramic resonator, RC, LC) • Very low power consumption • Operating temperature range: XTAL1 19 22 P2.1/A9 VSS 20 21 P2.0/A8 –40 to +85°C 44 34 1 33 QFP 11 23 12 22 SEE NEXT PAGE FOR QFP PIN FUNCTIONS. ORDERING CODE PHILIPS PART ORDER NUMBER PART MARKING PHILIPS NORTH AMERICA PART ORDER NUMBER1 ROMless TEMPERATURE °C AND PACKAGE ROM ROMless ROM P80CL410HFP P83CL410HFP P80CL410HF N P83CL410HF N –40 to +85, 40-Pin Plastic Dual In-line Package 32kHZ to 12MHz SOT129-1 P80CL410HFT P83CL410HFT P80CL410HF D P83CL410HF D –40 to +85, 40-Pin Plastic Very Small Outline Package 32kHZ to 12MHz SOT158-1 –40 to +85, 44-Pin Plastic Quad Flat Pack 32kHZ to 12MHz SOT307-2 P83CL410HFH NOTE: 1. Parts ordered by the Philips North America part number will be marked with the Philips part marking. For emulation purposes, the P85CL000 (Piggyback version) with 256 bytes of RAM is recommended. 1995 Jan 20 2 FREQUENCY Drawing Number Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C PLASTIC QUAD FLAT PACK PIN FUNCTIONS 44 80CL410/83CL410 LOGIC SYMBOL VDD 34 VSS XTAL1 33 Port 0 1 Address and Data Bus QFP XTAL2 RST EA Pin Function 1 2 Function P1.5/INT7 P1.6/INT8/SCL 23 24 P2.5/A13 P2.6/A14 3 P1.7/INT9/SDA 25 P2.7/A15 4 RST 26 PSEN 5 P3.0 27 ALE 6 NC 28 NC 7 8 P3.1 P3.2/INT0 29 30 EA P0.7/AD7 9 P3.3/INT1 31 P0.6/AD6 10 P3.4/T0 32 P0.5/AD5 11 P3.5/T1 33 P0.4/AD4 12 13 P3.6/WR P3.7/RD 34 35 P0.3/AD3 P0.2/AD2 14 XTAL2 36 P0.1/AD1 15 XTAL1 37 P0.0/AD0 16 VSS 38 VDD 17 18 NC P2.0/A8 39 40 NC P1.0/INT2 19 P2.1/A9 41 P1.1/INT3 20 P2.2/A10 42 P1.2/INT4 21 P2.3/A11 43 P1.3/INT5 22 P2.4/A12 44 P1.4/INT6 1995 Jan 20 PSEN ALE INT0 INT1 T0 T1 WR RD 3 Port 3 Pin 22 Alternate Functions 12 Port 1 23 Port 2 11 INT2 INT3 INT4 INT5 INT6 INT7 INT8/SCL INT9/SDA Address Bus Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 BLOCK DIAGRAM FREQUENCY REFERENCE XTAL2 COUNTER (1) XTAL1 OSCILLATOR AND TIMING T0 PROGRAM MEMORY (4K × 8 ROM) DATA MEMORY (128 × 8 RAM) T1 TWO 16-BIT TIMER/EVENT COUNTERS CPU 10 3 INTERNAL INTERRUPTS EXTERNAL INTERRUPTS (1) 64K BYTE BUS EXPANSION CONTRTOL CONTROL PROGRAMMABLE I/O PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS I2C-BUS SERIAL I/O SDA SCL (1) (1) Pins shared with parallel port pins. 1995 Jan 20 4 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 PIN DESCRIPTION PIN NO. MNEMONIC DIL40/ VSO40 TYPE QFP NAME AND FUNCTION VSS 16 20 I Ground: 0V reference. VDD 38 40 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 30–37 39–32 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. P1.0–P1.7 40–44 1–3 1–8 I/O 7 8 1–8 I/O I/O I Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Additional functions include: SCL (P1.6): I2C serial bus clock. SDA (P1.7): I2C serial bus data. INT2–INT9 (P1.0–P1.7): Additional external interrupts. P2.0–P2.7 18–25 21–28 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0–P3.7 5, 7–13 10–17 I/O 8 9 10 11 12 13 12 13 14 15 16 17 I I I I O O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: INT0 (P3.2): External interrupt 0 INT1 (P3.3): External interrupt 1 T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe RST 4 9 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. ALE 27 30 O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. PSEN 26 29 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 29 31 I External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 0FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. XTAL1 15 19 I Crystal 1: Input to the inverting oscillator amplifier and input for an external clock source. XTAL2 14 18 O Crystal 2: Output from the inverting oscillator amplifier. 1995 Jan 20 5 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 Table 1. 8XCL410 Special Function Registers SYMBOL DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H DPTR: Data pointer (2 bytes): High byte Low byte 83H 82H DPH DPL 00H 00H BF IP0*# Interrupt priority 0 B8H BE BD BC BB BA B9 B8 – – PS1 – PT1 PX1 PT0 PX0 FF FE FD FC FB FA F9 F8 PX7 PX6 PX5 PX4 PX3 PX2 xx000000B IP1*# Interrupt priority 1 F8H PX9 PX8 AF AE AD AC AB AA A9 A8 IEN0*# Interrupt enable 0 A8H EA – ES1 – ET1 EX1 ET0 EX0 EF EE ED EC EB EA E9 E8 IEN1*# Interrupt enable 1 E8H EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2 C7 C6 C5 C4 C3 C2 C1 C0 IRQ1*# Interrupt request flag C0H IQ9 IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 IX1# Interrupt polarity E9H P0* Port 0 80H 87 86 85 84 83 82 81 80 FFH P1* Port 1 90H 97 96 95 94 93 92 91 90 FFH P2* Port 2 A0H A7 A6 A5 A4 A3 A2 A1 A0 FFH P3* Port 3 B0H B7 B6 B5 B4 B3 B2 B1 B0 FFH PCON Power control 87H SMOD – – – GF1 GF0 PD IDL 0xxx0000B D7 D6 D5 D4 D3 D2 D1 D0 CY AC F0 RS1 RS0 OV – P DF DE DD DC DB DA D9 D8 – ENS1 STA STO SI AA CR1 CR0 PSW* Program status word D0H S1ADR# Slave address DBH 00H 00H 00H 00H 00H 00H 00H S1CON*# Serial control D8H S1DAT# S1STA# Serial data Serial status DAH D9H 00H 11111000B SP Stack pointer 81H 07H 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer/counter control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H TMOD Timer/counter mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H TH0 Timer 0 high byte 8CH 00H TH1 Timer 1 high byte 8DH 00H TL0 Timer 0 low byte 8AH 00H TL1 Timer 1 low byte 8BH * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1995 Jan 20 x0000000B 00H 6 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C PORT OPTIONS The pins of port 1 (not P1.6/SCL or P1.7/SDA), port 2, and port 3 may be individually configured with one of the following port options (see Figure 1): 80CL410/83CL410 Two cases have to be examined. First, accesses to external memory (EA = 0 or access above the built-in memory boundary), and second, I/O accesses. External Memory Accesses Option 1: Standard Port— quasi-bidirectional I/O with pull-up. The strong booster pull-up p1 is turned on for two oscillator periods after a 0-to-1 transition in the port latch. See Figure 1(a). Option 1: True 0 and 1 are written as address to the external memory (strong pull-up is used). Option 2: Open Drain—quasi-bidirectional I/O with n-channel open drain output. Use as an output requires the connection of an external pull-up resistor. See Figure 1(b). Option 3: Not allowed for external memory accesses as the port can only be used as output. Option 3: Push-Pull—output with drive capability in both polarities. Under this option, pins can only be used as outputs. See Figure 1(c). The definition of port options for port 0 is slightly different. Option 2: An external pull-up resistor is needed for external accesses. I/O Accesses Option 1: When writing a 1 to the port latch, the strong pull-up p1 will be on for two oscillator periods. No weak pull-up exists. Without an external pull-up, this option can be used as a high-impedance input. Option 2: Open drain—quasi-bidirectional I/O with n-channel open drain output. Use as an output requires the connection of an external pull-up resistor. See Figure 1(c). Option 3: Push-Pull—output with drive capability in both polarities. Under this option, pins can only be used as outputs. Individual mask selection of the post-reset state is available on any of the above pins. Make your selection by appending “S” or “R” to option 1, 2, or 3 above (e.g., 1S for a standard I/O to be set after RESET or 2R for an open-drain I/O to be reset after RESET. Option S: Set—after reset, this pin will be initialized High. Option R: Reset—after reset, this pin will be initialized Low. STRONG PULL-UP +5V TWO OSCILLATOR PERIODS P2 P1 P3 I/O PIN N (a) Q FROM PORT LATCH INPUT DATA READ PORT PIN INPUT BUFFER +5V EXTERNAL PULL-UP I/O PIN N (b) Q FROM PORT LATCH INPUT DATA READ PORT PIN INPUT BUFFER STRONG PULL-UP +5V P1 (c) I/O PIN N Q FROM PORT LATCH Figure 1. Ports 1995 Jan 20 7 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C POWER-DOWN MODE The instruction setting PCON.1 is the last executed prior to going into the power-down mode. In power-down mode, the oscillator is stopped. The contents of the the on-chip RAM and SFRs are preserved. The port pins output the values held by their respective SFRs. ALE and PSEN are held low. In the power-down mode, VDD may be reduced to minimize power consumption. However, the supply voltage must not be reduced until the power-down mode is active, and must be restored before the hardware reset is applied and frees the oscillator. Reset must be held active until the oscillator has restarted and stabilized. From the power-down mode the part can be restarted by using either the wake-up mode or the Reset Mode. Wake-Up Mode Setting both PD and IDL bits in the PCON register forces the controller into the power-down mode. Setting both bits enable the controller to be woken-up from the power-down mode via either an enabled external interrupt INT2–INT9, or a reset operation. An external interrupt for an enabled interrupt INT2–INT9 at port 1 starts both the oscillator and the delay counter. To ensure that the oscillator is stable before the controller restarts, the internal clock will remain inactive for 1536 oscillator periods after the interrupt Table 2. 80CL410/83CL410 is detected. This is controlled by the on-chip delay counter. After this, the PD flag will be reset, the controller is now in the Idle mode and the interrupt will be handled in the normal way. Reset Mode Setting only the PD bit in the PCON register again forces the controller into the power-down mode, but in this case it can only be restored to normal operation with a direct reset operation. To restore normal operation, the RESET pin has to be kept High for a minimum of 24 oscillator periods. The on-chip delay counter is inactive. The user has to insure that the oscillator is stable before any operation is attempted. Figure 2 illustrates the two possibilities for wake-up. IDLE MODE The instruction that sets PCON.0 is the last instruction executed before going into idle mode. In idle mode, the internal clock is stopped for the CPU, but not for the interrupt, timer, and serial port functions. The CPU status is preserved along with the stack pointer, program counter, program status word and accumulator. The RAM and all other registers maintain their data during idle mode. The port pins retain the logical states they held at idle mode activation. ALE and PSEN hold at the logic high level. There are two methods used to terminate the idle mode. Activation of any interrupt will cause PCON to be cleared by hardware; terminating idle mode. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device in the the idle mode. Flag bits GF0 and GF1 can be used to determine whether the interrupt was received during normal execution or idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. The second method of terminating the idle mode is with an external hardware reset. Since the oscillator is still running, the hardware reset is required to be active for only two machine cycles to complete the reset operation. Reset redefines all SFRs, but does not affect the state of the on-chip RAM. The status of the external pins during idle and power-down mode is shown in Table 2. If the power-down mode is activated while accessing external memory, port data held in the special function register P2 is restored to port 2. If the data is a logic 1, the port pin is held high during the power-down mode. External Pin Status During Idle and Power-Down Modes MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 Idle Internal 1 Idle External 1 Power-down Internal 0 Power-down External 0 PORT 2 PORT 3 1 Data 1 Floating Data Data Data Data Address Data 0 0 Data Data Data Data Floating Data Data Data POWER-DOWN RESET PIN EXTERNAL INTERRUPT OSCILLATOR > 24 PERIODS DELAY COUNTER 1536 PERIODS Figure 2. Wake-Up Operation 1995 Jan 20 8 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 SLAVE ADDRESS GC S1ADR SHIFT REGISTER SDA BUS CLOCK GENERATOR SCL 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 INTERNAL BUS S1DAT ARBITRATION LOGIC S1CON 7 S1STA Figure 3. Serial I/O I2C-BUS SERIAL I/O AA The serial port supports the twin line I2C-bus. The I2C-bus consists of a data line (SDA) and a clock line (SCL). These lines also function as I/O port lines P1.7 and P1.6 respectively. The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. The I2C-bus serial I/O has complete autonomy in byte handling and operates in four modes: – Master transmitter – Master receiver – Slave transmitter – Slave receiver These functions are controlled by the S1CON register. S1STA is the status register whose contents may also be used as a vector to various service routines. S1DAT is the data shift register and S1ADR the slave address register. Slave address recognition is performed by hardware. S1CON (D8H) Serial control register CR2 ENS1 STA STO SI AA CR1 CR0 CR0, CR1, CR2 These three bits determine the serial clock frequency when SIO is in a master mode. 1995 Jan 20 Assert acknowledge bit. When the AA flag is set, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: – own slave address is received – general call address is received (S1ADR.0 = 1) – data byte received while device is programmed as master – data byte received while device is selected slave With AA = 0, no acknowledge will be returned. Consequently, no interrupt is requested when the “own slave address” or general call address is received. SI SIO interrupt flag. When the SI flag is set, an acknowledge is returned after any one of the following conditions: – a start condition is generated in master mode – own slave address received during AA = 1 – general call address received while S1ADR.0 and AA = 1 – data byte received or transmitted in master mode (even if arbitration is lost) – data byte received or transmitted as selected slave – stop or start condition received as selected slave receiver or transmitter 9 STO STOP flag. With this bit set while in master mode, a STOP condition is generated. When a STOP condition is detected on the bus, the SIO hardware clears the STO flag. In the slave mode, the STO flag may also be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C-bus. However, the SIO hardware behaves as if a STOP condition has been received and releases SDA and SCL. The SIO then switches to the “not addressed” slave receiver mode. The STO flag is automatically cleared by hardware. STA START flag. When the STA bit is set in slave mode, the SIO hardware checks the status of the I2C-bus and generates a START condition if the bus is free. If STA is set while the SIO is in master mode, SIO transmits a repeated START condition. ENS1 When ENS1 = 0, the SIO is disabled. The SDA and SCL outputs are in a high-impedance state; P1.6 and P1.7 function as open drain ports. When ENS1 = 1, the SIO is enabled. The P1.6 and P1.7 port latches must be set to logic 1. Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C S1STA (D9H) Status register SC4 SC3 SC2 SC1 SC0 0 0 0 S1STA is an 8-bit read-only special function register. S1STA.3–S1STA.7 hold a status code. S1STA.0–S1STA.2 are held LOW. The contents of S1STA may be used as a vector to a service routine. This optimizes response time of the software and consequently that of the I2C-bus. The following is a list of the status codes: Abbreviations used: SLA: 7-bit slave address R: Read bit W: Write bit ACK: Acknowledgement (acknowledge bit = 0) ACK: Not Acknowledge (acknowledge bit = 1) DATA: 8-bit byte to or from the I2C-bus MST: Master SLV: Slave TRX: Transmitter REC: Receiver MST/REC mode S1STA value SLV/TRX mode S1STA value 08H – a START condition has been transmitted 10H – a repeated START condition has been transmitted 38H – Arbitration lost while returning ACK 40H – SLA and R have been transmitted, ACK received 48H – SLA and R have been transmitted, ACK received 50H – DATA has been received, ACK returned 58H – DATA has been received, ACK returned A8H – Own SLA and R have been received, ACK returned B0H – Arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK returned B8H – DATA byte has been transmitted, ACK received C0H – DATA byte has been transmitted, ACK received C8H – Last DATA byte has been transmitted (AA = logic 0), ACK received SLV/REC mode S1STA value MST/TRX mode S1STA value 08H – a START condition has been transmitted 10H – a repeated START condition has been transmitted 18H – SLA and W have been transmitted, ACK received 20H – SLA and W have been transmitted, ACK received 28H – DATA of S1DAT has been transmitted, ACK received 30H – DATA of S1DAT has been transmitted, ACK received 38H – Arbitration lost in SLA, R/W or DATA Table 3. 80CL410/83CL410 60H – Own SLA and W have been received, ACK returned 68H – Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned 70H – General CALL has been received, ACK returned 78H – Arbitration lost in SLA, R/W as MST. General CALL has been received 80H – Previously addressed with own SLA. DATA byte received, ACK returned 88H – Previously addressed with own SLA. DATA byte received, ACK returned 90H – Previously addressed with general CALL. DATA byte has been received, ACK has been returned 98H – Previously addressed with general CALL. DATA byte has been received, ACK has been returned A0H – A STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX Miscellaneous S1STA value 00H – Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition F8H – No relevant state interruption available, SI = 0. S1DAT (DAH) Data Shift Register 7 6 5 4 3 2 1 Data shift register S1DAT This register contains the serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first, i.e., data is shifted from left to right. S1ADR (DBH) Slave Address Register 7 6 5 4 3 2 1 0 S1ADR.0, GC: 0 = general CALL address is not recognized 1 = general CALL address is recognized S1ADR.7-1: own slave address This 8-bit register may be loaded with the 7-bit slave address, to which the controller will respond when programmed as a slave receiver/transmitter. The LSB bit (GC) is used to determine whether the general CALL address is recognized. SCL Frequency BIT RATE (kHz) at fOSC CR2 CR1 CR0 fOSC DIVIDED BY 3.58MHz 6MHz 12MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 256 224 192 160 960 120 60 not allowed 14.0 16.0 18.6 22.4 3.73 29.8 59.7 – 23.4 26.8 31.3 37.5 6.25 50 100 – 46.9 53.6 62.5 75.0 12.5 100 – – 1995 Jan 20 0 10 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C INTERRUPT SYSTEM External events and the real-time-driven on-chip peripherals require service by the CPU asynchronous to the execution of any particular section of code. To tie the asynchronous activities of these functions to normal program execution, a multiple-source, two-priority level, nested interrupt system is provided. The 8XCL410 acknowledges interrupt requests from thirteen sources, as follows: – INT0 and INT1 – Timer 0 and timer 1 – I2C-bus serial I/O interrupt – INT2 to INT9 (port 1) Each interrupt vectors to a separate location in program memory for its service routine. Each source can be individually enabled or disabled by corresponding bits in the internal enable registers (IEN0, IEN1) The priority level is selected via the interrupt priority register (IP0, IP1). All enabled sources can be globally disabled or enabled. External Interrupts INT2–INT9 Port 1 lines serve an alternative purpose as eight additional interrupts INT2–INT9. When enabled, each of these lines can “wake-up” the device from power-down mode. Using the IX1 register, each pin may be initialized to either active high or low. IRQ1 is the interrupt request flag register. Each flag, if the interrupt is enabled, will be set on an interrupt request but it must be cleared by software. IEN1 (E8H) Interrupt enable register 7 6 5 4 3 2 1 0 EA — ES1 — ET1 EX1 ET0 EX0 Bit Symbol Function IEN0.7 EEA General enable/disable control 0 = no interrupt is enabled 1 = any individually enabled interrupt will be accepted IEN0.6 — (unused) IEN0.5 ES1 Enable I2C SIO interrupt IEN0.4 — (unused) IEN0.3 ET1 Enable Timer T1 interrupt IEN0.2 EX1 Enable external interrupt 1 IEN0.1 ET0 Enable Timer T0 interrupt IEN0.0 EX0 Enable external interrupt 0 IX1 (E9H) Interrupt polarity register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2 IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 Bit Symbol Function IEN1.7 EX9 Enable external interrupt 9 IEN1.6 EX8 Enable external interrupt 8 IEN1.5 EX7 Enable external interrupt 7 IEN1.4 EX6 Enable external interrupt 6 IEN1.3 EX5 Enable external interrupt 5 IEN1.2 EX4 Enable external interrupt 4 IEN1.1 EX3 Enable external interrupt 3 IEN1.0 EX2 Enable external interrupt 2 6 5 4 3 2 1 0 — — PS1 — PT1 PX1 PT0 PX0 IP0.2 IP0.1 7 6 5 4 3 2 1 0 PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2 IP1.6 IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0 Symbol Function PX9 External interrupt 9 priority level PX8 External interrupt 8 priority level PX7 External interrupt 7 priority level PX6 External interrupt 6 priority level PX5 External interrupt 5 priority level PX4 External interrupt 4 priority level PX3 External interrupt 3 priority level PX2 External interrupt 2 priority level Interrupt priority is as follows: 0 – low priority 1 – high priority 1995 Jan 20 11 IX1.4 IX1.0 Symbol Function IL9 External interrupt 9 polarity level IL8 External interrupt 8 polarity level IL7 External interrupt 7 polarity level IL6 External interrupt 6 polarity level IL5 External interrupt 5 polarity level IL4 External interrupt 4 polarity level IL3 External interrupt 3 polarity level IL2 External interrupt 2 polarity level Writing either a “1” or “0” to an IX1 register bit sets the priority level of the corresponding external interrupt to active High or Low, respectively. Symbol Function — (unused) — (unused) PS1 I2C SIO interrupt priority level — (unused) PT1 Timer 1 interrupt prioity level PX1 External interrupt 1 priority level PT0 Timer 0 interrupt prioity level PX0 External interrupt 0 priority level IP1 (F8H) Interrupt priority register Bit IP1.7 IX1.5 IX1.1 7 IP0.4 IP0.3 IX1.6 IX1.2 IP0 (B8H) Interrupt priority register Bit IP0.7 IP0.6 IP0.5 Bit IX1.7 IX1.3 where 0 = interrupt disabled 1 = interrupt enabled IP0.0 IEN0 (A8H) Interrupt enable register 80CL410/83CL410 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C IRQ1 (C0H) Interrupt request flag register 7 6 5 4 3 2 1 0 IQ9 IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 Bit Symbol Function IRQ1.7 IQ9 External interrupt 9 request flag IRQ1.6 IQ8 External interrupt 8 request flag IRQ1.5 IQ7 External interrupt 7 request flag IRQ1.4 IQ6 External interrupt 6 request flag IRQ1.3 IQ5 External interrupt 5 request flag IRQ1.2 IQ4 External interrupt 4 request flag IRQ1.1 IQ3 External interrupt 3 request flag IRQ1.0 IQ2 External interrupt 2 request flag Priority X0 (highest) S1 X5 T0 X6 X1 X2 X7 T1 X3 X8 X4 X9 (lowest) Vector 0003H 002BH 0053H 000BH 005BH 0013H 003BH 0063H 001BH 0043H 006BH 004BH 0073H Source External 0 I2C port External 5 Timer 0 External 6 External 1 External 2 External 7 Timer 1 External 3 External 8 External 4 External 9 OSCILLATOR CIRCUITRY Power-on Reset The on-chip oscillator circuitry of the 8XCL410 is a single stage inverting amplifier biased by an internal feedback resistor. (See Figure 4.) The oscillator can be operated with a quartz crystal, ceramic resonator, LC network or RC network. See Figure 5 for different configurations. When ordering parts, it is necessary to specify an oscillator option. The options are: RC when an RC network will be used, OSC 2 for oscillator operation below 4MHz, OSC 3 for oscillator operation from 4MHz to 10MHz, OSC 4 for oscillator operation above 10MHz, and 32kHz if 32kHz to 400kHz operation is desired. The 8XCL410 contains on-chip circuitry which switch the port pins to the customer-defined logic level as soon as VDD exceeds 1.3V if the mask option “ON” has been chosen (see Figures 8 and 9). As soon as the minimum supply voltage is reached, the oscillator will start up. However, to ensure that the oscillator is stable before the controller starts, the clock signals are gated away from the CPU for a further 1536 oscillator periods. For operation as a standard quartz oscillator, no external components are needed (except at 32KHz). When using external capacitors, ceramic resonators, coils, and RC networks to drive the oscillator, five different configurations are supported (see Figure 5 and Table 4). In the power-down mode the oscillator is stopped and XTAL1 is pulled high. The oscillator inverter is switched off to ensure no current will flow. To drive the device with an external clock source, apply the external clock signal to XTAL1, and leave XTAL2 to float, as shown in Figure 5(f). There are no requirements on the duty cycle of the external clock, since the input to the internal clocking circuitry is split using a flip-flop. The following options are provided for optimum on-chip oscillator performance. Please state option when ordering: Osc.1: Register Function IX1 Interrupt polarity register IRQ1 Interrupt request flag register IEN0 Interrupt enable register IEN1 Interrupt enable register (INT2–INT9) IP0 Interrupt priority register IP1 Interrupt priority register (INT2–INT9) SFR Address E9H C0H A8H E8H B8H F8H 80CL410/83CL410 Figure 5(c). An option for 32kHz clock applications with external trimmer for frequency adjustment. A 4.7MΩ bias resistor must be connected in parallel with the crystal. Osc.2: Figure 5(e). An option for low-power, low-frequency operations using LC components or quartz. Osc.3: An option for medium frequency range applications. Osc.4: An option for high frequency range applications. RC: Figure 5(g). An option for an RC oscillator. The equivalent circuit data of the internal oscillator compares with that of matched crystals. The externally adjustable RC oscillator has a frequency range from 100kHz to 500kHz. (See Figure 7.) 1995 Jan 20 12 An hysteresis of approximately 50mV at a typical power-on switching level of 1.3V will ensure correct operation. The on-chip power–on reset circuitry can also be switched off via the mask option “OFF”. This option reduces the power-down current to typically 800µA and can be chosen if external reset circuitry is used. For applications not requiring the internal reset, option “OFF” should be chosen. An automatic reset can be obtained at power-on by connecting the RST pin to VDD via a 10µF capacitor. At power-on, the voltage on the RST pin is equal to VDD minus the capacitor voltage, and decreases from VDD as the capacitor discharges through the internal resistor RRST to ground. The larger the capacitor, the more slowly VRST decreases. VRST must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start-up time, plus 2 machine cycles. P80CL410: ROM-less VERSION OF P83CL410 The P80CL410 is a low voltage ROMless version of the P83CL410. The mask options on the P80CL410 are fixed as follows: • Port Options: All ports except P16/P17 have option “1S”, i.e., standard port, High after reset. The ports P16/P17 have option “2S”, i.e., open drain, High after reset. • Oscillator option: OSC3 • Power-on Reset option: OFF Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 VDD To internal timing circuits PD VDD VDD Rbias C2i C1i XTAL1 XTAL2 Figure 4. Oscillator XTAL1 XTAL2 XTAL1 XTAL1 XTAL2 XTAL2 4.7 MEG (a) Oscillator Configuration for Quartz Crystal XTAL1 (b) Quartz Oscillator with External Capacitors (d) Configuration for Ceramic Resonator XTAL2 XTAL1 XTAL2 (c) Configuration for 32kHz Operation XTAL1 XTAL2 N.C. N.C. VDD (e) Configuration for LC Network (f) External Clock Configuration Figure 5. Oscillator Configurations 1995 Jan 20 13 (g) RC Network Configuration Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C Table 4. 80CL410/83CL410 Oscillator Type Selection Guide C1 EXT. C2 EXT. MAXIMUM RESONATOR RESONATOR f (MHz) OPTION MIN MAX MIN MAX SERIES RESISTANCE Quartz 0.032 Osc.1 5 15 0 0 15kΩ1 Quartz 1.0 Osc.2 0 30 0 30 600Ω Quartz 3.58 Osc.2 0 15 0 15 100Ω Quartz 4.0 Osc.2 0 20 0 20 75Ω Quartz 6.0 Osc.3 0 10 0 10 60Ω Quartz 10.0 Osc.4 0 15 0 15 60Ω Quartz 12.0 Osc.4 0 10 0 10 40Ω Quartz 16.0 Osc.4 0 15 0 15 20Ω PXE 0.455 Osc.2 40 50 40 50 10Ω PXE 1.0 Osc.2 15 50 15 50 100Ω PXE 3.58 Osc.2 0 40 0 40 10Ω PXE 4.0 Osc.2 0 40 0 40 10Ω PXE 6.0 Osc.2 0 20 0 20 5Ω PXE 10.0 Osc.3 0 15 0 15 6Ω PXE 12.0 Osc.4 10 40 10 40 6Ω Osc.2 20 90 20 90 10µH = 1Ω 100µH = 5Ω 1mH = 75Ω LC NOTE: 1. 32kHz quartz crystals with a series resistance higher than 15kΩ will reduce the guaranteed supply voltage range to 2.5 to 3.5V. Table 5. Oscillator Equivalent Circuit Parameters (see Figure 6) OPTION SYMBOL CONDITION MIN TYP MAX UNIT Transconductance PARAMETER Osc.1 Osc.2 Osc.3 Osc.4 gm gm gm gm T = +25°C; VDD = 4.5V T = +25°C; VDD = 4.5V T = +25°C; VDD = 4.5V T = +25°C; VDD = 4.5V – 200 400 1000 15 600 1500 4000 – 1000 4000 10000 µs µs µs µs Input capacitance Osc.1 Osc.2 Osc.3 Osc.4 c1i c1i c1i c1i – – – – 3.0 8.0 8.0 8.0 – – – – pF pF pF pF Output capacitance Osc.1 Osc.2 Osc.3 Osc.4 c2i c2i c2i c2i – – – – 23.0 8.0 8.0 8.0 – – – – pF pF pF pF Output resistance Osc.1 Osc.2 Osc.3 Osc.4 R2 R2 R2 R2 – – – – 3800 65 18 5.0 – – – – kΩ kΩ kΩ kΩ 1995 Jan 20 14 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 Rf XTAL1 XTAL2 C1i V1 gm R2 C2i Figure 6. Equivalent Circuit Diagram 600 400 fOSC (kHz) 200 0 0 2 RC (µs) 4 6 Figure 7. Frequency as a Function of RC SWITCHING LEVEL PDR HYSTERESIS SUPPLY VOLTAGE POWER-ON RESET (INTERNAL) OSCILLATOR CPU RUNNING START-UP 1536 OSCILLATOR TIME PERIODS DELAY Figure 8. Power-on Reset Switching Level 1995 Jan 20 15 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 VCC VCC + 8XCL410 10µF RST RRST Figure 9. Recommended Power-on Reset Circuitry ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Supply voltage RATING UNIT –0.5 to +6.5 V –0.5 to VDD +0.5 V 5 mA 300 mW Storage temperature range –65 to +150 °C Operating ambient temperature range –40 to +85 °C 125 °C All input voltages DC current into any input or output Total power dissipation Operating junction temperature NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 1995 Jan 20 16 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 DC ELECTRICAL CHARACTERISTICS Tamb = –40°C to +85°C, VSS = 0V TEST SYMBOL PARAMETER LIMITS CONDITIONS MIN MAX UNIT fCLK (see Figure 13) 1.8 1.0 6.0 — V V VDD Supply voltage RAM retention voltage in power-down mode IDD Power supply current: Operating1 OSC 1 option OSC 2 option OSC 2 option OSC 3 option OSC 4 option fCLK = 32kHz, VDD = 1.8V, Tamb = +25°C fCLK = 3.58MHz, VDD = 3V fCLK = 10MHz, VDD = 5V fCLK = 12MHz, VDD = 5V fCLK = 12MHz, VDD = 5V — — — — — 50 2.5 14 16 20 µA mA mA mA mA Idle mode2 OSC 1 option OSC 2 option OSC 2 option OSC 3 option OSC 4 option fCLK = 32kHz, VDD = 1.8V, Tamb = +25°C fCLK = 3.58MHz, VDD = 3V fCLK = 10MHz, VDD = 5V fCLK = 12MHz, VDD = 5V fCLK = 12MHz, VDD = 5V — — — — — 25 1.0 5.0 7.0 8.5 µA mA mA mA mA VDD = 1.8V, Tamb = +25°C — 10 µA VSS 0.3VDD V 0.7VDD VDD Power-down mode3 VIL Input low voltage VIH Input high voltage IOL Output sink current, except SDA, SCL IOL1 Output sink current, SDA, SCL IOH Output source current (push-pull options only) IIL Logical 0 input current, ports 1, 2, 3 ITL Logical 1-to-0 transition current, ports 1, 2, 3 ILI Input leakage current, port 0, EA RRST Internal reset pull-down resistor V VDD = 5V, VOL = 0.4V VDD = 2.5V, VOL = 0.4V 1.6 0.7 mA mA VDD = 5V, VOL = 0.4V 3.0 mA VDD = 5V, VOH = VDD – 0.4V VDD = 2.5V, VOH = VDD – 0.4V 1.6 0.7 mA mA VDD = 5V,VIN = 0.4V VDD = 2.5V,VIN = 0.4V –100 –50 µA µA VDD = 5V, VIN = VDD/2 VDD = 2.5V, VIN = VDD/2 –1.0 –500 mA µA VSS < VI < VDD ±10 µA 200 kΩ 10 NOTES: 1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS, VIH = VDD; XTAL2 not connected; EA = RST = Port 0 = VDD; all open drain outputs connected to VSS. 2. The idle supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS, VIH = VDD; XTAL2 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS. 3. The power-down current is measured with all output pins disconnected; XTAL1 not connected; EA = port 0 = VDD; RST = VSS; all open-drain outputs connected to VSS. 4. The RC-oscillator is not implemented in this version. 5. Circuits with “power-on reset” option “OFF” are tested at VDDMIN = 1.8V, with option “ON” (typically 1.3V) are tested at VDDMIN = 2.3V. 1995 Jan 20 17 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 1.8 1.6 1.4 1.2 1.0 IDD (mA) 1.2MHz 0.8 0.6 0.4 32kHz 0.2 0 0 1 2 3 4 5 6 VDD MIN = 1.8V VDD (V) Typical Operating Current Versus Supply and Frequency (32kHz–1.2MHz) at +25°C 1995 Jan 20 18 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 AC ELECTRICAL CHARACTERISTICS Tamb = –40°C to +85°C, VSS = 0V1, 2 SYMBOL FIGURE PARAMETER 12MHz CLOCK VARIABLE CLOCK MIN MIN MAX UNIT 0 20 MHz MAX Program Memory 1/tCLCL Oscillator frequency tLL 10 ALE pulse width 127 2tCLCL–40 ns tAL 10 Address valid to ALE low 43 tCLCL–40 ns tLA 10 Address hold after ALE low 48 tCLCL–35 ns tLIV 10 ALE low to valid instruction in tLC 10 ALE low to PSEN low 58 tCC 10 PSEN pulse width 215 tCIV 10 PSEN low to valid instruction in tCI 10 Input instruction hold after PSEN tCIF 10 Input instruction float after PSEN 63 tCLCL–20 ns tAVI 10 Address to valid instruction in 302 5tCLCL–115 ns tAFC 10 PSEN low to address float tRR 11 tWW 12 tLA 11, 12 tRD 11 RD low to valid data in tDFR 11 tLD tAD tLW 11, 12 ALE low to RD or WR low 200 tAW 11, 12 Address valid to WR low or RD low 203 4tCLCL–130 ns tCLCL–60 ns 233 4tCLCL–100 tCLCL–25 ns 3tCLCL–35 125 0 ns ns 3tCLCL–125 0 ns ns 0 0 ns RD pulse width 400 6tCLCL–100 ns WR pulse width 400 6tCLCL–100 ns Address hold time after ALE 48 Data Memory – ns 250 5tCLCL–165 ns Data float after RD 97 2tCLCL–70 ns 11 ALE low to valid data in 517 8tCLCL–150 ns 11 Address to valid data in 585 9tCLCL–165 ns 3tCLCL+50 ns tDWX 12 Data valid to WR transition 23 tDW 11 Data valid to WR 433 tWD 12 Data hold after WR tAFR tWHLH 11 11, 12 RD low to address – 300 – 33 float3 tCLCL–35 3tCLCL–50 7tCLCL–150 tCLCL–50 12 RD or WR high to ALE high 43 – 123 tCLCL–40 ns ns 12 ns tCLCL+40 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 50pF, load capacitance for all other outputs = 40pF. 3. Interfacing the 8XCL410 to devices with float time up to 75ns is permitted. This limited bus connection will not cause damage to port 0 drivers. 1995 Jan 20 19 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 tLL ALE tCC tAL tLC tLIV tCIV PSEN tLA tCIF tAFC tCI INSTR IN A0–A7 PORT 0 A0–A7 tAVI PORT 2 A8–A15 A8–A15 Figure 10. External Program Memory Read Cycle ALE tWHLH PSEN tLD tLW tRR RD tAL PORT 0 tDFR tLA tAFR A0–A7 FROM RI OR DPL DATA IN tAW A0–A7 FROM PCL tRD tAD PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH Figure 11. External Data Memory Read Cycle 1995 Jan 20 20 A8–A15 FROM PCH INSTR IN Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 ALE tWHLH PSEN tWW tLW WR tAL tDWX tLA A0–A7 FROM RI OR DPL PORT 0 tWD tDW DATA OUT A0–A7 FROM PCL tAW PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH Figure 12. External Data Memory Write Cycle 0.7 VDD 0.7 VDD 0.9 VDD TEST POINTS 0.4 VDD 0.3 VDD 0.3 VDD Figure 13. AC Testing Input Waveform ITL 500µA –IIL IIL 100µA 0 VDD/2 Figure 14. Input Current 1995 Jan 20 21 VDD INSTR IN Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C f (MHz) 80CL410/83CL410 100 16 10 12 IDD (mA) 1 8 12MHz 4 0.1 8MHz 3.58MHz 0 0.01 0 1 2 3 4 5 6 1 7 2 4 3 VDD (V) 5 6 VDD (V) NOTE: Below 32kHz, clock has to be supplied externally. Figure 16. Typical Operating Current as a Function of Frequency and VDD, Tamb = 25°C Figure 15. Frequency Operating Range 8 5 4 6 3 fIDLE IPD (µA) (mA) 12MHz 4 2 2 8MHz 1 3.58MHz 0 0 1 2 3 4 5 6 0 VDD (V) 2 3 4 5 VDD (V) Figure 17. Typical Idle Current as a Function of Frequency and VDD, Tamb = 25°C 1995 Jan 20 1 Figure 18. Typical Power-Down Current Vs. Frequency and VDD, Tamb = 25oC 22 6 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C PIGGYBACK SPECIFICATION The differences between the masked version and the piggyback are described herein. General Description 80CL410/83CL410 Features • Full static 80C51 CPU • 8-bit CPU, RAM, I/O in a single 40-lead DIP The P85CL000HFZ is a piggy-back version with 256 bytes of RAM used for emulation of the P83CL410 microcontroller. The P85CL000HFZ is manufactured in an advanced CMOS technology. The instruction set of the P85CL000HFZ is based on that of the 8051. The device has low power consumption and a wide supply voltage range. The P85CL000HFZ has two software selectable modes of reduced activity for further power reduction: Idle and Power-down. For timing and AC/DC characteristics, please refer to the P83CL410 specifications. • Socket for up to 16k external EPROM • 256 bytes RAM, expandable externally to 64K bytes • Four 8-bit ports, 32 I/O lines • Two 16-bit timer/event counters • External memory expandable up to 128K, external ROM up to 64K and/or RAM up to 64K • Thirteen source, thirteen vector interrupt structure with two priority levels • Enhanced architecture with: – non-page oriented instructions – direct addressing – four eight byte RAM register banks – stack depth up to 128 bytes – multiply, divide, subtract and compare instructions • STOP and IDLE instructions • Wake-up via external interrupts at port 1 • Single supply voltage of 1.8V to 6.0V • On-chip oscillator (option: oscillator 4) • Very low current consumption • Operating temperature range: –40 to +85°C • Full duplex serial port (UART) • I2C-bus interface for serial transfer on two lines STANDARD PIGGYBACK Types: P85CL000HFZ Emulation for: P83CL410, P80CL51 List of differences between masked microcontroller and corresponding piggyback: PARAMETER MASKED CONTROLLER PIGGYBACK RAM size 128 256 ROM size 4k EPROM size dependent (max 16k) Port option 1, 2, 3 1 Oscillator option Osc. 1, 2, 3, 4, RC Osc. 4 Mech. dimensions Standard Dual In-Line, Small Outline See SOT158A Current cons. IDD IDD (OSC. 4) + IEPROM Voltage range full full, limited by EPROM ESD specification not tested (different package) Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. 1995 Jan 20 23 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 DIP40: plastic dual in-line package; 40 leads (600 mil) 1995 Jan 20 24 SOT129-1 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 VSO40: plastic very small outline package; 40 leads 1995 Jan 20 25 SOT158-1 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm 1995 Jan 20 26 SOT307-2 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 NOTES 1995 Jan 20 27 Philips Semiconductors Product specification Low voltage/low power single-chip 8-bit microcontroller with I2C 80CL410/83CL410 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1995 All rights reserved. Printed in U.S.A.