PCM1808 SLES177A – APRIL 2006 – REVISED AUGUST 2006 SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • 24-Bit Delta-Sigma Stereo A/D Converter Single-Ended Voltage Input: 3 Vp-p High Performance: – THD + N: –93 dB (Typical) – SNR: 99 dB (Typical) – Dynamic Range: 99 dB (Typical) Oversampling Decimation Filter: – Oversampling Frequency: ×64 – Pass-Band Ripple: ±0.05 dB – Stop-Band Attenuation: –65 dB – On-Chip High-Pass Filter: 0.91 Hz (48 kHz) Flexible PCM Audio Interface – Master/Slave Mode Selectable – Data Formats: 24-Bit I2S, 24-Bit Left-Justified Power Down and Reset by Halting System Clock Analog Antialias LPF Included Sampling Rate: 8 kHz–96 kHz System Clock: 256 fS, 384 fS, 512 fS Dual Power Supplies: – 5-V for Analog – 3.3-V for Digital Package: 14-Pin TSSOP DVD Recorder Digital TV AV Amplifier/Receiver MD Player CD Recorder Multitrack Receiver Electric Musical Instrument DESCRIPTION The PCM1808 is high-performance, low-cost, single-chip, stereo analog-to-digital converter with single-ended analog voltage input. The PCM1808 uses a delta-sigma modulator with 64-times oversampling and includes a digital decimation filter and high-pass filter that removes the dc component of the input signal. For various applications, the PCM1808 supports master and slave mode and two data formats in serial audio interface. The PCM1808 supports the power-down and reset function by means of halting the system clock. The PCM1808 is suitable for wide variety of cost-sensitive consumer applications where good performance and operation with a 5-V analog supply and 3.3-V digital supply is required. The PCM1808 is fabricated using a highly advanced CMOS process and is available in a small, 14-pin TSSOP package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) PCM1808 Analog supply voltage, VCC –0.3 V to 6.5 V Digital supply voltage, VDD –0.3 V to 4 V Ground voltage differences, AGND, DGND ±0.1 V Digital input voltage, LRCK, BCK, DOUT –0.3 V to (VDD + 0.3 V) < 4 V Digital input voltage, SCKI, MD0, MD1, FMT –0.3 V to 6.5 V Analog input voltage, VINL, VINR, VREF –0.3 V to (VCC + 0.3 V) < 6.5 V ±10 mA Input current (any pins except supplies) Ambient temperature under bias, TA –40°C to 125°C Storage temperature, Tstg –55°C to 150°C Junction temperature, TJ 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (reflow, peak) (1) 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX Analog supply voltage, VCC 4.5 5 5.5 V Digital supply voltage, VDD 2.7 3.3 3.6 V Analog input voltage, full scale (–0 dB) VCC = 5 V 3 Digital input logic family Vp-p TTL compatible Digital input clock frequency, system clock Digital input clock frequency, sampling clock 2.048 49.152 MHz 8 96 kHz 20 pF 85 °C Digital output load capacitance Operating free-air temperature, TA 2 UNIT –40 Submit Documentation Feedback PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN Resolution TYP MAX 24 UNIT Bits DATA FORMAT I2S, left-justified Audio data interface format Audio data bit length 24 Audio data format fS Sampling frequency System clock frequency Bits MSB-first, 2s complement 8 48 96 256 fS 2.048 12.288 24.576 384 fS 3.072 18.432 36.864 512 fS 4.096 24.576 49.152 kHz MHz INPUT LOGIC VIH (1) 2 VDD VIL (1) 0 0.8 2 5.5 VIH (2) (3) Input logic level VIL (2) (3) 0 IIH (2) IIL (2) IIH (1) (3) Input logic current IIL (1) (3) 0.8 VIN = VDD ±10 VIN = 0 V ±10 VIN = VDD VDC 65 100 µA ±10 VIN = 0 V OUTPUT LOGIC VOH (4) VOL (4) Output logic level IOUT = –4 mA 2.8 IOUT = 4 mA 0.5 VDC DC ACCURACY Gain mismatch, channel-to-channel ±1 ±3 % of FSR Gain error ±3 ±6 % of FSR –93 –87 DYNAMIC PERFORMANCE (5) VIN = –0.5 dB, fS = 48 kHz THD + N Total harmonic distortion + noise VIN = –0.5 dB, fS = 96 kHz S/N Signal-to-noise ratio Channel separation (1) (2) (3) (4) (5) (6) –87 VIN = –60 dB, fS = 48 kHz VIN = –60 dB, fS = 96 kHz Dynamic range (6) –37 (6) fS = 48 kHz, A-weighted fS = 96 kHz, A-weighted fS = 96 kHz, A-weighted 95 95 99 101 93 (6) 99 101 (6) fS = 48 kHz fS = 96 kHz –39 (6) fS = 48 kHz, A-weighted dB 97 91 dB dB dB Pins 7, 8: LRCK, BCK (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, in slave mode) Pin 6: SCKI (Schmitt-trigger input, 5-V tolerant) Pins 10–12: MD0, MD1, FMT (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant) Pins 7–9: LRCK, BCK (in master mode), DOUT Analog performance specifications are tested using a System Two™ audio measurement system by Audio Precision™ with 400-Hz HPF and 20-kHz LPF in RMS mode. fS = 96 kHz, system clock = 256 fS. Submit Documentation Feedback 3 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Input voltage 0.6 VCC Center voltage (VREF) 0.5 VCC Input impedance Antialiasing filter frequency response –3 dB Vp-p V 60 kΩ 1.3 MHz DIGITAL FILTER PERFORMANCE Pass band 0.454 fS Stop band 0.583 fS Hz ±0.05 Pass-band ripple Stop-band attenuation –65 Delay time Hz dB dB 17.4/fS HPF frequency response –3 dB 0.019 fS/1000 POWER SUPPLY REQUIREMENTS VCC VDD Voltage range fS = 48 kHz, 96 kHz ICC Powered down Supply current (7) 4.5 5 5.5 2.7 3.3 3.6 8.6 11 (8) (9) fS = 96 kHz 5.9 (8) Powered down (9) fS = 48 kHz Power dissipation (7) fS = 96 kHz Powered down 8 mA 150 µA 81 77 (9) mA 10.2 62 (8) mA µA 1 fS = 48 kHz IDD VDC mW µW 500 TEMPERATURE RANGE TA Operation temperature θJA Thermal resistance (7) (8) (9) 4 –40 85 170 Minimum load on LRCK (pin 7), BCK (pin 8), DOUT (pin 9) fS = 96 kHz, system clock = 256 fS. Power-down and reset functions enabled by halting SCKI, BCK, LRCK. Submit Documentation Feedback °C °C/W PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 PIN ASSIGNMENTS PW PACKAGE (TOP VIEW) VREF AGND VCC VDD DGND SCKI LRCK 1 2 3 4 5 6 7 VINR VINL FMT MD1 MD0 DOUT BCK 14 13 12 11 10 9 8 P0032-02 TERMINAL FUNCTIONS TERMINAL NAME I/O DESCRIPTION PIN AGND 2 – BCK 8 I/O DGND 5 – Digital GND DOUT 9 O Audio data digital output FMT 12 I Audio interface format select LRCK 7 I/O MD0 10 I Audio interface mode select 0 (2) MD1 11 I Audio interface mode select 1 (2) SCKI 6 I System clock input; 256 fS, 384 fS or 512 fS (3) VCC 3 – Analog power supply, 5-V VDD 4 – Digital power supply, 3.3-V VINL 13 I Analog input, L-channel VINR 14 I Analog input, R-channel VREF 1 – Reference voltage decoupling (= 0.5 VCC) (1) (2) (3) Analog GND Audio data bit clock input/output (1) (2) Audio data latch enable input/output (1) Schmitt-trigger input with internal pulldown (50-kΩ, typical) Schmitt-trigger input with internal pulldown (50-kΩ, typical), 5-V tolerant Schmitt-trigger input, 5-V tolerant Submit Documentation Feedback 5 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 Functional Block Diagram Antialias LPF VINL VREF Delta-Sigma Modulator BCK ×1/64 Decimation Filter with High-Pass Filter Reference Antialias LPF VINR DOUT FMT Mode/ Format Control MD1 Delta-Sigma Modulator MD0 Clock and Timing Control Power Supply VCC LRCK Serial Interface AGND DGND SCKI VDD B0004-10 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. DECIMATION FILTER FREQUENCY RESPONSE OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS 50 0 −10 0 −20 Amplitude − dB Amplitude − dB −30 −50 −100 −40 −50 −60 −70 −150 −80 −90 −200 0 8 16 24 Normalized Frequency [× fS] 32 −100 0.00 G001 Figure 1. 6 0.25 0.50 Frequency [× fS] Figure 2. Submit Documentation Feedback 0.75 1.00 G002 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. DECIMATION FILTER FREQUENCY RESPONSE (Continued) PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS 0.2 0 −1 −2 −3 −0.2 Amplitude − dB Amplitude − dB 0.0 −0.4 −0.6 −4 –4.13 dB at 0.5 fS −5 −6 −7 −8 −0.8 −9 −1.0 0.0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency [× fS] −10 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 0.6 Normalized Frequency [× fS] G003 Figure 3. G004 Figure 4. HIGH-PASS FILTER FREQUENCY RESPONSE HPF STOP-BAND CHARACTERISTICS HPF PASS-BAND CHARACTERISTICS 0.2 0 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −0.2 −0.4 −0.6 −0.8 −90 −100 0.0 −1.0 0.1 0.2 0.3 0.4 Normalized Frequency [× fS/1000] 0 G005 Figure 5. 1 2 3 Normalized Frequency [× fS/1000] 4 G006 Figure 6. Submit Documentation Feedback 7 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. DYNAMIC RANGE AND SNR vs TEMPERATURE −87 105 −88 104 −89 103 Dynamic Range and SNR − dB THD + N − Total Harmonic Distortion + Noise − dB THD + N vs TEMPERATURE −90 −91 −92 −93 −94 −95 −96 −97 −50 101 100 99 98 97 −25 0 25 50 75 95 −50 100 0 25 50 75 G007 Figure 7. Figure 8. THD + N vs SUPPLY VOLTAGE DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE −88 104 −89 103 Dynamic Range and SNR − dB 105 −90 −91 −92 −93 −94 −95 −96 100 G008 102 101 100 Dynamic Range 99 SNR 98 97 96 4.50 4.75 5.00 5.25 VCC − Supply Voltage − V 5.50 5.75 95 4.25 G009 Figure 9. 8 −25 TA − Free-Air Temperature − °C −87 −97 4.25 Dynamic Range SNR 96 TA − Free-Air Temperature − °C THD + N − Total Harmonic Distortion + Noise − dB 102 4.50 4.75 5.00 Figure 10. Submit Documentation Feedback 5.25 VCC − Supply Voltage − V 5.50 5.75 G010 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. DYNAMIC RANGE AND SNR vs fSAMPLE CONDITION −87 105 −88 104 −89 103 Dynamic Range and SNR − dB THD + N − Total Harmonic Distortion + Noise − dB THD + N vs fSAMPLE CONDITION −90 −91 −92 −93 −94 −95 Dynamic Range SNR 102 101 100 99 98 97 (1) System (1) System Clock = 384 fS (2) System Clock = 512 f S (3) System Clock = 256 f S −96 −97 Clock = 384 fS System Clock = 512 fS (3) System Clock = 256 f S (2) 96 95 44.1(1) 44.1(1) 48(2) 96(3) fSAMPLE Condition − kHz 48(2) 96(3) fSAMPLE Condition − kHz G011 Figure 11. Figure 12. OUTPUT SPECTRUM (–0.5 dB, N = 8192) OUTPUT SPECTRUM (–60 dB, N = 8192) G012 OUTPUT SPECTRUM 0 0 Input Level = −60 dB Data Points = 8192 −20 −20 −40 −40 Amplitude − dB Amplitude − dB Input Level = −0.5 dB Data Points = 8192 −60 −80 −60 −80 −100 −100 −120 −120 −140 −140 0 5 10 15 20 0 f − Frequency − kHz 5 10 15 20 f − Frequency − kHz G013 Figure 13. G014 Figure 14. Submit Documentation Feedback 9 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. OUTPUT SPECTRUM (Continued) THD + N − Total Harmonic Distortion + Noise − dB THD + N vs SIGNAL LEVEL 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 Signal Level − dB G015 Figure 15. SUPPLY CURRENT SUPPLY CURRENT vs fSAMPLE CONDITION 15 ICC and IDD − Supply Current − mA ICC IDD 10 5 (1) System Clock = 384 fS System Clock = 512 fS (3) System Clock = 256 f S (2) 0 44.1(1) 48(2) 96(3) fSAMPLE Condition − kHz G016 Figure 16. 10 Submit Documentation Feedback PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 SYSTEM CLOCK The PCM1808 supports 256 fS, 384 fS and 512 fS as system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 6). The PCM1808 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS in slave mode. In master mode, the system clock frequency must be controlled through the serial control port, which uses MD1 (pin 111) and MD0 (pin 10). The system clock is divided down automatically to generate frequencies of 128 fS and 64 fS, which are used to operate the digital filter and the delta-sigma modulator, respectively. Table 1 shows some typical relationships between sampling frequency and system clock frequency, and Figure 17 shows system clock timing. Table 1. Sampling Frequency and System Clock Frequency SAMPLING FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (fSCLK) (MHz) 256 fS 384 fS 512 fS 8 2.048 3.072 4.096 16 4.096 6.144 8.192 32 8.192 12.288 16.384 44.1 11.2896 16.9344 22.5792 48 12.288 18.432 24.576 64 16.384 24.576 32.768 88.2 22.5792 33.8688 45.1584 96 24.576 36.864 49.152 tw(SCKH) tw(SCKL) SCKI 2V SCKI 0.8 V T0005B07 SYMBOL PARAMETER MIN MAX UNIT tw(SCKH) System clock pulse duration, HIGH 8 ns tw(SCKL) System clock pulse duration, LOW 8 ns System clock duty cycle 40% 60% Figure 17. System Clock Timing FADE-IN AND FADE-OUT FUNCTIONS The PCM1808 has fade-in and fade-out functions on DOUT (pin 9) to avoid pop noise, and the functions come into operation in some cases as described in several following sections. The level changes from 0 dB to mute or mute to 0 dB are performed using calculated pseudo S-shaped characteristics with zero-cross detection. Because of the zero-cross detection, the time needed for the fade in and fade out depends on the analog input frequency (fin). It takes 48/fin until processing is completed. If there is no zero cross during 8192/fS, DOUT is faded in or out by force during 48/fS (TIME OUT). Figure 18 illustrates the fade-in and fade-out operation processing. Submit Documentation Feedback 11 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 Fade-Out Start Fade-In Complete Fade-In Start DOUT (Contents) Fade-Out Complete BPZ 48/fin or 48/fS 48/fin or 48/fS T0080-01 Figure 18. Fade-In and Fade-Out Operations POWER ON The PCM1808 has an internal power-on-reset circuit, and initialization (reset) is performed automatically when the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts after VDD > 2.2 V (typical), the PCM1808 stays in the reset state and the digital output is forced to zero. The digital output is valid after the reset state is released and the time of 8960/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the data corresponding to the analog input signal is obtained. Figure 19 illustrates the power-on timing and the digital output. VDD 2.6 V 2.2 V 1.8 V Reset Reset Release Internal Reset Operation 1024 System Clocks 8960/fS System Clock DOUT Zero Data Normal Data Fade-In Complete Fade-In Start DOUT BPZ (Contents) 48/fin or 48/fS T0014-09 Figure 19. Power-On Timing 12 Submit Documentation Feedback PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 CLOCK-HALT POWER-DOWN AND RESET FUNCTION The PCM1808 has a power-down and reset function, which is triggered by halting SCKI (pin 6) in both master and slave modes. The function is available anytime after power on. Reset and power down are performed automatically 4 µs (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1808 stays in the reset and power-down mode, and DOUT (pin 9) is forced to zero. SCKI must be supplied to release the reset and power-down mode. The digital output is valid after the reset state is released and the time of 1024 SCKI + 8960/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the level corresponding to the analog input signal is obtained. Figure 20 illustrates the clock-halt reset timing. To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) are required to synchronize with SCKI within 4480/fS after SCKI is resumed. If it takes more than 4480/fS for BCK and LRCK to synchronize with SCKI, SCKI should be masked until the synchronization is achieved again, taking care of glitch and jitter. See the typical circuit connection diagram, Figure 26. To avoid ADC performance degradation, the clock-halt reset also should be asserted when system clock SCKIor the audio interface clocks BCK and LRCK (sampling rate fS) are changed on the fly. SCKI Halt SCKI Resume Fixed to Low or High SCKI t(CKR) Reset: t(RST) Clock-Halt Reset Internal Reset DOUT Reset Release: t(REL) Operation Operation Normal Data Zero Data Normal Data Fade-In Complete Fade-In Start DOUT BPZ (Contents) Normal Data 48/fin or 48/fS T0081-01 SYMBOL PARAMETER MIN MAX UNIT µs t(CKR) Delay time from SCKI halt to internal reset 4 t(RST) Delay time from SCKI resume to reset release 1024 SCKI µs t(REL) Delay time from reset release to DOUT output 8960/fS µs Figure 20. Clock-Halt Power-Down and Reset Timing Submit Documentation Feedback 13 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 SERIAL AUDIO DATA INTERFACE The PCM1808 interfaces the audio system through LRCK (pin 7), BCK (pin 8), and DOUT (pin 9). INTERFACE MODE The PCM1808 supports master mode and slave mode as interface modes, which are selected by MD1 (pin 11) and MD0 (pin 10), as shown in Table 2. MD1 and MD0 must be set prior to power on. In master mode, the PCM1808 provides the timing of serial audio data communications between the PCM1808 and the digital audio processor or external circuit. While in slave mode, the PCM1808 receives the timing for data transfer from an external controller. Table 2. Interface Modes MD1 (Pin 11) MD0 (Pin 10) INTERFACE MODE Low Low Slave mode (256 fS, 384 fS, 512 fS autodetection) Low High Master mode (512 fS) High Low Master mode (384 fS) High High Master mode (256 fS) Master mode In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated in the clock circuit of the PCM1808. The frequency of BCK is fixed at 64 BCK/frame. Slave mode In slave mode, BCK and LRCK work as input pins. The PCM1808 accepts 64-BCK/frame or 48-BCK/frame format (only for a 384-fS system clock), not 32-BCK/frame format. DATA FORMAT The PCM1808 supports two audio data formats in both master and slave modes. The data formats are selected by FMT (pin 12), as shown in Table 3. Figure 21 illustrates the data formats in slave mode and master mode. Table 3. Data Format 14 FORMAT NO. FMT (Pin 12) 0 Low I2S, 24-bit FORMAT 1 High Left-justified, 24-bit Submit Documentation Feedback PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 FORMAT 0: FMT = LOW 24-Bit, MSB-First, I2S Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 22 23 24 MSB 1 LSB 2 3 22 23 24 MSB LSB FORMAT 1: FMT = HIGH 24-Bit, MSB-First, Left-Justified Left-Channel LRCK Right-Channel BCK DOUT 1 2 MSB 3 22 23 24 LSB 1 2 3 MSB 22 23 24 1 LSB T0016-17 Figure 21. Audio Data Format (LRCK and BCK Work as Inputs in Slave Mode and as Outputs in Master Mode) Submit Documentation Feedback 15 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 INTERFACE TIMING Figure 22 and Figure 23 illustrate the interface timing in slave mode and master mode, respectively. t(LRCP) 1.4 V LRCK t(BCKL) t(LRSU) t(BCKH) t(LRHD) 1.4 V BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT T0017-02 SYMBOL PARAMETER t(BCKP) BCK period t(BCKH) t(BCKL) t(LRSU) MIN TYP MAX UNIT 1/(64 fS) ns BCK pulse duration, HIGH 1.5 × t(SCKI) ns BCK pulse duration, LOW 1.5 × t(SCKI) ns LRCK setup time to BCK rising edge 50 ns t(LRHD) LRCK hold time to BCK rising edge 10 ns t(LRCP) LRCK period 10 t(CKDO) Delay time, BCK falling edge to DOUT valid –10 40 ns t(LRDO) Delay time, LRCK edge to DOUT valid –10 40 ns tr Rise time of all signals 20 ns tf Fall time of all signals 20 ns µs NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Rise and fall times are from 10% to 90% of the input/output signal swing. Load capacitance of DOUT is 20 pF. t(SCKI) is the SCKI period. Figure 22. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs) 16 Submit Documentation Feedback PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 t(LRCP) 0.5 VDD LRCK t(BCKL) t(BCKH) t(CKLR) 0.5 VDD BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT T0018-02 MIN TYP MAX UNIT t(BCKP) SYMBOL BCK period PARAMETER 150 1/(64 fS) 2000 ns t(BCKH) BCK pulse duration, HIGH 65 1200 ns t(BCKL) BCK pulse duration, LOW 65 1200 ns t(CKLR) Delay time, BCK falling edge to LRCK valid –10 20 ns t(LRCP) LRCK period 10 125 µs t(CKDO) Delay time, BCK falling edge to DOUT valid –10 20 ns t(LRDO) Delay time, LRCK edge to DOUT valid –10 20 ns tr Rise time of all signals 20 ns tf Fall time of all signals 20 ns 1/fS NOTE: Timing measurement reference level is 0.5 VDD. Rise and fall times are from 10% to 90% of the input/output signal swing. Load capacitance of all signals is 20 pF. Figure 23. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs) 1.4 V SCKI t(SCKBCK) t(SCKBCK) 0.5 VDD BCK T0074-01 SYMBOL t(SCKBCK) PARAMETER Delay time, SCKI rising edge to BCK edge MIN 5 TYP MAX UNIT 30 ns NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of BCK is 20 pF. This timing is applied when SCKI frequency is less than 25 MHz. Figure 24. Audio Clock Interface Timing (Master Mode: BCK Works as Output) Submit Documentation Feedback 17 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In slave mode, the PCM1808 operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6). The PCM1808 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48 BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI is established. In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization does not occur and the previously described digital output control and discontinuity do not occur. Figure 25 illustrates the digital output response for loss of synchronization and resynchronization. During undefined data, the PCM1808 can generate some noise in the audio signal. Also, the transition of normal data to undefined data creates a discontinuity in the digital output data, which can generate some noise in the audio signal. The digital output is valid after resynchronization completes and the time of 32/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the level corresponding to the analog input signal is obtained. If synchronization is lost during the fade-in or fade-out operation, the operation stops and DOUT (pin 9) is forced to zero data immediately. The fade-in operation resumes from mute after the time of 32/fS following resynchronization. Resynchronization Resynchronization Synchronization Lost State of Synchronization Synchronous Asynchronous 1/fS DOUT Normal Data Synchronization Lost Synchronous Asynchronous Synchronous 32/fS Undefined Data Zero Data Normal Data Zero Data Normal Data Fade-In Complete Fade-In Start DOUT BPZ (Contents) Fade-In Restart Normal Data 32/fS 48/fin or 48/fS 48/fin or 48/fS T0082-01 Figure 25. ADC Digital Output for Loss of Synchronization and Resynchronization 18 Submit Documentation Feedback PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 APPLICATION INFORMATION TYPICAL CIRCUIT CONNECTION DIAGRAM Figure 26 is a typical circuit connection diagram. The antialiasing low-pass filters are integrated on the analog inputs, VINL and VINR. If the performance of these filters is not adequate for an application, appropriate external antialiasing filters are needed. A passive RC filter (100 Ω and 0.01 µF to 1 kΩ and 1000 pF) generally is used. PCM1808 C5(3) C4(2) 4 µs (min) 5V 3.3 V Mask PLL170x X1(4) + (2) + (5) + 1 VREF VINR 14 2 AGND VINL 13 3 VCC FMT 12 4 VDD MD1 11 5 DGND MD0 10 6 SCKI DOUT 9 7 LRCK BCK 8 C3 + C1(1) + C2(1) R-ch IN L-ch IN High/Low Pin Setting DSP or Audio Processor S0113-02 (1) C1, C2: A 1-µF electrolytic capacitor gives 2.7 Hz (τ = 1 µF × 60 kΩ) cutoff frequency for the input HPF in normal operation and requires a power-on settling time with a 60-ms time constant in the power-on initialization period. (2) C3, C4: Bypass capacitors, 0.1-µF ceramic and 10-µF electrolytic, depending on layout and power supply (3) C5: 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended. (4) X1: X1 masks the system clock input when using the clock-halt reset function with external control. (5) Optional external antialiasing filter could be required, depending on the application. Figure 26. Typical Circuit Connection Diagram BOARD DESIGN AND LAYOUT CONSIDERATIONS VCC, VDD PINS The digital and analog power supply lines to the PCM1808 should be bypassed to the corresponding ground pins with both 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC. AGND, DGND PINS To maximize the dynamic performance of the PCM1808, the analog and digital grounds are not internally connected. These grounds should have low impedance to avoid digital noise feedback into the analog ground. They should be connected directly to each other under the PCM1808 package to reduce potential noise problems. VINL, VINR PINS VINL and VINR are single-ended inputs. The antialias low-pass filters are integrated on these inputs to remove the high-frequency noise outside the audio band. If the performance of these filters is not adequate for an application, appropriate external antialiasing filters are required. A passive RC filter (100 Ω and 0.01 µF to 1 kΩ and 1000 pF) is generally used. Submit Documentation Feedback 19 PCM1808 www.ti.com SLES177A – APRIL 2006 – REVISED AUGUST 2006 APPLICATION INFORMATION (continued) VREF PIN To ensure low source impedance of the ADC references, 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended between VREF and AGND. These capacitors should be located as close as possible to the VREF pin to reduce dynamic errors on the ADC references. DOUT PIN The DOUT pin has a large load-drive capability, but if the DOUT line is long, locating a buffer near the PCM1808 and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and maximize the dynamic performance of the ADC. SYSTEM CLOCK The quality of the system clock can influence dynamic performance, as the PCM1808 operates based on a system clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time difference between system clock transition and BCK or LRCK transition in slave mode. 20 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 5-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCM1808PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1808PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1808PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM1808PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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