PULSECORE PCS2P2310ANZG-28-AT

PCS2I2310ANZ
September 2006
rev 0.5
3.3V SDRAM Buffer for Mobile PCS with 4 SO-DIMMs
Functional Description
Features
•
One input to 10 output buffer/driver
•
Supports up to four SDRAM SO-DIMMs
•
Two additional outputs for feedback
•
Serial interface for output control
•
Low skew outputs
•
Up to 133MHz operation
•
Multiple VDD and VSS pins for noise reduction
•
Dedicated OE pin for testing
•
Space-saving 28 Pin SSOP package
The PCS2I2310ANZ also includes a serial interface (IIC),
•
3.3V operation
which can enable or disable each output clock. The IIC is
The PCS2I2310ANZ is a 3.3V buffer designed to distribute
high-speed clocks in mobile PC applications. The part has
10 outputs, 8 of which can be used to drive up to four
SDRAM SO-DIMMs, and the remaining can be used for
external feedback to a PLL. The device operates at 3.3V
and outputs can run up to 133MHz, thus making it
i
compatible with Pentium II® processors.
Slave Receiver only and is Standard mode compliant. IIC
Master can write into the IIC registers but cannot read
back. The first two bytes after address should be ignored
by IIC Block and data is valid after these two bytes as given
in IIC Byte Flow Table. On power-up, all output clocks are
enabled. A separate Output Enable pin facilitates testing on
ATE.
i
Pentium II is a registered trademark of Intel Corporation
Block Diagram
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDATA
Serial Interface
Decoding
SDRAM4
SDRAM5
SDRAM6
SCLOCK
SDRAM7
SDRAM8
SDRAM9
OE
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PCS2I2310ANZ
September 2006
rev 0.5
Pin Configuration
28 Pin SSOP Package-- Top View
VDD
1
28
VDD
SDRAM0
2
27
SDRAM7
SDRAM1
3
26
SDRAM6
VSS
4
25
VSS
VDD
5
24
VDD
SDRAM2
6
23
SDRAM5
SDRAM3
7
22
SDRAM4
VSS
8
21
VSS
BUF_IN
9
20
OE
VDD
10
19
VDD
SDRAM8
11
18
SDRAM9
VSS
12
17
VSS
PCS2P2310ANZ
16pi TSSOP
VDDIIC
13
16
VSSIIC
SDATA
14
15
SCLOCK
28 pin SSOP
Pin Description
Pins
Name
Type
Description
1, 5, 10, 19, 24, 28
VDD
P
3.3V Digital voltage supply
4, 8, 12, 17, 21, 25
VSS
P
Ground
13
VDDIIC
P
3.3V Serial interface voltage supply
16
VSSIIC
P
Ground for serial interface
9
BUF_IN
I
Input clock, 5V tolerant
20
OE
I
Output Enable, three-states outputs when LOW.
Internal pull-up to VDD
14
SDATA
15
SCLK
I
Serial clock input. Internal pull-up to VDD. 5V tolerant
2, 3, 6, 7
SDRAM [0–3]
O
SDRAM byte 0 Clock Outputs
22, 23, 26, 27
SDRAM [4–7]
O
SDRAM byte 1 Clock Outputs
11, 18
SDRAM [8–9]
O
SDRAM byte 2 Clock Outputs
I/O
Bi-directional Serial data pin. Internal pull-up to VDD. 5V tolerant
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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PCS2I2310ANZ
September 2006
rev 0.5
Device Functionality
Byte 1: SDRAM Active/Inactive Register1
(1 = Enable, 0 = Disable), Default = Enable
OE
SDRAM [0–17]
0
High-Z
Bit
Pin #
1
1 x BUF_IN
Bit 7
27
SDRAM7 (Active/Inactive)
Bit 6
26
SDRAM6 (Active/Inactive)
Bit 5
23
SDRAM5 (Active/Inactive)
Bit 4
22
SDRAM4 (Active/Inactive)
Bit 3
--
Unused
Bit 2
--
Unused
Bit 1
--
Unused
Bit 0
--
Unused
Serial Configuration Map
• The Serial bits will be read by the clock driver in the
following order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits can be programmed to either
Description
“0” or “1”.
Byte 2: SDRAM Active/Inactive Register1
(1 = Enable, 0 = Disable), Default = Enable
• Serial interface address for the PCS2I2310ANZ is:
A6
A5
A4
A3
A2
A1
A0
R/W
Bit
Pin #
1
1
0
1
0
0
1
----
Bit 7
18
SDRAM9 (Active/Inactive)
Bit 6
11
SDRAM8 (Active/Inactive)
Bit 5
--
Reserved
Bit 4
--
Reserved
Bit 3
--
Reserved
Bit 2
--
Reserved
Bit 1
--
Reserved
Bit 0
--
Reserved
Byte 0: SDRAM Active/Inactive Register1
(1 = Enable, 0 = Disable), Default = Enable
Bit
Pin #
Description
Bit 7
--
Unused
Bit 6
--
Unused
Bit 5
--
Unused
Bit 4
--
Unused
Bit 3
7
SDRAM3 (Active/Inactive)
Bit 2
6
SDRAM2 (Active/Inactive)
Bit 1
3
SDRAM1 (Active/Inactive)
Bit 0
2
SDRAM0 (Active/Inactive)
Description
Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value
of all the bits is high after chip is powered up.
IIC Byte Flow
Byte
Description
1
IIC Address
2
Command (dummy value, ignored)
3
Byte Count (dummy value, ignored)
4
IIC Data Byte 0
5
IIC Data Byte 1
6
IIC Data Byte 2
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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PCS2I2310ANZ
September 2006
rev 0.5
Absolute Maximum Ratings
Symbol
VDD
VIN
VINB
TSTG
TJ
TDV
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except BUF_IN)
DC Input Voltage (BUF_IN)
Storage Temperature
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Rating
Unit
-0.5V to +7.0
-0.5V to VDD + 0.5
-0.5V to +7.0
-65°C to +150
150
V
V
V
°C
°C
2000
V
Operating Conditions
Parameter
Description
Min
Max
Unit
VDD
TA
CL
CIN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
3.135
0
20
3.465
70
30
7
V
°C
pF
pF
0.05
50
ms
tPU
Electrical Characteristics
Parameter
Description
VIL
VILIIC
VIH
VOL
VOH
Input LOW Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage1
Output HIGH Voltage1
Quiescent Supply
Current
High Impedance
Output Current
OffState Current
(for SCL ,SDATA)
ICC
IOZ
IOFF
∆ICC
Ii
Change in Supply
Current
Input Leakage
1
IDD
IDD
IDD
IDD
IDD
IDD
Supply Current
Supply Current1
Supply Current1
Supply Current1
Supply Current1
Supply Current1
IDDS
Supply Current
Test Conditions
Min
Typ
Except serial interface pins
For serial interface pins only
Max
Unit
0.8
0.7
V
V
V
V
V
2.0
IOL= 25 mA
IOH = –36 mA
VDD= 3.465V, Vi = VDD or GND
IO =0
0.4
2.4
50
VDD= 3.465V, Vi = VDD or GND
VDD= 0V, Vi = 0V or 5.5V
VDD= 3.135V to 3.465V
One Input at VDD-0.6, All other Inputs
at VDD or GND
VDD= 3.465V or GND
(Applicable to all Input Pins)
Unloaded outputs, 133MHz
Loaded outputs, 30pF, 133MHz
Unloaded outputs, 100MHz
Loaded outputs, 30pF,100MHz
Unloaded outputs, 66.67MHz
Loaded outputs, 30pF ,66.67MHz
BUF_IN=VDD or VSS,
all other inputs at VDD
-5
100
µA
±10
µA
50
µA
500
µA
+5
µA
266
360
200
290
150
185
mA
mA
mA
mA
mA
mA
500
µA
Note: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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PCS2I2310ANZ
September 2006
rev 0.5
Switching Characteristics1
Parameter
Name
fmax
Maximum Operating Frequency
tD
t3
t4
t5
t6
t7
tPLZ, tPHZ
tPZL, tPZH
tr
tf
2,3
Duty Cycle
Test Conditions
= t2 ÷ t1
Min
Measured at 1.5V
3
Rising Edge Rate
3
Falling Edge Rate
3
Output to Output Skew
Typ
Max
Unit
133
MHz
45.0
50.0
55.0
%
Measured between 0.4V and 2.4V
1
2
4
V/nS
Measured between 2.4V and 0.4V
1
2
4
V/nS
150
225
pS
All outputs equally loaded
3
Input edge greater than 1 V/nS
1
2.7
3.5
nS
3
Input edge greater than 1 V/nS
1
2.7
3.5
nS
Input edge greater than 1 V/nS
1
3
5
nS
SDRAM Buffer Disable Delay
Input edge greater than 1 V/nS
1
3
5
nS
Rise Time for SDATA
(Refer Test Circuit for IIC)
Refer figure no.3
Fall Time for SDATA
(Refer Test Circuit for IIC)
Refer figure no.3
CL = 10pF
6
SDRAM Buffer LH Prop. Delay
SDRAM Buffer HL Prop. Delay
3
SDRAM Buffer Enable Delay
3
CL = 400pF
250
CL = 10pF
20
CL = 400pF
250
nS
nS
Note: 1 .All parameters specified with loaded outputs.
2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Test Circuit for SDRAM Enable and Disable Times
S1
2 * VDD
Open
VSS
VDD
500Ω
VI
VO
PULSE
GENERATOR
D.U.T
RT
TEST
t6/t7
tPLZ/tPZL
tPHZ/tPZH
CL
500Ω
S1
Open
2* VDD
VSS
Figure 1. Load circuit for Switching times
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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PCS2I2310ANZ
September 2006
rev 0.5
SDRAM Enable and Disable Times
VM = 1.5V
VX = VOL +0.3V
VY = VOH -0.3V
VOH and VOL are the typical Output Voltage drop that occur with the output load
VI
VDD
VM
OE INPUT
GND
tPZL
tPLZ
VDD
OUTPUT
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VDD
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
tPZH
VY
VM
VSS
Outputs
enabled
Outputs
enabled
Outputs
disabled
Figure 2. 3-State Enable and Disable times
Test Circuit for IIC Rise and Fall Times
VO = 3.3V
RL = 1kΩ
DUT
CL = 10pF or
CL = 400pF
GND
Figure 3. Test Circuit for IIC
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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PCS2I2310ANZ
September 2006
rev 0.5
Switching Waveforms
Duty Cycle Timing
t1
t2
1.5 V
1.5 V
1.5 V
All Outputs Rise/Fall Time
2.4 V
OUTPUT
3.3 V
2.4 V
0.4 V
0.4 V
0V
t3
t4
Output - Output Skew
1.5 V
OUTPUT
1.5 V
OUTPUT
t5
SDRAM Buffer LH and HL Propagation Delay
INPUT
OUTPUT
t6
Test Circuits
t7
TEST CIRCUIT
+3.3V
VDD
+3.3V
CLKOUT
0.1uF
OUTPUT
CLOAD
VDD
0.1uF
GND
GND
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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PCS2I2310ANZ
September 2006
rev 0.5
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done.
Rs
CPUCLK
BUF_IN
Rs
SDRAMX
SDATA
SDATA
SCLK
SCLK
Ct
VDD
VDD
Cd = Decoupling Capacitor
VSS
Ct = Optional EMI-Reducing Capacitor
Rs = Series Terminating Resistors
X = 0 to 10
Cd = 0.1µ F
PCS2I2310ANZ
SSOP 28
Summary
•
Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of
0.1µF. In some cases, smaller value capacitors may be required.
•
The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic
impedance of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating
resistor.
Rseries > Rtrace – Rout
•
Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating
resistor as is physically possible. Typical values of these capacitors range from 4.7pF to 22pF.
•
A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead
offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions.
•
If a Ferrite Bead is used, a 10µF–22µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This
capacitor prevents power supply droop during current surges.
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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PCS2I2310ANZ
September 2006
rev 0.5
IIC Serial Interface Information
The information in this section assumes familiarity with IIC programming.
How to program PCS2I2310ANZ through IIC:
•
Master (host) sends a start bit.
•
Master (host) sends the write address D3 (H).
•
PCS2I2310ANZ device will acknowledge.
•
Master (host) sends the Command Byte.
•
PCS2I2310ANZ device will acknowledge the Command Byte.
•
Master (host) sends a Byte count
•
PCS2I2310ANZ device will acknowledge the Byte count.
•
Master (host) sends the Byte 0
•
PCS2I2310ANZ device will acknowledge Byte 0
•
Master (host) sends the Byte 1
•
PCS2I2310ANZ device will acknowledge Byte 1
•
Master (host) sends the Byte 2
•
PCS2I2310ANZ device will acknowledge Byte 2
•
Master (host) sends a Stop bit.
Controller (Host)
PCS2I2310ANZ
(slave/receiver)
Start Bit
Slave Address D3(H)
ACK
Command Byte
ACK
Byte count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Stop Bit
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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PCS2I2310ANZ
September 2006
rev 0.5
Package Information
28L SSOP (209 mil)
Symbol
A
Dimensions
Inches
Millimeters
Min
Max
Min
Max
….
0.079
…
2.0
A1
0.002
…
0.05
…
A2
0.065
0.073
1.65
1.85
D
0.394
0.409
10.00
10.40
L
0.021
0.037
0.55
0.95
E
0.295
0.319
7.50
8.10
E1
0.197
0.220
5.00
5.60
R1
0.004
….
0.09
…..
b
0.009
0.015
0.22
0.38
b1
0.009
0.013
0.22
0.33
c
0.004
0.010
0.09
0.25
c1
0.004
0.008
0.09
0.21
L1
0.050REF
1.25 REF
e
0.026 BSC
0.65 BSC
θ
0°
8°
0°
8°
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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PCS2I2310ANZ
September 2006
rev 0.5
Ordering Information
Part Number
Marking
PCS2P2310ANZG-28-AT
2P2310ANZG
Package Type
Operating Range
28-pin SSOP –Tube, Green
Commercial
Commercial
PCS2P2310ANZG-28-AR
2P2310ANZG
28-pin SSOP –Tape and Reel, Green
PCS2I2310ANZG-28-AT
2I2310ANZG
28-pin SSOP –Tube, Green
PCS2I2310ANZG-28-AR
2I2310ANZG
28-pin SSOP –Tape and Reel, Green
Industrial
Industrial
Device Ordering Information
P C S 2 I 2 3 1 0 A N Z G - 2 8 - A R
R = Tape & Reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
11 of 12
PCS2I2310ANZ
September 2006
rev 0.5
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Copyright © PulseCore Semiconductor
All Rights Reserved
Preliminary Information
Part Number: PCS2I2310ANZ
Document Version: 0.5
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their
respective companies. PulseCore reserves the right to make changes to this document and its products at any time without
notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein
represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct
this data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from
PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale.
The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products
for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result
in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the
manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
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