CY2318ANZ 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs Features Functional Description • One input to 18 output buffer/driver • Supports up to four SDRAM DIMMs • Two additional outputs for feedback • Serial interface for individual output control • 150ps typical output-output skew • Up to 100 MHz operation • Dedicated OE pin for testing The CY2318ANZ is a 3.3V buffer designed to distribute high-speed clocks in PC applications. The part has 18 outputs, 16 of which can be used to drive up to four SDRAM DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium II® processors. The CY2318ANZ can be used in conjunction with the CY2280, CY2281, CY2282 or similar clock synthesizer for a complete Pentium II motherboard solution. The CY2318ANZ also includes a serial interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull up). A separate Output Enable pin facilitates testing on ATE. • Space-saving 48-pin SSOP package • 3.3V operation Pin Configuration Block Diagram SSOP Top View NC NC VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD SDRAM4 SDRAM5 VSS VDD SDRAM6 SDRAM7 VSS VDD SDRAM16 VSS VDDIIC SDATA BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDATA Serial Interface Decoding SCLOCK SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17 OE Cypress Semiconductor Corporation Document #: 38-07181 Rev. *B • 3901 North First Street • 1 2 48 47 3 4 46 45 5 44 6 43 7 42 8 9 41 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 32 31 19 30 20 21 29 28 22 27 23 26 24 25 NC NC VDD SDRAM15 SDRAM14 VSS VDD SDRAM13 SDRAM12 VSS OE VDD SDRAM11 SDRAM10 VSS VDD SDRAM9 SDRAM8 VSS VDD SDRAM17 VSS VSSIIC SCLOCK San Jose, CA 95134 • 408-943-2600 Revised January 19, 2005 CY2318ANZ Pin Summary Name Pins Description VDD 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 VSS 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 Ground VDDIIC 23 Serial interface voltage supply VSSIIC 26 Ground for serial interface BUF_IN 11 Input clock (5V Tolerant) OE 38 Output Enable (active HIGH), Three-state outputs when low[1] SDATA 24 Serial data input[1] SCLK 25 Serial clock input[1] SDRAM [0–3] 4, 5, 8, 9 SDRAM byte 0 clock outputs SDRAM [4–7] 13, 14, 17, 18 SDRAM byte 1 clock outputs SDRAM [8–11] 31, 32, 35, 36 SDRAM byte 2 clock outputs SDRAM [12–15] 40, 41, 44, 45 SDRAM byte 3 clock outputs SDRAM [16–17] 21, 28 SDRAM clock outputs usable for feedback N/C Reserved for future modifications, do not connect in system 1, 2, 47, 48 3.3V Digital voltage supply Note: 1. Internal pull-up resistor to VDD (value > 100 kohms) Device Functionality OE SDRAM [0–17] 0 Hi-Z 1 1 x BUF_IN Document #: 38-07181 Rev. *B Page 2 of 9 CY2318ANZ Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits should be programmed to “0”. • Serial interface address for the CY2318ANZ is: • • A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 ---- • Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description Bit 7 45 SDRAM15 (Active/Inactive) Bit 6 44 SDRAM14 (Active/Inactive) Bit 5 41 SDRAM13 (Active/Inactive) Bit 4 40 SDRAM12 (Active/Inactive) Bit 3 36 SDRAM11 (Active/Inactive) Bit 2 35 SDRAM10 (Active/Inactive) Bit 1 32 SDRAM9 (Active/Inactive) Bit 0 31 SDRAM8 (Active/Inactive) Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active • Byte 0:SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description Bit 7 18 SDRAM7 (Active/Inactive) Bit 6 17 SDRAM6 (Active/Inactive) Bit 5 14 SDRAM5 (Active/Inactive) Bit 4 13 SDRAM4 (Active/Inactive) Bit 3 9 SDRAM3 (Active/Inactive) Bit 2 8 SDRAM2 (Active/Inactive) Bit 1 5 SDRAM1 (Active/Inactive) Bit 0 4 SDRAM0 (Active/Inactive) Document #: 38-07181 Rev. *B Bit Pin # Description Bit 7 28 SDRAM17 (Active/Inactive) Bit 6 21 SDRAM16 (Active/Inactive) Bit 5 -- Reserved, drive to 0 Bit 4 -- Reserved, drive to 0 Bit 3 -- Reserved, drive to 0 Bit 2 -- Reserved, drive to 0 Bit 1 -- Reserved, drive to 0 Bit 0 -- Reserved, drive to 0 Page 3 of 9 CY2318ANZ Maximum Ratings Storage Temperature .................................. –65°C to +150°C Supply Voltage to Ground Potential ..................–0.5 to +7.0V DC Input Voltage (except BUF_IN) .......... –0.5V to VDD + 0.5 DC Input Voltage (BUF_IN).............................. –0.5V to 7.0V Junction Temperature ............................................... +150°C Static Discharge Voltage............................................ >2000V (per MIL-STD-883, Method 3015) Operating Conditions Parameter Description Min. Max. Unit VDD, VDDIIC Supply Voltage 3.135 3.465 V TA Operating Temperature (Ambient Temperature) 0 70 °C CL Load Capacitance 20 30 pF CIN Input Capacitance 7 pF tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms Min. Max. Unit For all pins except serial interface pins 0.8 V For serial pins only 0.7 V 10 µA 100 µA 10 µA 0.4 V Electrical Characteristics Over the Operating Range Parameter Description Voltage[2] VIL Input LOW VILiic Input LOW Voltage Test Conditions Voltage[2] VIH Input HIGH IIL Input LOW Current (BUF_IN input) VIN = 0V IIL Input LOW Current (Except BUF_IN Pin) VIN = 0V IIH Input HIGH Current VIN = VDD Voltage[3] VOL Output LOW VOH Output HIGH Voltage[3] Current[3] IDD Supply IDD Supply Current Current[3] 2.0 –10 –10 IOL = 25 mA IOH = –36 mA V 2.4 V Unloaded outputs, 100 MHz 200 mA Loaded outputs, 100 MHz 360 mA IDD Supply Unloaded outputs, 66.67 MHz 150 mA IDD Supply Current Loaded outputs, 66.67 MHz 230 mA IDDS Supply Current BUF_IN = VDD or VSS, all other inputs at VDD 500 µA Notes: 2. BUF_IN input has a threshold voltage of VDD/2. 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07181 Rev. *B Page 4 of 9 CY2318ANZ Switching Characteristics[4] Parameter Name Test Conditions Min. Typ. Maximum Operating Frequency Duty Cycle [3, 5] = t2 ÷ t1 t3 Rising Edge Rate[3] t4 Falling Edge Rate[3] [3] Output to Output Skew t5 Max. Unit 100 MHz Measured at 1.5V 45.0 50.0 55.0 % Measured between 0.4V and 2.4V 0.9 1.5 4.0 V/ns Measured between 2.4V and 0.4V 0.9 1.5 4.0 V/ns 150 250 ps All outputs equally loaded t6 [3] SDRAM Buffer LH Prop. Delay Input edge greater than 1 V/ns 1.0 3.5 5.0 ns t7 SDRAM Buffer HL Prop. Delay[3] Input edge greater than 1 V/ns 1.0 3.5 5.0 ns [3] Input edge greater than 1 V/ns 1.0 5 12 ns [3] Input edge greater than 1 V/ns 1.0 20 30 ns SDRAM Buffer Enable Delay t8 SDRAM Buffer Disable Delay t9 Switching Waveforms Duty Cycle Timing t1 t2 1.5V 1.5V 1.5V All Outputs Rise/Fall Time OUTPUT 2.4V 0.4V 2.4V 0.4V 3.3V 0V t4 t3 Output-Output Skew OUTPUT 1.5V 1.5V OUTPUT t5 Notes: 4. All parameters specified with loaded outputs. 5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns. Document #: 38-07181 Rev. *B Page 5 of 9 CY2318ANZ Switching Waveforms (continued) SDRAM Buffer LH and HL Propagation Delay INPUT OUTPUT t6 t7 SDRAM Buffer Enable and Disable Times OE Three-State Active OUTPUTS t8 t9 Test Circuit VDD 0.1 µF OUTPUTS CLK out CLOAD GND Document #: 38-07181 Rev. *B Page 6 of 9 CY2318ANZ Application Circuit +3.3V Rs CPUCLK VDD BUF_IN VDDIIC 0.1 µF 0.1 µF CY2280: 48-pin SSOP Rs SDRAM[0:17] SDATA SCLK SDRAM[0:17] Ct VssIIC Vss CY2318ANZ: 48-pin SSOP Rs = Series termination resistor Ct = Optional cap to reduce EMI Ordering Information Ordering Code Package Type Operating Range CY2318ANZPVC–11 48-pin SSOP Commercial CY2318ANZPVC–11T 48-pin SSOP - Tape and Reel Commercial CY2318ANZOXC–11 48-pin SSOP Commercial CY2318ANZOXC–11T 48-pin SSOP- Tape and Reel Commercial Lead-free Document #: 38-07181 Rev. *B Page 7 of 9 CY2318ANZ Package Diagram 48-Lead Shrunk Small Outline Package O48 51-85061-*C Pentium II is a registered trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07181 Rev. *B Page 8 of 9 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2318ANZ Document History Page Document Title: CY2318ANZ 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs Document Number: 38-07181 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 111857 12/09/01 DSG Change from Spec number: 38-00771 to 38-07181 *A 121833 12/14/02 RBI Power up requirements added to Operating Conditions Information *B 310577 See ECN RGL Added Tape and Reel option Added Lead-free Devices Document #: 38-07181 Rev. *B Page 9 of 9