MITSUBISHI SEMICONDUCTOR <INTELLIGENT POWER MODULES> PM50CTJ060-3 INSULATED PACKAGE FLAT-BASE TYPE PM50CTJ060-3 ¡4th gen. planer IGBTs are integrated ¡3φ 50A, 600V Current-sense IGBT type inverter ¡Monolithic gate drive & protection logic ¡Detection, protection & status indication circuits for over-current, short-circuit, over-temperature & under-voltage ¡Acoustic noise-less 3.7kW class inverter application APPLICATION Air-conditioner, General purpose inverter, servo drives and other motor controls OUTLINE DRAWING Dimensions in mm Terminal code 1. 2. 3. 4. 5. 6. 7. 94.5 ±1 76 3.56✕17=60.52 ±0.8 4 5 6 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. FO P N U V W X=3.56±0.25mm 7.12 7 8 9 VP VWP1 VNC VN1 UN VN WN 10 11 12 13 14 15 19 2–φ0.8 64 ±0.5 16 17 18 19 20 P N U V W 5.5 5.5 10.5 5.5 1 2 3 7.12 33.6 ±0.8 44 ±1 3.56±0.3 7.12 (11.99) VUPC UP VUP1 VVPC VP VVP1 VWPC 2–φ4.5 LABEL B 8 6.35 (t=0.8) φ1.65 3.4 ±0.1 A 8 ±0.5 16 ±1 19.4 ±1 3.5 TAB #250(t = 0.8) 3.5 ±0.5 (1) 2–R5 56 ±0.8 84.5 ±0.5 3.45 ±1.25 7.95 (14.25) 14 ±0.3 0.8 ±0.1 (t = 0.4) A : DETAIL B : DETAIL Mar. 2001 MITSUBISHI SEMICONDUCTOR <INTELLIGENT POWER MODULES> PM50CTJ060-3 INSULATED PACKAGE FLAT-BASE TYPE EQUIVALENT CIRCUIT DIAGRAM VNC VN1 FO WN VN UN GND VCC FO WN VN UN VWPC WP VWP1 VVPC Tc VP VVP1 VUPC UP VUP1 GND In VCC GND In VCC GND In VCC GND GND GND Tb SWN OWN SVN OVN SUN OUN N MAXIMUM RATINGS INVERTER PART Symbol VCC VCC(surge) VCES ±IC ±ICP PC Tj GND W Out V Out U Out P (Tj = 25°C, unless otherwise noted) Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Collector current Collector current (peak) Collector dissipation Junction temperature Conditions Applied between : P-N Applied between : P-N, Surge value TC = 25°C TC = 25°C TC = 25°C Ratings 450 500 600 50 100 100 –20 ~ +125* Unit V V V A A W °C * The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the IPM to ensure safe operation. However, these power elements can endure junction temperature as high as 150°C instantaneously. To make use of this additional temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested to be provided before use. CONTROL PART Symbol VD ICIN VFO IFO Parameter Supply voltage Input current Fault output supply voltage Fault output current Conditions Applied between : VUP1-VUPC , VVP1-VVPC VWP1-VWPC, V N1-VNC At : UP, VP, WP, UN, VN, WN terminals Applied between : FO -VNC Sink current of FO terminals Ratings Unit 20 V 20 20 20 mA V mA Mar. 2001 MITSUBISHI SEMICONDUCTOR <INTELLIGENT POWER MODULES> PM50CTJ060-3 INSULATED PACKAGE FLAT-BASE TYPE TOTAL SYSTEM Symbol Parameter Supply voltage protected VCC(PROT) by OC & SC TC Module case operating temperature T stg Storage temperature Viso Isolation voltage Ratings Conditions VD = 13.5 ~ 16.5V, Inverter part, T j = 125°C start (Note 1) 60Hz, sinusoidal, Charged part to Base, AC · 1 min. Unit 400 V –20 ~ +100 –40 ~ +125 2500 °C °C Vrms Note 1 : TC measurement point. P N U V W Tc THERMAL RESISTANCES Symbol Rth(j-c)Q Rth(j-c)F Rth(c-f) Parameter Junction to case thermal resistances Contact thermal resistance ELECTRICAL CHARACTERISTICS INVERTER PART Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Parameter Test conditions Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) Case to fin, (per 1 module) thermal grease applied Limits Tye. — — — Max. 1.2 2.9 0.4 Min. — — — 0.5 — — — — — — Limits Typ. 1.8 2.0 2.5 1.0 0.1 0.3 3.0 1.0 — — Max. 2.6 3.0 3.5 2.0 — 0.9 4.0 2.0 1 10 Unit °C / W °C / W °C / W (Tj = 25°C, unless otherwise noted) Test conditions Collector-emitter saturation voltage FWD forward voltage VD = 15V, ICIN = 10mA T j = 25°C IC = 50A, Pulsed (Fig. 1) T j = 125°C –IC = 50A, VD = 15V, ICIN = 0mA (Fig. 2) Switching time VD = 15V, ICIN = 0mA↔10mA VCC = 300V, IC = 50A Tj = 125°C Inductive Load (Upper-Lower Arm) (Fig. 3) Collector-emitter cutoff current Min. — — — VCE = VCES, VD = 15V (Fig. 4) Tj = 25°C Tj = 125°C Unit V V µs µs µs µs µs mA Mar. 2001 MITSUBISHI SEMICONDUCTOR <INTELLIGENT POWER MODULES> PM50CTJ060-3 INSULATED PACKAGE FLAT-BASE TYPE CONTROL PART Symbol Parameter Test conditions VN1 -VNC VXP1-VXPC ID Circuit current VD = 15V, I CIN = 0mA Ith(ON) Ith(OFF) OC SC toff(OC) OT OTr UV UVr IFO(H) IFO(L) Input on threshold current Input off threshold current Over current trip level Short circuit trip level Over current delay time Supply circuit under voltage protection At : U P-VUPC, V P-VVPC , WP-VWPC UN · VN · WN-VNC terminals –20°C ≤ Tj ≤ 125°C, VD = 15V (Fig. 5, 6) (Lower Arm only) –20°C ≤ Tj ≤ 125°C, VD = 15V (Fig. 5, 6) (Lower Arm only) (Fig. 5, 6) VD = 15V Baseplate Trip level Temperature detection, VD = 15V Reset level Trip level –20°C ≤ Tj ≤ 125°C (Lower Arm only) Reset level Fault output current VD = 15V, VFO = 15V (Note 2) Minimum fault output pulse width VD = 15V (Note 2) tFO Over temperature protection Min. — — 1 1 65 — — 100 — 11.5 — — — Limits Typ. 25 5 3 3 91 130 10 110 90 12.0 12.5 — 10 1.0 1.8 Max. 35 10 5 5 — — — 120 — 12.5 — 0.01 15 — Unit mA mA mA A A µs °C °C V V mA mA ms Note 2 : Fault output is given only when the internal OC, SC, OT & UV protections schemes of lower arm device operate to protect it. MECHANICAL RATINGS AND CHARACTERISTICS Symbol — — Parameter Mounting torque Weight Test conditions Mounting part screw : M4 Min. 0.98 — Limits Typ. 1.18 80 Max. 1.47 — Min. 0 Limits Typ. 300 Max. 400 13.5 15.0 16.5 V 5 0 — 3.5 10 — — — 20 1 8 — mA mA kHz µs Unit N·m g RECOMMENDED CONDITIONS FOR USE Symbol Parameter VCC VD ICIN(ON) ICIN(OFF) fPWM tdead Supply voltage Input on current Input off current PWM input frequency Arm shoot-through blocking time Test conditions Applied across P-N terminals Applied between : VUP1-VUPC, VVP1-VVPC VWP1-VWPC, VN1- VNC At : UP, VP, WP, UN, VN, WN terminals For IPM’s each input signals, (Fig. 7) For IPM’s each input signals, (Fig. 7) Unit V Mar. 2001 MITSUBISHI SEMICONDUCTOR <INTELLIGENT POWER MODULES> PM50CTJ060-3 INSULATED PACKAGE FLAT-BASE TYPE PRECAUTIONS FOR TESTING 1. Before appling any control supply voltage (VD), the input signals should be turned on from its off state. After this, the specified ON and OFF level setting for each input signal should be done. 2. When performing “OC” and “SC” tests, the turn-off surge voltage spike at the corresponding protection operation should not be allowed to rise above V CES rating of the device. (These test should not be done by using a curve tracer or its equivalent.) P,(U,V,W) P, (U,V,W,B) ICIN Ic V VD (all) U,V,W,(N) VD (all) U,V,W, (N) –Ic V all open Fig.2 VEC Test Fig.1 VCE(sat) Test a) Lower Arm Switching P trr Signal input (Upper Arm) Signal input (Lower Arm) ICIN IC 90% U,V,W VD(all) N b) Upper Arm Switching 90% IC 10% 10% P Signal input (Upper Arm) ICIN Vce Irr VCC tc (on) tc (off) ICIN U,V,W VCC td (on) Signal input (Lower Arm) tr td (off) ton= td (on) + tr tf toff= td (off) + tf N VD(all) IC Fig. 3 Switching time Test circuit and waveform P,(U,V,W) Signal input A ICIN Over Current Pulse ICIN VCC VD(all) U,V,W,(N) Constant Current IC Fig.4 ICES Test OC toff (OC) P,(U,V,W) Signal input Short Circuit ICIN SC VCC Constant Current IC VD(all) U,V,W,(N) IC toff (OC) Fig. 6 OC and SC Test waveform Fig. 5 OC and SC Test P VD ICINP U,V,W VCC VD ICINN N Snubber IC ICINP t 0A ICINN t 0A tdead tdead tdead Fig. 7 Dead time measurement point example Mar. 2001 MITSUBISHI SEMICONDUCTOR <INTELLIGENT POWER MODULES> PM50CTJ060-3 INSULATED PACKAGE FLAT-BASE TYPE P VUP1 + VD1 UP VUPC 560 VVP1 + VD2 VP VVPC 560 VWP1 + VD3 WP VWPC OUT VCC In GND GND VCC OUT U In GND GND VCC OUT V In GND Tc Tb 560 GND W GND 560 UN UN OUN 560 N SUN VN VN 560 OVN WN WN SVN FO FO VN1 VCC OWN SWN 33 VD4 VNC GND NOTES FOR STABLE AND SAFE OPERATION ; Design the PCB pattern to minimize wiring length between opto-coupler and IPM’s input terminal, and also to minimize the stray capacity between the input and output wirings of opto-coupler. Connect low impedance capacitor between the Vcc and GND terminal of each switching opto-coupler. Slow switching opto-coupler : CTR = 100%~200% Use 4 isolated control power supplies (VD). Also, care should be taken to minimize the instantaneous voltage charge of the power supply. Make inductance of DC bus line as small as possible, and minimize surge voltage using snubber capacitor between P and N terminal. Use line noise filter capacitor (ex. 4.7nF) between each input AC line and ground to reject common-mode noise from AC line and improve noise immunity of the system. • • • • • • Mar. 2001