PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 07/28/06 500MHz HSTL Potato Chip DESCRIPTION: FEATURES: . Patented Technology . Four HSTL differential outputs . The two pair of LVDS/LVPECL/HSTL/ differential or single-ended inputs . Hot-swappable/-insertable . Operating frequency up to 500MHz with 2pf load . Operating frequency up to 480MHz with 5pf load . Operating frequency up to 400MHz with 15pf load . Very low output pin to pin skew < 80ps . Very low pulse skew < 80ps . 2.8-ns propagation delay (typical) . 2.4V to 3.6V power supply . Industrial temperature range: –40°C to 85°C . 20-pin 209 mil SSOP package VCC NC VCC CLK_SEL CLKA CLKA# CLKB CLKB# VEE VCC 1 2 3 4 5 6 7 8 9 10 PO74HSTL314 Pin Configuration The PO74HSTL314 is a low-skew, 2-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on 0.35um CMOS technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 500MHz . The device features two differential input paths that are multiplexed plexed internally. This mux is controlled by the CLK_SEL pin. The PO74HSTL314 may function not only as a differential clock buffer but also as a signal-level translator and fanout on HSTL or LVCMOS / LVTTL single-ended signal to four HSTL differential loads. Since the PO74HSTL314 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Logic Block Diagram 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q0# Q0 Q0# VCC CLKA CLKA# Q1 Q1# Q1 Q1# VEE VCC Q2 Q2# Q3 CLKB CLKB# Q3# CLK_SEL Q2 Q2# VEE Q3 Q3# VCC VEE 1 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 08/03/06 500MHz HSTL Potato Chip Pin Definitions Name Pin I/O VCC Description Type 1, 10,11,20,3 VCC 2 NC 4 CLK_SEL I,PD LVCMOS 5 CLKA I,PD LVDS, PECL, HSTL Default differential clock input 6 CLKA# I,PU LVDS, PECL, HSTL Input clock select with pull up resistor 7 CLKB I,PD LVDS, PECL, HSTL Input clock select with pull down resistor 8 CLKB# I,PU LVDS, PECL, HSTL Input clock select with pull up resistor Power Power supply, positive connection No connect Input clock select with pull down resistor 9 VEE Power Ground Q[0:3]# GND O Power 18, 16,14,12 HSTL Complement output 19, 17,15,13 Q[0:3] O HSTL Ture output Function Table Control CLK_SEL 0 CLKA, CLKA# input pair is active (Default condition with no connection to pin) CLKA can be driven with LVDS, ECL, PECL, HSTL or TTL compatible signals with respective power configurations 1 CLKB, CLKB# input pair is active CLKB can be driven with LVDS, ECL, PECL, HSTL or TTL compatible signals with respective power configurations Pin Characteristics Symbol Parameter CIN Input Capacitance RPULLUP RPULLDOWN Test Conditions Minimum Typical Maximum Units 4 pF Input Pullup Resistor 88 KΩ Input Pulldown Resistor 88 KΩ 2 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 07/28/06 500MHz HSTL Potato Chip Maximum Ratings Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -40 to 85 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to +5.5 V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description VOH Output High voltage VOL Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V VIK Clamp diode voltage Vcc = Min. And IIN = -18mA - -0.7 -1.2 V IOFF Power off output leakage current Vcc = 0V. Vi or Vo = 0V to 5.5V - - +-5 uA Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 3 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 07/28/06 500MHz HSTL Potato Chip Power Supply Characteristics Symbol IccQ Description Quiescent Power Supply Current Test Conditions (1) Min Typ Max Unit Vcc=Max, Vin=Vcc or GND - 0.1 30 uA Notes: 1. 2. 3. 4. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25°C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Switching Characteristics Symbol tPD tr/tf Description Propagation Delay CLKA or CLKB to Output pair Rise/Fall Time Test Conditions (1) M ax Unit CL = 15pF 3.2 ns 0.8V – 2.0V ns ps tsk(p) Pulse Skew (Same Package) CL = 15pF, 125MHz 0.8 80 tsk(o) Output Pin to Pin Skew (Same Package) CL = 15pF, 125MHz 80 ps Output Skew (Different Package) CL = 15pF, 125MHz 350 ps MHz MHz tsk(pp) fmax fmax Input Frequency CL =15pF Input Frequency CL = 5pF 400 250 480 300 fmax Input Frequency CL = 2pF 500 400 MHz Notes: 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz 4 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 07/10/06 500MHz HSTL Potato Chip Test Waveforms FIGURE 1. LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS VCC VCC= 3.3V VIH VPP VPP RANGE 0V-VCC VIL VEE=0.0V VEE FIGURE 2. HSTL/HSTL OUTPUT tr,tf, 20-80% VO FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for both CLKA or CLKB to output pair INPUT CLOCK VPP TPLH TPD TPHL OUTPUT CLOCK VO tSK(O) ANOTHER OUTPUT CLOCK 5 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 07/10/06 500MHz HSTL Potato Chip Test Circuit 50pF to 2pF 50Ω 50pF to 2pF 50Ω Packaging Mechanical Drawing: 20 pin SSOP 20 0.55 .022 0.95 .037 .197 .220 1 5.00 5.60 .272 .295 6.90 7.50 .004 .009 .291 .322 7.40 8.20 0.09 0.25 .078 2.00 Max SEATING PLANE .0256 BSC 0.65 .0098 Max. 0.25 .002 Min 0.050 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 6 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 07/28/06 500MHz HSTL Potato Chip Ordering Information Ordering Code Package Top-Marking TA PO74HSTL314ASU 20pin SSOP Tube Pb-free & Green PO74HSTL314AS -40°C to 85°C PO74HSTL314ASR 20pin SSOP Tape and reel Pb-free & Green PO74HSTL314AS -40°C to 85°C 7 Copyright © Potato Semiconductor Corporation