MITSUBISHI MITSUBISHI SEMICONDUCTOR SEMICONDUCTOR <Application <Application Specific Specific Intelligent Intelligent Power Power Module> Module> PS11014 PS11014 FLAT-BASE FLAT-BASE TYPE TYPE INSULATED INSULATED TYPE TYPE PS11014 INTEGRATED FUNCTIONS AND FEATURES • Converter bridge for 3 phase AC-to-DC power conversion. • Circuit for dynamic braking of motor regenerative energy. • 3-phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technology. • Inverter output current capability IO (Note 1): Type Name PS11014 100% load 5.0A (rms) 150% over load 7.5A (rms), 1min (Note 1) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : IOP = IO × √ 2 INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS: • For inverter side upper-leg IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short circuit protection (SC). Bootstrap circuit supply scheme (single drive power supply) and Under voltage protection (UV). • For inverter side lower-leg IGBTs : Drive circuit, Short circuit protection (SC). Control supply circuit under- & over- voltage protection (OV/UV). System over temperature protection (OT). Fault output signaling circuit (FO) and Current limit warning signal output (CL). • For Brake circuit IGBT : Drive circuit • Warning and Fault signaling : FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through. FO2 : N-side control supply abnormality locking (OV/UV). FO3 : System over-temperature protection (OT). CL : Warning for inverter current overload condition • For system feedback control : Analogue signal feedback reproducing actual inverter output phase currents (3φ). • Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection. APPLICATION Acoustic noise-less 0.75kW/AC200V class 3 phase inverter and other motor control applications PACKAGE OUTLINES 0.5 4-R2 12 3 4 ✽ 6 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ✽ 0.5 2 ± 0.3 82 ± 0.8 94.2 ± 1 5 24 50 2424 Terminals Assignment: 7 8 91011121314151617181920212223 2-φ4 32 33 34 35 36 37 38 39 40 22.6 ✽ 0.6 29 5.08 ± 0.3 ✕ 9 = 45.72 ± 0.8 31 (16.25) 5 2-R4 CBU+ CBU– CBV+ CBV– CBW+ CBW– GND NC VDH CL FO1 FO2 FO3 CU CV CW UP VP WP UN 21 VN 22 WN 23 Br 31 32 33 34 35 36 37 38 39 40 R S T P1 P2 N B U V W 62 ± 1 0.4 54 ± 0.5 0.8 12 0~0.8 0.3 ✽ Main terminal top portion details ± 0.5 0 ± 0.5 0 0.35MAX 0.5 ✽ Control Pin top portion details 0~0.8 27 ± 1 20.4 ± 1 12 LABEL 8.5 3.5 1.2 0.6 0.5 ± 0.03 (Fig. 1) Jan . 2000 MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLAT-BASE TYPE INSULATED TYPE C3 ; 3.3µF or more, tight tolerance, temp-compensated electrolytic type (Note : the value may change depending on the type PWM control scheme used in the applied system) C4 ; 2µF R-category ceramic condenser for noise filtering. Application Specific Intelligent Power Module Protection Circuit CBW– CBW+ C4,C3 CBU– CBU+ CBV– CBV+ INTERNAL FUNCTIONS BLOCK DIAGRAM Level shifter Drive Circuit P2 Brake resistor connection, B Inrush prevention P1 circuit, etc. AC200V line input R S T Z U V W C M AC 200V line output T.S. N Z : Surge absorber. C : AC filter (Ceramic condenser 2.2~6.5nF) [Note : Additionally an appropriate Line-to line surge absorber circuit maybe necessary depending on the application environment]. Current sensing circuit CUCVCW Analogue signal output corresponding to each phase current (5V line) Note 1) Trig signal conditioning Drive Curcuit FO Logic Protection circuit Control supply fault sense UP VP WPUN VN WN Br CL FO1 FO2 FO3 Each phase input (PWM) Fault output (5V line) Note 2) (5V line) Note 3) C2 C2 ; 3.3µF or more GND VDH (15V line) Note 1) To prevent chances of signal oscillation, an RC coupling at each output is recommended. (see also Fig.10) Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU, without any opto or transformer isolation ispossible. (see also Fig.10) Note 3) All these outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig.10) Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC powerinput pins. (Fig. 2) MAXIMUM RATINGS (Tj = 25°C) INVERTER PART (Including Brake Part) Symbol VCC Item Supply voltage VCC(surge) Supply voltage (surge) VP or VN VP(S) or VN(S) ±IC(±ICP) IC(ICP) IF (IFP) Condition Applied between P2-N Ratings 450 Unit V 500 V 600 V 600 V ±15 (±30) A 4 (8) 4 (8) A Ratings 800 Unit V 3φ rectifying circuit 220 25 V A 1 cycle at 60Hz, peak value non-repetitive Value for one cycle of surge current 196 160 A A 2s Ratings Unit 20 V –0.5 ~ 7.5 V –0.5 ~ 7 15 mA Applied between P2-N, Surge-value Applied between P-U, V, W, Br or U, V, W, Each output IGBT collector-emitter static voltage Br-N Each output IGBT collector-emitter Applied between P-U, V, W, Br or U, V, W, switching surge voltage Br-N Each output IGBT collector current TC = 25°C Brake IGBT collector current Brake diode anode current Note: “( )” means IC peak value A CONVERTER PART Symbol VRRM Item Repetitive peak reverse voltage Ea IO Recommended AC input voltage DC output current IFSM I2t Surge (non-repetitive) forward current I2t for fusing Condition CONTROL PART Symbol Item VDH , VDB Supply voltage VCIN Input signal voltage VFO IFO Fault output supply voltage Fault output current VCL Current-limit warning (CL) output voltage CL output current ICL ICO Analogue current signal output current Condition Applied between VDH-GND, CBU+-CBU– , CBV+-CBV–, CBW+ -CBW– Applied between UP · V P · WP · U N · V N · W N · Br-GND Applied between F O1 · FO2 · FO3-GND Sink current of F O1 · FO2 · FO3 Applied between CL-GND Sink current of CL Sink current of CU · CV · CW –0.5 ~ 7 15 ±1 V V mA mA Jan. 2000 MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLAT-BASE TYPE INSULATED TYPE TOTAL SYSTEM Symbol Tj Item Junction temperature T stg TC Storage temperature Module case operating temperature Viso Isolation voltage — Ratings Unit (Note 2) –20 ~ +125 °C (Fig. 3) –40 ~ +125 –20 ~ +100 °C °C 2500 Vrms 0.78 ~ 1.27 kg·cm Condition — 60 Hz sinusoidal AC applied between all terminals and the base plate for 1 minute. Mounting screw: M3.5 Mounting torque Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. However, these power elements can endure junction temperature as high as 150°C instantaneously . To make use of this additional temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested to be provided before use. CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface) TC (Fig. 3) THERMAL RESISTANCE Symbol Condition Item Min. Ratings Typ. Max. Unit °C/W Rth(j-c) Q Rth(j-c) F Inverter IGBT (1/6) Inverter FWDi (1/6) — — — — 2.8 3.9 Junction to case Thermal Rth(j-c)QB Resistance Rth(j-c) FB Brake IGBT Brake FWDi — — — — 5.8 6.0 Rth(j-c)FR Converter Di (1/6) — — 4.3 °C/W °C/W Case to fin, thermal grease applied (1 Module) — — 0.044 °C/W Min. — Ratings Typ. — Max. 2.9 Tj = 25°C, IC = –15A, Input = OFF — — 2.9 V V VDH = 15V, Input = ON, Tj = 25°C, IC = 4A — — 3.5 V Tj = 25°C, IF = 4A, Input = OFF — — — — 2.9 8 1/2 Bridge inductive load, Input = ON — 0.3 — 0.6 1.5 1.5 VCC = 300V, Ic = 15A, Tj = 125°C VDH = 15V, VDB = 15V — — 0.2 1.1 0.6 1.8 Note : ton, toff include delay time of the internal control circuit — — 0.4 0.1 1.0 — V mA V µs µs µs µs µs Rth(c-f) Contact Thermal Resistance °C/W °C/W ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted) Symbol VCE(sat) VEC Condition Item Collector-emitter saturation voltage FWDi forward voltage VDH = VDB = 15V, Input = ON, Tj = 25°C, IC = 15A VFBr Brake IGBT Collector-emitter saturation voltage Brake diode forward voltage IRRM VFR Converter diode reverse current VR = VRRM , Tj = 125°C Tj = 25°C, IF = 10A Converter diode voltage VCE(sat)Br ton tc(on) Switching times toff tc(off) trr FWD reverse recovery time Short circuit endurance (Output, Arm, and Load, Short Circuit Modes) Switching SOA VCC ≤ 400V, Input = ON (one-shot) Tj = 125°C start 13.5V ≤ VDH = VDB ≤ 16.5V VCC ≤ 400V, Tj ≤ 125°C, Ic < IOL(CL) operation level, Input = ON 13.5V ≤ VDH = VDB ≤ 16.5V Unit • No destruction • FO output by protection operation • No destruction • No protecting operation • No FO output Jan . 2000 MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLAT-BASE TYPE INSULATED TYPE ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted) Symbol IDH Vth(on) Vth(off) Ri fPWM txx tdead tint VCO Condition Item Circuit current Input on threshold voltage Input off threshold voltage Input pull-up resistor PWM input frequency Allowable input on-pulse width Allowable input signal dead time for blocking arm shoot-through Input inter-lock sensing Analogue signal linearity with V C+(200%) output current V C–(200%) Offset change area vs temperature |∆VCO | VC+ Analogue signal output voltage limit VDH = 15V, VCIN = 5V Integrated between input terminal-VDH TC ≤ 100°C, Tj ≤ 125°C (Note 3) VDH = 15V, T C = –20°C ~ +100°C Relates to corresponding input (Except brake part) T C = –20°C ~ +100°C Relates to corresponding input (Except brake part) Ic = 0A Ic = IOP(200%) Ic = –IOP (200%) VDH = 15V TC = –20°C ~ +100°C (Fig. 4) VDH = 15V, TC = –20°C ~ +100°C Ic > IOP(200%), VDH = 15V (Fig. 4) VC– ∆VC(200%) Analogue signal over all linear variation |VCO-VC±(200%)| rCH Analogue signal data hold accuracy Correspond to max. 500µs data hold period only, Ic = IOP(200%) (Fig. 5) td(read) ±IOL Analogue signal reading time Current limit warning (CL) operation level After input signal trigger point VDH =15V, TC = –20°C ~ +100°C ICL(H) ICL(L) Signal output current of CL operation SC OT OTr UVDH Idle Active Short circuit over current trip level Trip level Over temperature protection Reset level UVDB UVDBr tdV IFO(H) IFO(L) (Fig. 7) (Note 5) VDH =15V Trip level Reset level UVDHr OVDH OVDHr (Fig. 8) (Note 4) Open collector output Tj = 25°C Supply circuit under & over voltage protection Fault output current Trip level Reset level Trip level Reset level Filter time Idle Active — 0.8 2.5 — 2 1 Ratings Typ. — 1.4 3.0 150 — — 2.2 — Min. TC = –20°C ~ +100°C Tj ≤ 125°C Open collector output Max. Unit 150 2.0 4.0 — 20 500 mA V V kΩ kHz µs — µs — 65 100 ns 1.87 0.77 2.97 — 2.27 1.17 2.57 1.47 V 3.37 15 3.67 — — 4.0 — — — 1.1 0.7 — — –5 — 5 % — 14.05 3 17.30 — 20.80 µs A — — — 1 1 — µA mA 23.2 100 43.0 110 62.0 120 A °C — 11.05 90 12.00 — 12.75 °C V 11.55 18.00 12.50 19.20 13.25 20.15 V V 16.50 17.50 18.65 V 10.0 10.5 11.0 11.5 12.0 12.5 — — 10 — — 1 V V µs µA — 1 — mA V V mV V V V (Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only. (b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit. (Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme. (Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momentarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropriately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back from its FO1 pin of the ASIPM indicating a short circuit situation. RECOMMENDED CONDITIONS Symbol VCC Item Supply voltage Condition Applied across P2-N terminals VDH , VDB Control supply voltage Applied between V DH-GND, CBU+-CBU– , CBV+-CBV–, CBW+ -CBW– ∆VDH, ∆V DB Supply voltage ripple VCIN(on) Input on voltage VCIN(off) Input off voltage fPWM PWM Input frequency tdead Arm shoot-through blocking time Using application circuit Using application circuit Ratings 400 (max.) Unit V 15±1.5 V ±1 (max.) 0 ~ 0.3 V/µs 4.8 ~ 5.0 2 ~ 20 2.2 (min.) V V kHz µs Jan. 2000 MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLAT-BASE TYPE INSULATED TYPE Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING LINEARITY Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING “DATA HOLD” DEFINITION 5 VC VC– 4 min VDH=15V TC= –20~100˚C max 500µs VC–(200%) 3 0V VCH(5µs) VC(V) VC0 2 rCH= VC+(200%) 1 Analogue output signal data hold range 0 –400 –300 –200 –100 0 VC+ 100 200 300 400 VCH(505µs) VCH(505µs)-VCH(5µs) VCH(5 µs) Note ; Ringing happens around the point where the signal output voltage changes state from “analogue” to “data hold” due to test circuit arrangement and instrumentational trouble. Therefore, the rate of change is measured at a 5 µs delayed point. Real load current peak value.(%)(Ic=Io✕ 2) (Fig. 4) Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART Input signal VCIN(p) of each phase upper arm 0V Input signal VCIN(n) of each phase lower arm 0V Gate signal Vo(p) of each phase upper arm (ASIPM internal) 0V Gate signal Vo(n) of each phase upper arm (ASIPM internal) 0V Error output FO1 0V Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simultaneously in “LOW” level. By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F O” signal is outputted. After an “input interlock” operation the circuit is latched. The “FO” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later. Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION Input signal VCIN of each phase upper arm 0V Short circuit sensing signal VS 0V Gate signal Vo of each phase upper arm(ASIPM internal) Error output FO1 SC delay time 0V 0V Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”). Jan . 2000 MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLAT-BASE TYPE INSULATED TYPE Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART N-side IGBT Current N-side FWDi Current off VCIN on on V(hold) off IC 0 +ICL (VS) 0 –ICL t(hold) VC Ref 0 off VCL on Delay time td(read) Fig. 9 START-UP SEQUENCE Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT Normally at start-up, Fo and CL output signals will be pulled-up High to Supply voltage (OFF level); however, FO1 output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT. This can happen particularly when the boot-strap capacitor is of large size. FO1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph 5V ASIPM 5.1kΩ DC-Bus voltage Control voltage supply VPN 0 PWM starts a) VDH 0 Boot-strap voltage VDB N-Side input signal VCIN(N) P-Side input signal VCIN(P) on Brake input signal VCIN(Br) on FO1 output signal FOI 0 UP,VP,WP,UN,VN,WN,Br R CPU F01,F02,F03,CL 10kΩ CU,CV,CW b) 0.1nF on R 0.1nF GND(Logic) on a) Boot-strap charging scheme : Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20µs number of pulses =10 ~ 500 depending on the boot-strap capacitor size) b) FO1 resetting sequence: Apply ON signals to the following input pins : Br → Un/Vn/Wn → Up/Vp/Wp in that order. Jan. 2000