Preliminary R2J20605ANP Integrated Driver – MOS FET (DrMOS) REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Description The R2J20605ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating the need for an external SBD for this purpose. Integrating a driver and both high-side and low-side power MOS FETs, the new device is also compliant with the package standard "integrated Driver – MOS FET (DrMOS)" proposed by Intel Corporation. Features Built-in power MOS FET suitable for Notebook, Desktop, Server application Built-in driver circuit which matches the power MOS FET Low-side MOS FET with built-in SBD for lower loss and reduced ringing Built-in tri-state input function which can support a number of PWM controllers VIN operating-voltage range: 27 V max High-frequency operation (above 1 MHz) possible Large average output current (Max. 40 A) Achieve low power dissipation Controllable driver: Remote on/off Low-side MOS FET disabled function for DCM operation Built-in thermal warning Built-in bootstrapping switch Small package: QFN56 (8 mm 8 mm 0.95 mm) Terminal Pb-free/Halogen-free Outline VCIN BOOT GH 1 VIN 14 15 56 Reg5V Driver PAD High-side MOS PAD DISBL# VSWH MOS FET Driver LSDBL# Low-side MOS PAD PWM 43 THWN CGND GL PGND 28 42 29 (Bottom view) QFN56 package 8 mm × 8 mm REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 1 of 16 R2J20605ANP Preliminary Block Diagram Driver Chip VCIN THWN Reg5V UVL THWN BOOT GH Boot SW VIN Reg5V DISBL# High Side MOS FET 20 μA Supervisor CGND Reg5V Level Shifter 25 k 150 k LSDBL# Reg5V VSWH PWM Overlap Protection. & Logic Input Logic (TTL Level) (3 state in) Low Side MOS FET Reg5V 20 μA PGND CGND GL Notes: 1. Truth table for the DISBL# pin. DISBL# Input "L" "Open" "H" 2. Truth table for the LSDBL# pin. Driver Chip Status Shutdown (GL, GH = "L") Shutdown (GL, GH = "L") Enable (GL, GH = "Active") 3. Output signal from the UVL block UVL output Logic Level For shutdown "L" VCIN VL REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 2 of 16 VH "L" "Open" "H" GL Status "L" "Active" "Active" 4. Output signal from the THWN block For active "H" LSDBL# Input "H" Thermal Warning Logic Level "L" Normal operating Thermal Warning TIC(°C) TwarnL TwarnH R2J20605ANP Preliminary BOOT VCIN NC LSDBL# CGND 10 CGND 11 GH 12 9 8 7 6 5 4 3 2 1 15 56 PWM 16 55 DISBL# 17 54 Reg5V 53 THWN 19 52 GL VIN 20 51 CGND VSWH 21 50 VSWH PGND 22 49 23 48 VIN 18 CGND 24 25 46 26 45 27 44 28 43 31 32 33 34 35 36 37 38 39 40 41 VSWH 42 VSWH 30 PGND 29 VSWH PGND 47 VSWH PGND VIN 13 NC 14 VIN VIN Pin Arrangement (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name CGND LSDBL# NC VCIN BOOT GH VIN VSWH PGND GL THWN Reg5V DISBL# PWM Pin No. 1, 6, 51, Pad 2 3, 8 4 5 7 9 to 20, Pad 21, 40 to 50, Pad 22 to 39 52 53 54 55 56 Description Control signal ground Low-side gate disable No connect Control input voltage Bootstrap voltage pin High-side gate signal Input voltage Phase output/Switch output Power ground Low-side gate signal Thermal warning +5 V logic power supply output Signal disable PWM drive logic input REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 3 of 16 Remarks Should be connected to PGND externally When asserted "L" signal, Low-side gate disable Driver Vcc input To be supplied +5 V through internal BOOT SW Pin for Monitor Pin for Monitor Disabled when DISBL# is "L" 5 V logic input R2J20605ANP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Symbol Pt(25) Pt(110) Iout VIN(DC) VIN(AC) VSWH(DC) VSWH(AC) VBOOT(DC) VBOOT(AC) VCIN Vpwm Average output current Input voltage Switch node voltage BOOT voltage Supply voltage PWM voltage Other I/O voltage Reg5V voltage Reg5V current Vdisble, Vlsdbl, Vthwn Vreg5V Ireg5V THWN current Operating junction temperature Storage temperature Ithwn Tj-opr Tstg Notes: 1. 2. 3. 4. 5. 6. 7. 8. Rating 25 8 40 –0.3 to +27 30 27 30 32 36 –0.3 to +27 Units W A V V V V V –0.3 to +5.5 @UVL OFF –0.3 to +0.3 @UVL ON –0.3 to Reg5V + 0.3 2 –0.3 to +6 –20 to +0.1 V mA 7 3 0 to 1.0 –40 to +150 –55 to +150 mA °C °C 3 Average Output Current (A) VOUT = 1.3 V VIN = 12 V VCIN = Reg5V = 5 V L = 0.45 μH fsw = 600 kHz 25 REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 4 of 16 50 2, 4 2, 5 2, 7, 8 V Safe Operating Area 0 2 2, 4, 6 2 2, 4, 6 2 2, 4, 6 2 –0.3 to VCIN + 0.3 Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. Rated voltages are relative to voltages on the CGND and PGND pins. For rated current, (+) indicates inflow to the chip and (–) indicates outflow. This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode). This rating is when UVL (Under Voltage Lock out) is effective (lock out mode). The specification values indicated "AC" are limited within 100 ns. This rating is when the external power-source is applied to Reg5V pin. Reg5V + 0.3 V < 6 V 50 45 40 35 30 25 20 15 10 5 0 Note 1 75 100 125 PCB Temperature (°C) 150 175 R2J20605ANP Preliminary Recommended Operating Condition Item Input voltage Supply voltage Symbol VIN VCIN Rating 4.5 to 22 Units V V 4.5 to 5.5 or 8 to 22 Note When the usage of VCIN = 4.5 V to 5.5 V, VCIN should be connected to Reg5V (Refer to "Pin Connection") Electrical Characteristics (Ta = 25C, VCIN = 12 V, VSWH = 0 V, unless otherwise specified) Item Supply PWM input 5V regulator DISBL# input Symbol Min Typ Max Units Test Conditions VCIN start threshold VH 7.0 7.4 7.8 V VCIN shutdown threshold VL 6.6 7.0 7.4 V UVLO hysteresis dUVL — 0.4 — V VCIN operating current ICIN — 52 — mA fPWM = 1 MHz, Ton_pwm = 120 ns VCIN disable current ICIN-DISBL — — 2.5 mA DISBL# = 0 V, PWM = 0 V, LSDBL# = Open PWM rising threshold VH-PWM 3.0 3.4 3.8 V PWM falling threshold VL-PWM 0.9 1.2 1.5 V PWM input resistance RIN-PWM 10 20 40 k VL-PWM — VH-PWM V — 100 — ns Tri-state shutdown window VIN-SD Shutdown hold-off time tHOLD-OFF *1 VH – VL PWM = 1 V Output voltage Vreg 4.95 5.2 5.45 V Line regulation Vreg-line –10 0 10 mV VCIN = 12 V to 16 V Load regulation Vreg-load –10 0 10 mV Ireg = 0 to 10 mA Disable threshold VDISBL 0.9 1.2 1.5 V Enable threshold VENBL 1.9 2.4 2.9 V Input current IDISBL 10 20 40 A DISBL# = 1 V LSDBL# input Low-side activation threshold VLSDBLH 1.9 2.4 2.9 V Low-side disable threshold VLSDBLL 0.9 1.2 1.5 V Input current ILSDBL –56 –28 –14 A LSDBL# = 1 V Thermal warning Warning temperature TTHWN *1 95 115 135 °C Driver IC temperature Temperature hysteresis THYS *1 — 15 — °C Note: 1 THWN on resistance RTHWN * 0.2 0.5 1.0 k THWN = 0.2 V THWN leakage current ILEAK — 0.001 1.0 A THWN = 5 V 1. Reference values for design. Not 100% tested in production. REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 5 of 16 R2J20605ANP Preliminary Typical Application (1) Desktop/Server Application +12 V VCIN THWN BOOT VIN DISBL# Reg5V R2J20605ANP PGND PWM CGND LSDBL# GH +5 V VCIN VSWH THWN GL BOOT VIN DISBL# Reg5V R2J20605ANP PWM VSWH PGND CGND LSDBL# GH GL PWM1 PWM Control Circuit +1.3 V PWM2 PWM3 PWM4 VCIN THWN BOOT VIN DISBL# Reg5V R2J20605ANP PGND PWM CGND LSDBL# GH VCIN VSWH THWN GL BOOT VIN DISBL# Reg5V R2J20605ANP PWM CGND LSDBL# GH REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 6 of 16 VSWH PGND GL Power GND Signal GND R2J20605ANP Preliminary Typical Application (cont.) (2) Notebook Application +19 V +5 V VCIN THWN BOOT VIN DISBL# Reg5V R2J20605ANP PGND PWM CGND LSDBL# GH VCIN VSWH THWN GL BOOT VIN DISBL# Reg5V R2J20605ANP PWM VSWH PGND CGND LSDBL# GH GL PWM1 PWM Control Circuit +1.1 V PWM2 PWM3 VCIN THWN BOOT DISBL# VIN Reg5V R2J20605ANP PWM CGND LSDBL# GH REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 7 of 16 VSWH PGND GL Power GND Signal GND R2J20605ANP Preliminary Pin Connection (1) Typical Desktop/Server Application 0.1 μF 1.0 μF CGND 0 to 10Ω VIN 12 V Low Side Disable Signal INPUT 7 6 5 4 3 2 NC LSDBL# 16 17 VIN PAD 18 PGND 1 CGND 8 VCIN 15 9 BOOT 10 CGND 11 NC 12 GH 13 VIN 14 VIN CGND 10 μF × 4 PWM 56 DISBL# 55 Reg5V 54 THWN 53 GL 52 CGND 51 VSWH 50 CGND PAD 19 20 VIN 21 VSWH 22 PGND R2J20605ANP 1.0 μF DISBL# INPUT 51 kΩ 49 +5 V 48 23 VSWH PAD 24 25 47 46 Thermal Warning 45 26 44 29 30 31 32 33 34 35 36 37 38 VSWH PGND PGND 27 28 PWM INPUT 39 40 VSWH 41 43 42 0.45 μH Vout PGND PGND (2) Typical Notebook Application 0.1 μF Low Side Disable Signal INPUT 0 to 10Ω VIN 19 V 8 7 6 5 4 3 2 VCIN NC LSDBL# 16 17 VIN PAD 18 PGND CGND PAD 1 CGND 9 BOOT 10 CGND 11 NC 12 GH 15 13 VIN 14 VIN CGND 10 μF × 4 PWM 56 DISBL# 55 Reg5V 54 THWN 53 GL 52 CGND 51 VSWH 50 19 20 VIN 21 VSWH 22 PGND R2J20605ANP 49 23 1.0 μF VSWH PAD 25 5.0 V External Power Supply DISBL# INPUT 51 kΩ +5 V 48 24 47 46 26 Thermal Warning 45 27 29 30 31 32 33 34 35 36 37 38 VSWH 44 PGND PGND 28 PWM INPUT 39 40 VSWH 41 43 42 0.45 μH Vout PGND REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 8 of 16 PGND R2J20605ANP Preliminary Test Circuit Vinput A IIN V VIN Vcont A ICIN VCIN V VCIN BOOT DISBL# VIN R2J20605ANP Reg5V VSWH LSDBL# THWN 5 V pulse PWM CGND Note: PIN = IIN × VIN + ICIN × VCIN POUT = IO × VO Efficiency = POUT / PIN PLOSS(DrMOS) = PIN – POUT Ta = 27°C REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 9 of 16 PGND GH Electric load IO GL Average Output Voltage Averaging V VO circuit R2J20605ANP Preliminary Typical Data Power Loss vs. Input Voltage Power Loss vs. Output Current 1.6 10 VCIN = Reg5V = 5 V VIN = 12 V 1.5 VOUT = 1.3 V Normalized Power Loss @ VIN = 12 V Power Loss (W) 9 VCIN = Reg5V = 5 V 8 VOUT = 1.3 V fPWM = 600 kHz 7 L = 0.45 μH 6 5 4 3 2 IOUT = 30 A 1.3 1.2 1.1 1.0 0.9 0.8 1 0 fPWM = 600 kHz 1.4 L = 0.45 μH 0 5 10 15 20 25 30 35 0.7 40 4 6 8 Power Loss vs. Output Voltage 14 16 18 20 22 Power Loss vs. Switching Frequency 1.6 1.6 VIN = 12 V VIN = 12 V 1.5 VCIN = Reg5V = 5 V fPWM = 600 kHz 1.4 L = 0.45 μH IOUT = 30 A 1.2 1.1 1.0 0.9 Normalized Power Loss @ fPWM = 600 kHz 1.5 VCIN = Reg5V = 5 V Normalized Power Loss @ VOUT = 1.3 V 12 Input Voltage (V) Output Current (A) 1.3 10 VOUT = 1.3 V 1.4 L = 0.45 μH 1.3 IOUT = 30 A 1.2 1.1 1.0 0.9 0.8 0.8 0.7 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 0.7 250 Output Voltage (V) REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 10 of 16 500 750 1000 Switching Frequency (kHz) 1250 R2J20605ANP Preliminary Typical Data (cont.) Power Loss vs. VCIN Power Loss vs. Output Inductance 1.6 1.6 VIN = 12 V VIN = 12 V 1.5 VOUT = 1.3 V VOUT = 1.3 V 1.4 fPWM = 600 kHz 1.3 Normalized Power Loss @ VCIN = 5 V Normalized Power Loss @ L = 0.45 μH 1.5 VCIN = Reg5V = 5 V IOUT = 30 A 1.2 1.1 1.0 0.9 IOUT = 30 A 1.3 VCIN = Reg5V 1.2 1.1 1.0 0.9 0.8 0.8 0.7 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.7 4.5 Average ICIN vs. Switching Frequency 80 VIN = 12 V 70 VCIN = Reg5V = 5 V VOUT = 1.3 V L = 0.45 μH 60 IOUT = 0 A 50 40 30 20 10 250 500 750 1000 Switching Frequency (kHz) REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 11 of 16 5.0 5.5 VCIN (V) Output Inductance (μH) Average ICIN (mA) fPWM = 600 kHz 1.4 L = 0.45 μH 1250 6.0 R2J20605ANP Preliminary Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, lowside MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & DISBL# The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the buit-in 5 V regulator is disabled as long as VCIN is 7.4 V or less. On cancellation of UVL, the built-in 5 V regulator remains enabled until the UVL input is driven to 7.0 V or less. The built-in 5 V regulator is a series regulator with temperature compensation. A ceramic capacitor with a value of 0.1 F or more must be connected between the CGND plane and the Reg5V Pin. The output of 5 V regulator is monitored by the internal Supervisor circuits. When the Supervisor detects this output is more than 4.2 V (typ.), the driver state becomes active (figure1.1). Figure 1.2 shows the application when the external 5 V regulator is used. When the Reg5V pin is applied into external 5 V, the Supervisor can activate the driver. In this application usage, VCIN should be connected to Reg5V. The signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit, the built-in 5 V regulator does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is terminated, and the 5 V regulator is not disabled. Voltages from –0.3 V to VCIN + 0.3 V can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. VCIN L H H H DISBL# L H Open REG5V 0 Active Active Active 12 V Driver State Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L) VCIN > 7.4 V VCIN VCIN 5V IN Reg5V UVL & 5 V Regulator To Internal Logic OUT OUT IN UVL & 5 V Regulator Reg5V External 5 V To Internal Logic Supervisor Figure 1.1 Typical 12 V Input Application (Activate Built-in 5 V Regulator) REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 12 of 16 Supervisor Figure 1.2 External 5 V Application R2J20605ANP Preliminary PWM & LSDBL# The PWM pin is the signal input pin for the driver chip. When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM L H GH L H GL H L The LSDBL# pin is the Low Side Gate Disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is low. Figure 2 shows the Typical high side and low side gate switching and Inductor current (IL) during "Continuous Conduction Mode (CCM)" and low side gate disabled when asserting LSDBL# signal. This pin is internally pulled up to Reg5V with 150 k resistor. When low side disable function is not used, keep this pin open or pulled up to VCIN. CCM Operation (LSDBL# = "H" or Open mode) IL GH GL Figure 2.1 Typical Signals during CCM DCM Operation (LSDBL# = "L") IL 0A GH GL Figure 2.2 Typical Signals during DCM REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 13 of 16 R2J20605ANP Preliminary The PWM input is TTL level and has hysteresis. When the PWM input signal is abnormal, e.g., when the signal route from the control IC is abnormal, the tri-state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 100 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 3.4 V or more is required to make the circuit return to normal operation. 100 ns (tHOLD-OFF) 100 ns (tHOLD-OFF) 3.4 V PWM 1.2 V GH GL 100 ns (tHOLD-OFF) 100 ns (tHOLD-OFF) 3.4 V PWM 1.2 V GH GL Figure 3 PWM Shutdown-Hold Time Signal REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 14 of 16 R2J20605ANP Preliminary The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal operation; after the PWM input signal has stayed in the hysteresis window for 100 ns (typ.) and the tri-state detection signal has been driven high, the transistor M1 is turned off. When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is asserted high signal, M1 becomes ON and shifts to normal operation. VCIN DISBL# M1 20 k PWM Pin Tri-state detection signal Input Logic To internal control 20 k Figure 4 Equivalent Circuit for the PWM-pin Input THWN This Thermal Warning feature is the indication of the high temperature status. THWN is an open drain logic output signal and need to connect a pull-up resistor (ex.51 k) to THWN for Systems with the thermal warning implementation. When the chip temperature of the internal driver IC becomes over 115°C, Thermal warning function operates. This signal is only indication for the system controller and does not disable DrMOS operation. When thermal warning function is not used, keep this pin open. "H" THWN output Logic Level "L" Thermal Warning Normal operating 100 115 TIC (°C) Figure 5 MOS FETs The MOS FETs incorporated in R2J20605ANP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 15 of 16 R2J20605ANP Preliminary Package Dimensions JEITA Package Code P-HVQFN56-8x8-0.50 RENESAS Code PVQN0056KA-A Previous Code — MASS[Typ.] 0.2g HD D 42 29 29 43 28 28 3.0 0.0 E HE e 43 42 0.3 1.0 C 4 0. Reference Symbol Lp 14 14 ZD A1 A c1 c 3.0 Index mark 56 y 1 b b1 0.0 0.4 1.0 1 15 3.0 15 ZE 56 3.0 Dimension in Millimeters Min Nom Max D 7.95 8.00 8.05 E 7.95 8.00 8.05 A2 A 0.95 A1 0.005 b 0.20 0.25 0.30 b1 0.23 e 0.50 Lp 0.40 0.50 0.60 x y 0.05 y1 t HD 8.10 8.20 8.30 HE 8.10 8.20 8.30 ZD 0.75 ZE 0.75 c 0.17 0.22 0.27 c1 0.20 Ordering Information Part Name R2J20605ANP#G3 Quantity 2500 pcs REJ03G1821-0300 Rev.3.00 Feb 26, 2010 Page 16 of 16 Shipping Container Taping Reel Notice 1. All information included in this document is current as of the date this document is issued. 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