RFMD RF3146PCBA

RF3146
Preliminary
0
QUAD-BAND GSM850/GSM900/DCS/PCS
POWER AMP MODULE
Typical Applications
• 3V Quad-Band GSM Handsets
• GSM850/EGSM900/DCS/PCS Products
• Commercial and Consumer Systems
• GPRS Class 12 Compatible
• Portable Battery-Powered Equipment
• Power StarTM Module
Product Description
-A-
The RF3146 is a high-power, high-efficiency power amplifier module with integrated power control. The device is a
self-contained 7mmx7mmx0.9mm lead frame module
(LFM) with 50Ω input and output terminals. The power
control function is also incorporated, eliminating the need
for directional couplers, detector diodes, power control
ASICs and other power control circuitry; this allows the
module to be driven directly from the DAC output. The
device is designed for use as the final RF amplifier in
GSM850, EGSM900, DCS and PCS handheld digital cellular equipment and other applications in the 824MHz to
849MHz, 880MHz to 915MHz, 1710MHz to 1785MHz
and 1850MHz to 1910MHz bands. On-board power control provides over 50dB of control range with an analog
voltage input; and, power down with a logic “low” for
standby operation.
Optimum Technology Matching® Applied
9
Si BJT
GaAs HBT
Si Bi-CMOS
SiGe HBT
InGaP/HBT
GaN HEMT
7.00 TYP
0.10 C A
2 PLCS
0.08 C
0.90
0.85
0.70
0.65
6.75 TYP
0.05
0.00
0.10 C B
2 PLCS
2 PLCS
0.10 C B
-B-
3.37 TYP
3.50 TYP
2 PLCS
0.10 C A
-C-
SEATING
PLANE
Dimensions in mm.
0.10M C A B
0.60
TYP
0.24
0.30
0.18
0.60
TYP
0.24
0.50
2.20
1.90
Shaded lead is pin 1.
0.30
0.50
TYP
0.30
5.25
4.95
Package Style: LFM, 48-Pin, 7mm x7mmx0.9mm
GaAs MESFET
9Si CMOS
SiGe Bi-CMOS
Features
• Integrated VREG
• Complete Power Control Solution
• +35dBm GSM Output Power at 3.5V
DCS/PCS IN 37
31 DCS/PCS OUT
• 60% GSM and 55% DCS/PCS EFF
BAND SELECT 40
TX ENABLE 41
VBATT 42
• +33dBm DCS/PCS Output Power at 3.5V
• 7mmx7mmx0.9mm Package Size
Fully Integrated
Power Control Circuit
VBATT 43
Ordering Information
VRAMP 45
RF3146
GSM IN 48
6 GSM OUT
RF3146 SB
RF3146 PCBA
Functional Block Diagram
Rev A7 040812 W3
Quad-Band GSM850/GSM900/DCS/PCS Power
Amp Module
Power Amp Module 5-Piece Sample Pack
Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
2-491
RF3146
Preliminary
Absolute Maximum Ratings
Parameter
Supply Voltage
Power Control Voltage (VRAMP)
Input RF Power
Max Duty Cycle
Output Load VSWR
Operating Case Temperature
Storage Temperature
Parameter
Rating
Unit
-0.3 to +6.0
-0.3 to +1.8
+10
50
10:1
-20 to +85
-55 to +150
VDC
V
dBm
%
°C
°C
Specification
Min.
Typ.
Max.
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Unit
Condition
Overall Power Control
VRAMP
Power Control “ON”
Power Control “OFF”
VRAMP Input Capacitance
VRAMP Input Current
Turn On/Off Time
TX Enable “ON”
TX Enable “OFF”
GSM Band Enable
DCS/PCS Band Enable
0.2
15
1.5
0.25
20
10
2
1.9
0.5
0.5
1.9
V
V
pF
µA
µs
V
V
V
V
Max. POUT, Voltage supplied to the input
Min. POUT, Voltage supplied to the input
DC to 2MHz
VRAMP =VRAMP MAX
VRAMP =0.2V to VRAMP MAX
V
V
µA
Specifications
Nominal operating limits
PIN <-30dBm, TX Enable=Low,
Temp=-20°C to +85°C
VRAMP =0.2V, TX Enable=High
Overall Power Supply
Power Supply Voltage
3.5
Power Supply Current
1
mA
Overall Control Signals
Band Select “Low”
Band Select “High”
Band Select “High” Current
TX Enable “Low”
TX Enable “High”
TX Enable “High” Current
2-492
0
1.9
0
1.9
0
2.0
20
0
2.0
1
0.5
3.0
50
0.5
3.0
2
V
V
µA
V
V
µA
Rev A7 040812 W3
RF3146
Preliminary
Parameter
Specification
Min.
Typ.
Max.
Unit
Temp=+25 °C, VBATT =3.5V,
VRAMP =VRAMP MAX, PIN =3dBm,
Freq=824MHz to 849MHz,
25% Duty Cycle, Pulse Width=1154µs
Overall (GSM850 Mode)
Operating Frequency Range
Maximum Output Power
Total Efficiency
Input Power Range
+34.2
824 to 849
MHz
dBm
+32.0
dBm
55
+3
+5
%
dBm
Output Noise Power
-88
-81
dBm
Forward Isolation 1
Forward Isolation 2
Cross Band Isolation at 2f0
Second Harmonic
Third Harmonic
All Other
Non-Harmonic Spurious
Input Impedance
Input VSWR
Output Load VSWR Stability
-50
-35
-35
-15
-18
-7
-15
-36
dBm
dBm
dBm
dBm
dBm
dBm
8:1
Output Load VSWR Ruggedness
10:1
Output Load Impedance
Condition
47
0
-15
-25
Ω
50
Ω
VRAMP =0.2V to VRAMP MAX
Spurious<-36dBm, RBW=3MHz
Set VRAMP where POUT <34.2dBm into 50Ω
load
Set VRAMP where POUT <34.2dBm into 50Ω
load. No damage or permanent degradation
to part.
Load impedance presented at RF OUT pad
dB
VRAMP =0.2V to VRAMP MAX
2.5:1
50
Temp = 25°C, VBATT =3.5V,
VRAMP =VRAMP MAX
Temp=+85 °C, VBATT =3.0V,
VRAMP =VRAMP MAX
At POUT MAX, VBATT =3.5V
Maximum output power guaranteed at minimum drive level
RBW=100kHz, 869MHz to 894MHz,
POUT > +5dBm
TXEnable=Low, PIN =+5dBm
TXEnable=High, PIN =+5dBm, VRAMP =0.2V
VRAMP =0.2V to VRAMP_RP
VRAMP =0.2V to VRAMP_RP
VRAMP =0.2V to VRAMP_RP
VRAMP =0.2V to VRAMP MAX
Power Control VRAMP
Power Control Range
55
Notes:
VRAMP MAX =0.4*VBATT +0.06<1.5V
VRAMP_RP =VRAMP set for 34.2dBm at nominal conditions.
Rev A7 040812 W3
2-493
RF3146
Parameter
Preliminary
Specification
Min.
Typ.
Max.
Unit
Temp=+25 °C, VBATT =3.5V,
VRAMP =VRAMP MAX, PIN =3dBm,
Freq=880MHz to 915MHz,
25% Duty Cycle, Pulse Width=1154µs
Overall (GSM900 Mode)
Operating Frequency Range
Maximum Output Power
Total Efficiency
Input Power Range
+34.2
880 to 915
MHz
dBm
+32.0
dBm
54
0
Output Noise Power
Forward Isolation 1
Forward Isolation 2
Cross Band Isolation 2f0
Second Harmonic
Third Harmonic
All Other
Non-Harmonic Spurious
Input Impedance
Input VSWR
Output Load VSWR Stability
8:1
Output Load VSWR Ruggedness
10:1
Output Load Impedance
Condition
58
+3
+5
%
dBm
-86
-80
dBm
-88
-84
dBm
-45
-30
-35
-15
-17
-10
-15
-36
dBm
dBm
dBm
dBm
dBm
dBm
-15
-25
Ω
50
Ω
VRAMP =0.2V to VRAMP MAX
Spurious<-36dBm, RBW=3MHz
Set VRAMP where POUT <34.2dBm into 50Ω
load
Set VRAMP where POUT <34.2dBm into 50Ω
load. No damage or permanent degradation
to part.
Load impedance presented at RF OUT pad
dB
VRAMP =0.2V to VRAMP MAX
2.5:1
50
Temp = 25°C, VBATT =3.5V,
VRAMP =VRAMP MAX
Temp=+85 °C, VBATT =3.0V,
VRAMP =VRAMP MAX
At POUT MAX, VBATT =3.5V
Maximum output power guaranteed at minimum drive level
RBW=100kHz, 925MHz to 935MHz,
POUT > +5dBm
RBW=100kHz, 935MHz to 960MHz,
POUT > +5dBm
TXEnable=Low, PIN =+5dBm
TXEnable=High, VRAMP =0.2V, PIN =+5dBm
VRAMP =0.2V to VRAMP_RP
VRAMP =0.2V to VRAMP_RP
VRAMP =0.2V to VRAMP_RP
VRAMP =0.2V to VRAMP MAX
Power Control VRAMP
Power Control Range
50
Notes:
VRAMP MAX =0.4*VBATT +0.06<1.5V
VRAMP_RP =VRAMP set for 34.2dBm at nominal conditions.
2-494
Rev A7 040812 W3
RF3146
Preliminary
Parameter
Specification
Min.
Typ.
Max.
Unit
Temp=25°C, VBATT =3.5V,
VRAMP =VRAMP MAX, PIN =3dBm,
Freq=1710MHz to 1785MHz,
25% Duty Cycle, pulse width=1154µs
Overall (DCS Mode)
Operating Frequency Range
Maximum Output Power
Total Efficiency
Input Power Range
+32.0
1710 to 1785
MHz
dBm
30
dBm
52
+3
+5
%
dBm
Output Noise Power
-85
-80
dBm
Forward Isolation 1
Forward Isolation 2
Second Harmonic
Third Harmonic
All Other
Non-Harmonic Spurious
Input Impedance
Input VSWR
Output Load VSWR Stability
-50
-25
-15
-20
-35
-15
-7
-15
-36
dBm
dBm
dBm
dBm
dBm
8:1
Output Load VSWR Ruggedness
10:1
Output Load Impedance
Condition
45
0
Ω
50
Ω
VRAMP =0.2V to VRAMP MAX
Spurious<-36dBm, RBW=3MHz
Set VRAMP where POUT <32.0dBm into 50Ω
load
Set VRAMP where POUT <32.0dBm into 50Ω
load. No damage or permanent degradation
to part.
Load impedance presented at RF OUT pin
dB
VRAMP =0.2V to VRAMP MAX, PIN =+5dBm
2.5:1
50
Temp=25°C, VBATT =3.5V,
VRAMP =VRAMP MAX
Temp=+85°C, VBATT =3.0V,
VRAMP =VRAMP MAX
At POUT MAX, VBATT =3.5V
Maximum output power guaranteed at minimum drive level
RBW=100kHz, 1805MHz to 1880MHz,
POUT > 0dBm, VBATT =3.5V
TXEnable=Low, PIN =+5dBm
TXEnable=High, VRAMP =0.2V, PIN =+5dBm
VRAMP =0.2V to VRAMP_RP
VRAMP =0.2V to VRAMP_RP
VRAMP =0.2V to VRAMP MAX
Power Control VRAMP
Power Control Range
50
Notes:
VRAMP MAX =0.4*VBATT +0.06<1.5V
VRAMP_RP =VRAMP set for 32.0dBm at nominal conditions.
Rev A7 040812 W3
2-495
RF3146
Parameter
Preliminary
Specification
Min.
Typ.
Max.
Unit
Temp=25°C, VBATT =3.5V,
VRAMP =VRAMP MAX, PIN =3dBm,
Freq=1850MHz to 1910MHz,
25% Duty Cycle, pulse width=1154µs
Overall (PCS Mode)
Operating Frequency Range
Maximum Output Power
Total Efficiency
Input Power Range
+32.0
1850 to 1910
MHz
dBm
30
dBm
55
+3
+5
%
dBm
Output Noise Power
-85
-80
dBm
Forward Isolation 1
Forward Isolation 2
Second Harmonic
Third Harmonic
All Other
Non-Harmonic Spurious
Input Impedance
Input VSWR
Output Load VSWR Stability
-40
-20
-15
-20
-33
-15
-7
-15
-36
dBm
dBm
dBm
dBm
dBm
8:1
Output Load VSWR Ruggedness
10:1
Output Load Impedance
Condition
48
0
Ω
50
Ω
VRAMP =0.2V to VRAMP MAX
Spurious<-36dBm, RBW=3MHz
Set VRAMP where POUT <32.0dBm into 50Ω
load
Set VRAMP where POUT <32.0dBm into 50Ω
load. No damage or permanent degradation
to part.
Load impedance presented at RF OUT pin
dB
VRAMP =0.2V to VRAMP MAX, PIN =+5dBm
2.5:1
50
Temp=25°C, VBATT =3.5V,
VRAMP =VRAMP MAX, 1850MHz to 1910MHz
Temp=+85°C, VBATT =3.0V,
VRAMP =VRAMP MAX
At POUT MAX, VBATT =3.5V
Full output power guaranteed at minimum
drive level
RBW=100kHz, 1930MHz to 1990MHz,
POUT > 0dBm, VBATT =3.5V
TX_ENABLE=Low, PIN =+5dBm
TXEnable=High, VRAMP =0.2V, PIN =+5dBm
VRAMP =0.2V to VRAMP_RP
VRAMP =0.2V to VRAMP_RP
VRAMP =0.2V to VRAMP MAX
Power Control VRAMP
Power Control Range
50
Notes:
VRAMP MAX =0.4*VBATT +0.06<1.5V
VRAMP_RP =VRAMP set for 32.0dBm at nominal conditions.
2-496
Rev A7 040812 W3
RF3146
Preliminary
Pin
1
2
3
4
5
6
Function Description
Interface Schematic
Internal circuit node. Do not externally connect.
NC
VCC2 GSM Controlled voltage input to the GSM driver stage. This voltage is part of
VCC2
the power control function for the module. This node must be connected to VCC OUT. This pin should be externally decoupled.
NC
GND
GND
GSM850/
GSM900
OUT
7
8
9
10
11
12
13
14
15
16
17
18
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC3 GSM
19
VCC OUT
20
VCC OUT
21
VCC3
DCS/PCS
22
23
24
25
26
27
28
29
30
NC
NC
NC
NC
NC
NC
NC
NC
GND
Rev A7 040812 W3
Internal circuit node. Do not externally connect.
Internally connected to the package base.
Internally connected to the package base.
RF output for the GSM bands. This is a 50Ω output. The output matching circuit and DC-block are internal to the package.
VCC3
Output
Match
RF OUT
Internally connected to the package base.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
No internal or external connection.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Controlled voltage input to the GSM output stage. This voltage is part of
the power control function for the module. This node must be connected to VCC OUT. This pin should be externally decoupled.
Controlled voltage output to feed VCC2 and VCC3. This voltage is part
of the power control function for the module. It cannot be connected to
any pins other than VCC2 and VCC3.
Controlled voltage output to feed VCC2 and VCC3. This voltage is part
of the power control function for the module. It cannot be connected to
any pins other than VCC2 and VCC3.
Controlled voltage input to the DCS/PCS output stage. This voltage is
part of the power control function for the module. This node must be
connected to VCC OUT. This pin should be externally decoupled.
Internal circuit node. Do not externally connect.
VCC3
See pin 18.
Internal circuit node. Do not externally connect.
No internal or external connection.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internal circuit node. Do not externally connect.
Internally connected to the package base.
2-497
RF3146
Pin
31
32
33
34
35
Function
DCS/PCS
OUT
GND
NC
GND
VCC2
DCS/PCS
36
NC
37
DCS/PCS IN
Preliminary
Description
Interface Schematic
RF output for the DCS/PCS bands. This is a 50Ω output. The output
matching circuit and DC-block are internal to the package.
See pin 6.
Internally connected to the package base.
Internal circuit node. Do not externally connect.
Internally connected to the package base.
Controlled voltage input to the DCS/PCS driver stage. This voltage is
part of the power control function for the module. This node must be
connected to VCC OUT. This pin should be externally decoupled.
No internal connection. Connect to ground plane close to the package
pin.
RF input to the DCS/PCS band. This is a 50Ω output.
See pin 2.
VCC1
RF IN
38
NC
39
VCC1
DCS/PCS
40
BAND SEL
No internal connection. Connect to ground plane close to the package
pin.
Controlled voltage on the GSM and DCS/PCS preamplifier stages. This
voltage is applied internal to the package. This pin should be externally
decoupled.
Allows external control to select the GSM or DCS/PCS bands with a
logic high or low. A logic low enables the GSM bands, whereas a logic
high enables the DCS/PCS bands.
VCC1
BAND SEL
GSM CTRL
TX EN
DCS CTRL
41
TX ENABLE
This signal enables the PA module for operation with a logic high. Both
bands are disabled with a logic low.
VBATT
TX EN
42
VBATT
43
VBATT
44
45
NC
VRAMP
Power supply for the module. This pin should be externally decoupled
and connected to the battery.
Power supply for the module. This pin should be externally decoupled
and connected to the battery.
Internal circuit node. Do not externally connect.
Ramping signal from DAC. A simple RC filter may be required depending on the selected baseband.
VRAMP
46
VCC1 GSM
47
GND1 GSM
48
GSM850/
GSM900 IN
GND
Pkg
Base
2-498
TX ON
Internally connected to VCC1 (pin 39). No external connection
required.
Ground connection for the GSM preamplifier stage. Connect to ground
plane close to the package pin.
RF input to the GSM band. This is a 50Ω input.
+
See pin 39.
See pin 37.
Connect to ground plane with multiple via holes. See recommended
footprint.
Rev A7 040812 W3
RF3146
Preliminary
GSM850/
GSM900 IN
GND1 GSM
vcc1 GSM
VRAMP
NC
VBATT
VBATT
TX ENABLE
BAND SEL
VCC1
DCS/PCS
NC
DCS/PCS IN
Pin Out
48
47
46
45
44
43
42
41
40
39
38
37
36 NC
NC 1
VCC2 GSM 2
35
34 GND
NC 3
GND 4
33 NC
GND 5
32 GND
GSM850/
6
GSM900 OUT
31 DCS/PCS OUT
30 GND
GND 7
Rev A7 040812 W3
VCC2
DCS/PCS
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
25 NC
VCC3
DCS/PCS
NC 12
VCC OUT
26 NC
VCC OUT
NC 11
VCC3 GSM
27 NC
NC
NC 10
NC
28 NC
NC
NC 9
NC
29 NC
NC
NC 8
2-499
RF3146
Preliminary
Application Schematic
TX EN
BAND SEL
VBATT
VRAMP
VCC1
4.7 µF
15 kΩ
VCC1: Internally supplied.
See Pin Function note.
1 nF
GSM850/
GSM900 IN
DCS/PCS IN
48
1
1 nF
47
46
45
44
43
42
41
40
39
38
37
36
From
VCC1
VCC
2
35
3
34
4
33
Fully Integrated
Power Control Circuit
5
GSM850/
GSM900 OUT
1 nF
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13
14
15
16
17
18
19
20
21
22
23
DCS/PCS OUT
24
10 nF
100 pF
2-500
Rev A7 040812 W3
RF3146
Preliminary
Evaluation Board Schematic
TX EN
BAND SEL
R2
100 kΩ
R3
100 kΩ
VRAMP
R4
100 kΩ
50 Ω µstrip
GSM850/
GSM900 IN
48
1
C9
1 nF
GSM850/
GSM900 OUT
47
46
R1
15 kΩ
45
VBATT
VCC1
C2
4.7 µF
44
VCC1: Internally supplied.
See Pin Function note.
C6
1 nF
43
42
41
40
39
38
50 Ω µstrip
DCS/PCS IN
37
36
From
VCC1
VCC
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
50 Ω µstrip
C8
1 nF
50 Ω µstrip
12
DCS/PCS OUT
25
13
14
15
16
17
18
19
C13
100 pF
Rev A7 040812 W3
C4
DNP
20
21
22
23
24
C10
10 nF
2-501
RF3146
Preliminary
Evaluation Board Layout
Board Size 2.0” x 2.0”
Board Thickness 0.032”, Board Material FR-4, Multi-Layer
2-502
Rev A7 040812 W3
RF3146
Preliminary
Theory of Operation
Overview
The RF3146 is a quad-band GSM850, EGSM900, DCS1800, and PCS1900 power amplifier module that incorporates an
indirect closed loop method of power control. This simplifies the phone design by eliminating the need for the complicated control loop design. The indirect closed loop appears as an open loop to the user and can be driven directly from
the DAC output in the baseband circuit.
Theory of Operation
The indirect closed loop is essentially a closed loop method of power control that is invisible to the user. Most power control systems in GSM sense either forward power or collector/drain current. The RF3146 does not use a power detector. A
high-speed control loop is incorporated to regulate the collector voltage of the amplifier while the stage are held at a constant bias. The VRAMP signal is multiplied by a factor of 2.65 and the collector voltage for the second and third stages are
regulated to the multiplied VRAMP voltage. The basic circuit is shown in the following diagram.
VBATT
TX ENABLE
VRAMP
H(s)
RF IN
RF OUT
TX ENABLE
By regulating the power, the stages are held in saturation across all power levels. As the required output power is
decreased from full power down to 0dBm, the collector voltage is also decreased. This regulation of output power is
demonstrated in Equation 1 where the relationship between collector voltage and output power is shown. Although load
impedance affects output power, supply fluctuations are the dominate mode of power variations. With the RF3146 regulating collector voltage, the dominant mode of power fluctuations is eliminated.
2
P dBm
( 2 ⋅ V CC – V SAT )
= 10 ⋅ log ------------------------------------------–3
8 ⋅ R LOAD ⋅ 10
(Eq. 1)
There are several key factors to consider in the implementation of a transmitter solution for a mobile phone. Some of
them are:
•
•
•
•
•
•
•
•
•
•
Current draw and system efficiency
Power variation due to Supply Voltage
Power variation due to frequency
Power variation due to temperature
Input impedance variation
Noise power
Loop stability
Loop bandwidth variations across power levels
Burst timing and transient spectrum trade offs
Harmonics
Rev A7 040812 W3
2-503
RF3146
Preliminary
Output power does not vary due to supply voltage under normal operating conditions if VRAMP is sufficiently lower than
VBATT. By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers most
cases where the PA will be operated. However, as the battery discharges and approaches its lower power range the
maximum output power from the PA will also drop slightly. In this case it is important to also decrease VRAMP to prevent
the power control from inducing switching transients. These transients occur as a result of the control loop slowing down
and not regulating power in accordance with VRAMP.
The switching transients due to low battery conditions are regulated by incorporating the following relationship limiting
the maximum VRAMP voltage (Equation 2). Although no compensation is required for typical battery conditions, the battery compensation required for extreme conditions is covered by the relationship in Equation 4. This should be added to
the terminal software.
V RAMPMAX = 0.4 ⋅ V BATT + 0.06 ≤ 1.5V
(Eq. 2)
Due to reactive output matches, there are output power variations across frequency. There are a number of components
that can make the effects greater or less. Power variation straight out of the RF3146 is shown in the tables below.
The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, there
is some length of microstrip that follows the power amplifier. There is also a frequency response found in directional couplers due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since the
RF3146 does not use a directional coupler with a diode detector, these variations do not occur.
Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where CBE and
CCB (CGS and CSG for a FET) vary over the bias voltage. The same principle used to make varactors is present in the
power amplifiers. The junction capacitance is a function of the bias across the junction. This produces input impedance
variations as the Vapc voltage is swept. Although this could present a problem with frequency pulling the transmit VCO
off frequency, most synthesizer designers use very wide loop bandwidths to quickly compensate for frequency variations
due to the load variations presented to the VCO.
The RF3146 presents a very constant load to the VCO. This is because all stages of the RF3146 are run at constant
bias. As a result, there is constant reactance at the base emitter and base collector junction of the input stage to the
power amplifier.
Noise power in PA's where output power is controlled by changing the bias voltage is often a problem when backing off of
output power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 5),
F2 – 1 F3 – 1
F TOT = F1 + ---------------- + ------------------G1 ⋅ G2
G1
(Eq. 3)
the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF3146 is kept constant
the gain in the first stage is always high and the overall noise power is not increased when decreasing output power.
Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loop
involves trade-offs affecting stability, transient spectrum and burst timing.
In conventional architectures the PA gain (dB/ V) varies across different power levels, and as a result the loop bandwidth
also varies. With some power amplifiers it is possible for the PA gain (control slope) to change from 100dB/V to as high
as 1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at low
slope regions which often causes instability at high slope regions.
The RF3146 loop bandwidth is determined by internal bandwidth and the RF output load and does not change with
respect to power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltage
and collector voltage do not vary.
2-504
Rev A7 040812 W3
RF3146
Preliminary
An often overlooked problem in PA control loops is that a delay not only decreases loop stability it also affects the burst
timing when, for instance the input power from the VCO decreases (or increases) with respect to temperature or supply
voltage. The burst timing then appears to shift to the right especially at low power levels. The RF3146 is insensitive to a
change in input power and the burst timing is constant and requires no software compensation.
Switching transients occur when the up and down ramp of the burst is not smooth enough or suddenly changes shape. If
the control slope of a PA has an inflection point within the output power range or if the slope is simply too steep it is difficult to prevent switching transients. Controlling the output power by changing the collector voltage is as earlier described
based on the physical relationship between voltage swing and output power. Furthermore all stages are kept constantly
biased so inflection points are nonexistent.
Harmonics are natural products of high efficiency power amplifier design. An ideal class “E” saturated power amplifier
will produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content.
Although this is common to all power amplifiers, there are other factors that contribute to conducted harmonic content as
well. With most power control methods a peak power diode detector is used to rectify and sense forward power. Through
the rectification process there is additional squaring of the waveform resulting in higher harmonics. The RF3146 address
this by eliminating the need for the detector diode. Therefore the harmonics coming out of the PA should represent the
maximum power of the harmonics throughout the transmit chain. This is based upon proper harmonic termination of the
transmit port. The receive port termination on the T/R switch as well as the harmonic impedance from the switch itself
will have an impact on harmonics. Should a problem arise, these terminations should be explored.
The RF3146 incorporates many circuits that had previously been required external to the power amplifier. The shaded
area of the diagram below illustrates those components and the following table itemizes a comparison between the
RF3146 Bill of Materials and a conventional solution.
Component
Power Control ASIC
Directional Coupler
Buffer
Attenuator
Various Passives
Mounting Yield
(other than PA)
Total
Conventional
Solution
$0.80
$0.20
$0.05
$0.05
$0.05
$0.12
RF3146
$1.27
$0.00
N/A
N/A
N/A
N/A
N/A
N/A
1
14
2
13
3
12
4
11
5
10
6
9
7
8
From DAC
*Shaded area eliminated with Indirect Closed Loop using RF3146
Rev A7 040812 W3
2-505
RF3146
Preliminary
PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. Typical thickness is
3µinch to 8µinch gold over 180µinch nickel.
PCB Land Pattern Recommendation
PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and
tested for optimized assembly at RFMD; however, it may require some modifications to address company specific
assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.
PCB Metal Land Pattern
A = 0.64 x 0.28 (mm) Typ.
B = 0.28 x 0.64 (mm) Typ.
C = 5.65 (mm) Sq.
5.50 Typ.
Dimensions in mm.
0.50 Typ.
Pin 48
B B B B B B B B B B B B
Pin 1
0.50 Typ.
A
A
A
A
A
A
A
A
A
A
A
C
A
0.55 Typ.
Pin 36
A
A
A
A
A
A
A
A
A
A
2.75
5.50 Typ.
A
A
B B B B B B B B B B B B
Pin 24
0.55 Typ.
2.75
Figure 1. PCB Metal Land Pattern (Top View)
2-506
Rev A7 040812 W3
RF3146
Preliminary
PCB Solder Mask Pattern
Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the
PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all
pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask
clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.74 x 0.38 (mm) Typ.
B = 0.38 x 0.74 (mm) Typ.
C = 5.25 x 2.20 (mm)
5.50 Typ.
Dimensions in mm.
0.50 Typ.
Pin 48
B B B B B B B B B B B B
Pin 1
0.50 Typ.
0.55 Typ.
A
A
A
A
A
A
A
A
A
A
A
A
C
Pin 36
A
A
A
A
A
A
A
A
A
A
A
A
1.95
5.50 Typ.
B B B B B B B B B B B B
Pin 24
0.55 Typ.
2.75
Figure 2. PCB Solder Mask Pattern (Top View)
Thermal Pad and Via Design
Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been
designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating
routing strategies.
The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size
on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested
that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
Rev A7 040812 W3
2-507
RF3146
2-508
Preliminary
Rev A7 040812 W3