TOSHIBA TC55VCM208ASTN55

TC55VCM208ASTN40,55
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55VCM208ASTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by
8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to
3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7 µA standby
current (at VDD = 3 V, Ta = 25°C, typical) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There
are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output
enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of −40° to 85°C, the TC55VCM208ASTN can be used in environments exhibiting extreme
temperature conditions. The TC55VCM208ASTN is available in a plastic 40-pin thin-small outline package
(TSOP).
FEATURES
•
•
•
•
•
•
•
•
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using CE1 and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of −40° to 85°C
Standby Current (maximum):
3.6 V
10 µA
3.0 V
5 µA
Access Times:
TC55VCM208ASTN
•
40
55
Access Time
40 ns
55 ns
CE1 Access Time
40 ns
55 ns
CE2
Access Time
40 ns
55 ns
OE
Access Time
25 ns
30 ns
Package:
TSOPⅠ40-P-1014-0.50
PIN ASSIGNMENT (TOP VIEW)
(Weight:0.30 g typ)
PIN NAMES
40 PIN TSOP
A0~A18
1
40
CE1 , CE2
Read/Write Control
OE
Output Enable
I/O1~I/O16
21
VDD
(Normal)
Chip Enable
R/W
LB , UB
20
Address Inputs
Data Byte Control
Data Inputs/Outputs
Power
GND
Ground
NC
No Connection
OP*
Option
*: OP pin must be open or connected to GND.
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
A16
A15
A14
A13
A12
A11
A9
A8
R/W
CE2
OP
NC
A18
A7
A6
A5
A4
A3
A2
A1
Pin No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
A0
CE1
GND
OE
I/O1
I/O2
I/O3
I/O4
NC
VDD
VDD
I/O5
I/O6
I/O7
I/O8
A10
NC
NC
GND
A17
2003-08-11
1/12
TC55VCM208ASTN40,55
BLOCK DIAGRAM
CE
MEMORY CELL ARRAY
2,048 × 256 × 8
(4,194,304)
SENSE AMP
COLUMN ADDRESS
DECODER
CLOCK
GENERATOR
DATA
CONTROL
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
GND
ROW ADDRESS
DECODER
ROW ADDRESS
REGISTER
VDD
ROW ADDRESS
BUFFER
A6
A7
A8
A9
A11
A12
A13
A14
A15
A16
A18
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
CE
A0 A1 A2 A3 A4 A5 A10 A17
OE
R/W
CE1
CE2
CE
OPERATING MODE
MODE
CE1
CE2
OE
R/W
Read
L
H
L
H
Output
IDDO
Write
L
H
*
L
Input
IDDO
Output Deselect
L
H
H
H
High-Z
IDDO
H
*
*
*
High-Z
IDDS
*
L
*
*
High-Z
IDDS
Standby
I/O1~I/O8
POWER
* = don't care
H = logic high
L = logic low
MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
VDD
Power Supply Voltage
−0.3~4.2
V
VIN
Input Voltage
−0.3*~4.2
V
VI/O
Input/Output Voltage
−0.5~VDD + 0.5
V
PD
Power Dissipation
0.6
W
Tsolder
Soldering Temperature (10s)
260
°C
Tstg
Storage Temperature
−55~150
°C
Topr
Operating Temperature
−40~85
°C
*: −2.0 V when measured at a pulse width of 20ns
2003-08-11
2/12
TC55VCM208ASTN40,55
DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
VDD
Power Supply Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
VDH
Data Retention Supply Voltage
MIN
TYP
MAX
UNIT
2.3

3.6
V

VDD + 0.3
V
−0.3*

VDD × 0.24
V
1.5

3.6
V
VDD = 2.3 V~2.7 V
2.0
VDD = 2.7 V~3.6 V
2.2
*: −2.0 V when measured at a pulse width of 20ns
DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V)
SYMBOL
PARAMETER
TEST CONDITION
IIL
Input Leakage
Current
IOH
Output High Current VOH = VDD − 0.5 V
VIN = 0 V~VDD
MIN
TYP
MAX UNIT


±1.0
µA
−0.5


mA
IOL
Output Low Current
VOL = 0.4 V
2.1


mA
ILO
Output Leakage
Current
CE1 = VIH or CE2 = VIL or R/W = VIL or OE = VIH,
VOUT = 0 V~VDD


±1.0
µA
MIN


35
1 µs


8
MIN


30
CE1 = VIL and CE2 = VIH and
R/W = VIH, IOUT = 0 mA,
Other Input = VIH/VIL
IDDO1
Operating Current
IDDO2
mA
CE1 = 0.2 V and
CE2 = VDD − 0.2 V and
R/W = VDD − 0.2 V,
IOUT = 0 mA,
Other Input = VDD − 0.2 V/0.2 V
tcycle
mA


3


1


10

0.7

VDD =3.0 V Ta = −40~40°C


2
Ta = −40~85°C


5
1 µs
CE1 = VIH or CE2 = VIL
IDDS1
VDD =
Ta = −40~85°C
3.3V± 0.3 V
Standby Current
IDDS2
CE1 = VDD − 0.2 V or
CE2 = 0.2 V
Ta = 25°C
mA
µA
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
TEST CONDITION
MAX
UNIT
CIN
Input Capacitance
VIN = GND
10
pF
COUT
Output Capacitance
VOUT = GND
10
pF
Note:
This parameter is periodically sampled and is not 100% tested.
2003-08-11
3/12
TC55VCM208ASTN40,55
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = −40° to 85°C, VDD = 2.7 to 3.6 V)
READ CYCLE
TC55VCM208ASTN
SYMBOL
PARAMETER
40
UNIT
55
MIN
MAX
MIN
MAX
tRC
Read Cycle Time
40

55

tACC
Address Access Time

40

55
tCO1
Chip Enable( CE1 ) Access Time

40

55
tCO2
Chip Enable(CE2) Access Time

40

55
tOE
Output Enable Access Time

25

30
tCOE
Chip Enable Low to Output Active
5

5

tOEE
Output Enable Low to Output Active
0

0

tOD
Chip Enable High to Output High-Z

20

25
tODO
Output Enable High to Output High-Z

20

25
tOH
Output Data Hold Time
10

10

ns
WRITE CYCLE
TC55VCM208ASTN
SYMBOL
PARAMETER
40
UNIT
55
MIN
MAX
MIN
MAX
tWC
Write Cycle Time
40

55

tWP
Write Pulse Width
30

40

tCW
Chip Enable to End of Write
35

45

tAS
Address Setup Time
0

0

tWR
Write Recovery Time
0

0

tODW
R/W Low to Output High-Z

20

25
tOEW
R/W High to Output Active
0

0

tDS
Data Setup Time
20

25

tDH
Data Hold Time
0

0

Note:
ns
tOD, tODO and tODW are specified in time when an output becomes high impedance, and are not judged depending on an
output voltage level.
2003-08-11
4/12
TC55VCM208ASTN40,55
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = −40° to 85°C, VDD = 2.3 to 3.6 V)
READ CYCLE
TC55VCM208ASTN
SYMBOL
PARAMETER
40
UNIT
55
MIN
MAX
MIN
MAX
tRC
Read Cycle Time
55

70

tACC
Address Access Time

55

70
tCO1
Chip Enable( CE1 ) Access Time

55

70
tCO2
Chip Enable(CE2) Access Time

55

70
tOE
Output Enable Access Time

30

35
tCOE
Chip Enable Low to Output Active
5

5

tOEE
Output Enable Low to Output Active
0

0

tOD
Chip Enable High to Output High-Z

25

30
tODO
Output Enable High to Output High-Z

25

30
tOH
Output Data Hold Time
10

10

ns
WRITE CYCLE
TC55VCM208ASTN
SYMBOL
PARAMETER
40
UNIT
55
MIN
MAX
MIN
MAX
tWC
Write Cycle Time
55

70

tWP
Write Pulse Width
40

50

tCW
Chip Enable to End of Write
45

55

tAS
Address Setup Time
0

0

tWR
Write Recovery Time
0

0

tODW
R/W Low to Output High-Z

25

30
tOEW
R/W High to Output Active
0

0

tDS
Data Setup Time
25

30

tDH
Data Hold Time
0

0

Note:
ns
tOD, tODO and tODW are specified in time when an output becomes high impedance, and are not judged depending on an
output voltage level.
2003-08-11
5/12
TC55VCM208ASTN40,55
AC TEST CONDITIONS
PARAMETER
TEST CONDITION
0.2 V, VDD × 0.7 V + 0.2 V
Input pulse level
tR, tF
1V / ns(Fig.1)
Timing measurements
VDD × 0.5
Reference level
VDD × 0.5
30 pF + 1 TTL Gate(Fig.2)
Output load
Fig.1 : Input rise and fall time
Fig.2 : Output load
VTM
VDD Typ
GND
90%
10%
90%
10%
1 V/ns
R1
Dout
1 V/ns
tR
tF
R2
30 pF
R1 = 810 Ω
R2 = 1610 Ω
VTM = 2.3 V
2003-08-11
6/12
TC55VCM208ASTN40,55
TIMING DIAGRAMS
READ CYCLE
(See Note 1)
tRC
Address
A0~A18
tACC
tOH
tCO1
CE1
tCO2
CE2
tOE
tOD
OE
tOEE
DOUT
I/O1~8
tODO
Hi-Z
VALID DATA OUT
Hi-Z
tCOE
INDETERMINATE
WRITE CYCLE 1 (R/W CONTROLLED)
(See Note 4)
tWC
Address
A0~A18
tAS
tWP
tWR
R/W
tCW
CE1
tCW
CE2
tOEW
tODW
DOUT
I/O1~8
(See Note 2)
Hi-Z
tDS
DIN
I/O1~8
(See Note 5)
(See Note 3)
tDH
VALID DATA IN
(See Note 5)
2003-08-11
7/12
TC55VCM208ASTN40,55
WRITE CYCLE 2 ( CE1 CONTROLLED)
(See Note 4)
tWC
Address
A0~A18
tAS
tWP
tWR
R/W
tCW
CE1
tCW
CE2
tCOE
DOUT
I/O1~8
tODW
Hi-Z
Hi-Z
tDS
DIN
I/O1~8
(See Note 5)
WRITE CYCLE 3 (CE2 CONTROLLED)
tDH
VALID DATA IN
(See Note 4)
tWC
Address
A0~A18
tAS
tWP
tWR
R/W
tCW
CE1
tCW
CE2
tCOE
DOUT
I/O1~8
tODW
Hi-Z
Hi-Z
tDS
DIN
I/O1~8
(See Note 5)
tDH
VALID DATA IN
2003-08-11
8/12
TC55VCM208ASTN40,55
Note:
(1)
R/W remains HIGH for the read cycle.
(2)
If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain
at high impedance.
(3)
If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will
remain at high impedance.
(4)
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
(5)
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
VDH
MIN
TYP
MAX
UNIT
1.5

3.6
V
VDH = 3.6 V Ta = −40~85°C


10
Ta = −40~40°C


2
Ta = −40~85°C


5
Data Retention Supply Voltage
IDDS2
Standby Current
VDH = 3.0 V
µA
tCDR
Chip Deselect to Data Retention Mode Time
0


ns
tR
Recovery Time
5


ms
CE1 CONTROLLED DATA RETENTION MODE
VDD
VDD
(See Note 1)
DATA RETENTION MODE
2.3 V
(See Note 2)
(See Note 2)
VIH
tCDR
VDD − 0.2 V
CE1
tR
GND
CE2 CONTROLLED DATA RETENTION MODE
VDD
VDD
(See Note 3)
DATA RETENTION MODE
2.3 V
CE2
VIH
VIL
tCDR
tR
0.2 V
GND
2003-08-11
9/12
TC55VCM208ASTN40,55
Note:
(1)
In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V or
CE2 ≥ VDD − 0.2 V.
(2)
When CE1 is operating at the VIH(min.) level, the operating current is given by IDDS1 during the
transition of VDD from 2.3(2.7) to 2.2V(2.4 V).
(3)
In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V.
2003-08-11
10/12
TC55VCM208ASTN40,55
PACKAGE DIMENSIONS
Weight:0.30 g (typ)
2003-08-11
11/12
TC55VCM208ASTN40,55
RESTRICTIONS ON PRODUCT USE
030619EBA
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
2003-08-11
12/12