DIODES ZABG4002JA16TC

A Product Line of
Diodes Incorporated
ZABG4002
LOW POWER 4 STAGE FET LNA BIAS CONTROLLER
Summary
The ZABG4002 is a four stage depletion mode FET bias controller intended primarily for satellite Low Noise Block’s (LNB’s), but
its also suitable for other LNA applications such as those in found in PMR’s and microwave links. The ZABG4002 provides each
FET with an independent protected negative gate voltage and positive drain voltage with user programmable drain current.
Combining an advanced IC process and packaging techniques, the ZABG4002 helps minimise power consumption, component
cost and PCB area whilst enhancing overall reliability.
•
FET drain current selectable from 0 to 15mA
•
Switchable FETs for power management
•
Allows first and second stage FETs to be run at different
(optimum) drain currents
•
FET drain voltages and currents held stable over
temperature and Vcc variations
•
FETs protected against overstress during power-up and
power-down.
•
Internal negative supply generator allowing single supply
operation (available for external use)
•
Low external component count
VCC
D3
FET drain voltages set at 2.0V
D2
G3
G2
D4
VCC
G4
GND
RCAL1
RCAL2
•
D1
Low quiescent supply current, 1.2mA typical
CSUB
Operating range of 3.0V to 8.0V
•
CNB1
•
CNB2
Four stage FET bias controller
G1
Pin Assignments
•
Top View
CSUB
Bottom View
Applications
•
Twin LNB’s
•
Quad LNB’s
•
US LNB’s
•
Microwave links
•
PMR and Cellular telephone systems
Vertical
Single Universal LNB System Diagram
Horizontal
NEW PRODUCT
Features
Gain stages
GaAs FET’s
ZABG
4002
6002
ZABG4002
Document number: DS32047 Rev. 2 - 2
Down
Converter
IF Switching, gain
and control
ZXHF
5002
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A Product Line of
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ZABG4002
Device Description
NEW PRODUCT
The ZABG series of devices are designed to meet the bias
requirements of GaAs and HEMT FETs commonly used in
satellite receiver LNBs with a minimum of external
components whilst operating from a minimal voltage supply
and using minimal current.
The ZABG4002 provides four FET bias stages, arranged in
two pairs of two. Resistors connected to pins Rcal1 and
Rcal2 set the FET drain currents of each pair over the range
of 0 to 15mA, allowing input FETs to be biased for optimum
noise and amplifier FETs for optimum gain.
Drain voltages of all stages are set at 2.0V. The drain
supplies are current limited to approximately 5% above the
operating currents set by the Rcal resistors.
As an additional feature the Rcal pins can also be used as
logic inputs to disable pairs of FETs as part of a power
management scheme or simply an alternative to LNA
switching. Driven to a logic high (>3.0V), the inputs disable
their associated FET bias stages by switching gate feeds to 2.5V and drain feeds open circuit.
Depletion mode FETs require a negative voltage bias supply
when operated in grounded source circuits. The ZABG4002
includes an integrated low noise switched capacitor DC-DC
converter generating a regulated output of -2.5V to allow
single supply operation.
ZABG4002
Document number: DS32047 Rev. 2 - 2
To facilitate the design of efficient low voltage 3.3V LNB
systems and to maintain compatibility with higher voltage
legacy designs, the ZABG4002 is capable of operating within
the supply of 3.0V to 8V.
These devices are unconditionally stable over the full working
temperature with the FETs in place, subject to the inclusion of
the recommended gate and drain capacitors. These ensure
RF stability and minimal injected noise.
It is possible to use less than the devices full complement of
FET bias controls, unused drain and gate connections can be
left open circuit without affecting operation of the remaining
bias circuits.
To protect the external FETs the circuits have been designed
to ensure that, under any conditions including power up/down
transients, the gate drive from the bias circuits cannot exceed
-3V. Additionally each stage has its own individual current
limiter. Furthermore if the negative rail experiences a fault
condition, such as overload or short circuit, the drain supply to
the FETs will shut down avoiding excessive current flow.
To minimise PCB space ZABG4002 is packaged in the 16 pin
3mm x 3mm QFN package.
Device operating temperature is -40°C to 85°C to suit a wide
range of environmental conditions.
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ZABG4002
Maximum Ratings
NEW PRODUCT
Parameter
Supply Voltage
Supply Current
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Electrical Characteristics
Parameter
Operating Voltage Range
(note 1)
Supply Current
Substrate Voltage
Rating
-0.6 to +10
80
500
-40 to +85
-40 to +150
Unit
V
mA
mW
°C
°C
(Measured at TAMB = 25°C, VCC = 3.3V (note 1), RCAL1 = RCAL2 = 39k (setting ID to 10mA) unless otherwise stated)
Conditions
ID1 = ID2 = ID3 = ID4 = 0
ID1 = ID2 = ID3 = ID4 = 10mA
ICSUB = 0
ICSUB = -200uA
Voltage Disabled
Drain Characteristics
Drain (D1 to D4)
Current Range
Current Operating
Current Disabled
Voltage Operating
delta ID vs VCC
delta ID vs TOP
delta VD vs VCC
delta VD vs TOP
RCAL(1 and 2)
Disable Threshold
Input Current
Min.
VCC
3.0
Typ.
Max.
Unit
8.0
V
4.0
44
-2.0
-2.0
600
mA
mA
V
V
kHz
ICC
ICC(L)
VCSUB
VCSUB(L)
FOSC
-3.0
150
1.2
42
-2.65
-2.55
240
IG
VG(L)
VG(H)
-100
-3.0
0
-2.5
0.7
+500
-2.0
1.0
uA
V
V
VG(DIS)
-3.0
-2.5
-2.0
V
Standard Application Circuit
VD = 0, VRCAL = 3.0V
ID = 10mA
VCC = 3.3 to 8.0V
TOP = -40°C to +85°C
VCC = 3.3 to 8.0V
TOP = -40°C to +85°C
ID
ID(OP)
ID(DIS)
VD(OP)
dID/dVCC
dID/dTOP
dVD/dVCC
dVD/dTOP
0
8
10
15
12
10
2.2
mA
mA
uA
V
%/V
%/°C
%/V
ppm/°C
VRCAL = 3.0V
VRCAL(DIS)
IRCAL(DIS)
3.0
10
V
uA
VD(NOISE)
0.02
Vpk-pk
VG(NOISE)
0.005
Vpk-pk
Oscillator Frequency
Gate Characteristics
Gate (G1 to G4)
Current Range
Voltage Low
Voltage High
Symbol
ID = 12mA, IG = -10uA
ID = 8mA, IG = 0
ID = 0, IG = -10uA,
V RCAL = 3.0V
1.8
2.0
1.2
0.05
0.05
50
1.8
2.7
1.7
Output Noise
Drain Voltage
Gate Voltage
Notes:
CGATE-GND = 10nF,
CDRAIN-GND = 10nF
CGATE-GND = 10nF,
CDRAIN-GND = 10nF
1. The two Vcc pins are internally connected, only one of the pins needs to be powered for the device to function. See applications section for further
information.
2. ESD sensitive, handling precautions are recommended.
3. The negative bias voltages are generated on-chip using an internal oscillator. Two external capacitors, CNB and CSUB of value 47nF are required for this
purpose.
4. The package (QFN1633) exposed pad must either be connected to Csub or left open circuit.
5. The characteristics are measured using two external reference resistors RCAL1 and RCAL2 of value 39k , wired from pins RCAL1/2 to ground. Resistor RCAL1
sets the drain current of FETs 1 and 3, resistor RCAL2 sets the drain currents of FETs 2 and 4.
6. Noise voltage measurements are made with FETs and gate and drain capacitors of value 10nF in place. Noise voltages are not measured in production.
ZABG4002
Document number: DS32047 Rev. 2 - 2
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ZABG4002
Typical Characteristics
(Measured at TAMB = 25°C, VCC = 3.3V, RCAL1 = RCAL2 = 39k (setting ID to 10mA) unless otherwise stated)
ZABG4002 Drain Voltage vs Drain Current
ZABG4002 Drain Current vs RCAL
2.2
15
D rain V o ltag e (V )
D rain C u rren t (m A )
5
2
1.9
0
10
100
1.8
1000
0
5
RCAL (k)
10
15
Drain Current (mA)
ZABG4002 Drain Voltage vs Temperature
ZABG4002 Drain Drain Current vs Temperature
2.3
20
18
2.2
16
D rain V oltage (V )
D rain C u rren t (m A )
14
12
10
8
2.1
2
1.9
6
4
1.8
2
1.7
0
-40
-20
0
20
40
60
-40
80
-20
0
20
40
60
80
Temperature (°C)
Temperature (°C)
ZABG4002 Substrate Voltage vs Substrate Current
-2
-2.2
S u b strate V o ltag e (V )
NEW PRODUCT
2.1
10
-2.4
-2.6
-2.8
-3
0
50
100
150
200
250
Substrate Current (uA)
ZABG4002
Document number: DS32047 Rev. 2 - 2
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ZABG4002
Applications Circuit
L*
JF1
NEW PRODUCT
D3
D2
G3
G2
D4
Vcc
L*
Vcc
C1
10nF
D1
C*
G1
Vcc
ZABG4002
G4
CNB
47nF
Rcal2
RCAL2
39k
CSUB
47nF
* Stripline Elements
Csub
C2
10nF
Cnb1
C*
Rcal1
Cnb2
Gnd
RCAL1
39k
Applications Information
Above is a partial applications circuit for the ZABG4002 showing all external components needed for biasing one of the four FET
stages available. Each bias stage is provided with a gate and drain pin. The drain pin provides a regulated 2.0V supply that
includes a drain current monitor. The drain current taken by the external FET is compared with a user selected level, generating a
signal that adjusts the gate voltage of the FET to obtain the required drain current. If for any reason, an attempt is made to draw
more than the user set drain current from the drain pin, the drain voltage will be reduced to ensure excess current is not taken.
The gate pin drivers are also current limited.
The bias stages are split up into two pairs, with the drain current of each pair set by an external RCAL resistor. RCAL1 sets the drain
currents of stages 1 and 3, whilst RCAL2 sets the drain currents of stages 2 and 4. This allows the optimisation of drain currents for
differing tasks such as input stages where noise can be critical and later amplifier stages where gain may be more important. A
graph showing the relationship between the value of RCAL and ID is provided in the Typical Characteristics section of this
datasheet. The RCAL pins can also be used as logic inputs. If set to a logic high state (>3.0V), the associated FET bias stages are
disabled, driving gate pins to -2.5V and switching drain pins open-circuit. This feature can be used as part of a power
management system that turns off any unwanted stages in a multi input receiver.
The ZABG4002 includes a switched capacitor DC-DC converter that is used to generate the negative supply required to bias
depletion mode FETs used in common source circuit configuration as shown above. This converter uses two external capacitors,
CNB the charge transfer capacitor and CSUB the output reservoir capacitor. The circuit provides a regulated -2.5V supply both for
gate driver use and for external use if required (for extra discrete bias stages, mixer bias, local oscillator bias etc.). The -2.5V
supply is available from the CSUB pin.
If any bias stages are not required, their gate and drain pins may be left open circuit. If all bias stages associated with an RCAL
resistor are not required, then this resistor may be omitted.
To ease PCB layout, the pinout for the ZABG4002 includes two Vcc pins. These pins are internally connected so only one of the
pins needs to be powered for the device to function. It is probable that the extra pin will help avoid the need for trace cross-over
components or ground plane disruption from reverse side PCB links. Note that the exposed pad of the package must be either left
floating or connected to Csub.
ZABG4002
Document number: DS32047 Rev. 2 - 2
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A Product Line of
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ZABG4002
Package Outline Dimensions
QFN16 3x3
Dim
Min
Max
A
0.55
0.65
A1
0.00
0.05
A3
0.15 Typ
b
0.18
0.28
D
2.95
3.05
D2
1.40
1.60
e
0.50 BSC
E
2.95
3.05
E2
1.40
1.60
L
0.35
0.45
Z
0.625 Typ
All Dimensions in mm
E
A1
D
A3
E2
Pin #1 ID
NEW PRODUCT
A
L
D2
e
b
Z
Note: Controlling dimensions are in millimetres. Approximate dimensions are provided in inches.
The package appearance may vary as shown, for further details please contact your local Diodes sales office.
Ordering Information
(Note x)
Device
Package
ZABG4002JA16TC
QFN1633
Reel Size
(inches)
13
Tape Width
(mm)
8
Quantity
(per reel)
3000
Marking Information
Pin 1
ZABG
4002
YYWW
ZABG4002
Document number: DS32047 Rev. 2 - 2
Part Name
Date Code
Year/Week
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ZABG4002
IMPORTANT NOTICE
NEW PRODUCT
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ZABG4002
Document number: DS32047 Rev. 2 - 2
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