Revised June 2001 74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs General Description Features The LVQ125 contains four independent non-inverting buffers with 3-STATE outputs. ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Guaranteed incident wave switching into 75Ω Ordering Code: Order Number Package Number Package Description 74LVQ125SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVQ125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Truth Table Pin Descriptions Inputs Pin Names Description An , Bn Inputs On Outputs Output An Bn L L L L H H H X Z On H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial © 2001 Fairchild Semiconductor Corporation DS011349 www.fairchildsemi.com 74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs February 1992 74LVQ125 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC ) Recommended Operating Conditions (Note 2) −0.5V to +7.0V DC Input Diode Current (IIK) Supply Voltage (VCC) 2.0V to 3.6V VI = −0.5V −20 mA Input Voltage (VI) 0V to VCC VI = VCC + 0.5V +20 mA Output Voltage (VO) 0V to VCC DC Input Voltage (VI) −0.5V to VCC + 0.5V Minimum Input Edge Rate (∆V/∆t) VO = −0.5V −20 mA VIN from 0.8V to 2.0V VO = VCC + 0.5V +20 mA VCC @ 3.0V DC Output Voltage (VO) 125 mV/ns −0.5V to VCC + 0.5V DC Output Source Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ±50 mA or Sink Current (IO) DC VCC or Ground Current ±200 mA (ICC or IGND) Storage Temperature (TSTG) −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) −65°C to +150°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Latch-Up Source or ±100 mA Sink Current DC Electrical Characteristics Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level TA = +25°C VCC (V) Typ 3.0 1.5 TA = −40°C to +85° C Units Conditions Guaranteed Limits 2.0 2.0 V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V 3.0 1.5 0.8 0.8 V 3.0 2.99 2.9 2.9 V 2.58 2.48 V 0.1 0.1 V 3.0 0.36 0.44 V 3.6 ±0.1 ±1.0 µA Leakage Current 3.6 ±0.25 ±2.5 µA VI = VCC, GND IOLD Minimum Dynamic (Note 4) 3.6 36 mA VOLD = 0.8V Min (Note 5) IOHD Output Current 3.6 −25 mA VOHD = 2.0V Min (Note 5) ICC Maximum Quiescent 40.0 µA Input Voltage VOH Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage IIN Maximum Input Leakage Current IOZ 3.0 3.0 0.002 or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH (Note 3) IOH = −12 mA IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA VI = VCC, GND VI (OE) = VIL, VIH Maximum 3-STATE VO = VCC, GND Supply Current VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Maximum High Level Dynamic Input Voltage VILD Maximum Low Level Dynamic Input Voltage 3.6 4.0 VIN = VCC or GND (Note 6)(Note 7) 3.3 0.6 1.0 V 3.3 −0.6 −1.0 V (Note 6)(Note 7) 3.3 1.7 2.0 V (Note 6)(Note 8) 3.3 1.5 0.8 V (Note 6)(Note 8) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 TA = +25°C Symbol tPLH Parameter Propagation Delay Data to Output Propagation Delay tPHL Data to Output tPZH Output Enable Time tPZL Output Enable Time Output Disable Time tPHZ tPLZ Output Disable Time tOSHL, Output to Output Skew (Note 9) tOSLH Data to Output TA = −40°C to +85°C CL = 50 pF VCC CL = 50 pF (V) Min Typ Max Min Max 2.7 1.0 7.8 12.7 1.0 14.0 3.3 ± 0.3 1.0 6.5 9.0 1.0 10.0 2.7 1.0 7.8 12.7 1.0 14.0 3.3 ± 0.3 1.0 6.5 9.0 1.0 10.0 2.7 1.0 7.2 14.8 1.0 16.0 3.3 ± 0.3 1.0 6.0 10.5 1.0 11.0 2.7 1.0 9.0 14.0 1.0 16.0 3.3 ± 0.3 1.0 7.5 10.0 1.0 11.0 2.7 1.0 9.0 14.0 1.0 15.0 3.3 ± 0.3 1.0 7.5 10.0 1.0 10.5 2.7 1.0 9.0 14.8 1.0 16.5 3.3 ± 0.3 1.0 7.5 10.5 1.0 11.5 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 Units ns ns ns ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = Open Conditions CPD (Note 10) Power Dissipation Capacitance 34 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. 3 www.fairchildsemi.com 74LVQ125 AC Electrical Characteristics 74LVQ125 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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