Revised February 2005 74VHC125 Quad Buffer with 3-STATE Outputs General Description Features The VHC125 contains four independent non-inverting buffers with 3-STATE outputs. It is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology and achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. ■ High Speed: tPD 3.8 ns (typ) at VCC ■ High noise immunity: VNIH 5V 4 PA (max) at TA ■ Lower power dissipation: ICC VNIL 25qC 28% VCC (min) ■ Power down protection is provided on all inputs ■ Low noise: VOLP 0.8V (max) ■ Pin and function compatible with 74HC125 Ordering Code: Order Number Package Package Description Number 74VHC125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC125MX_NL (Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC125SJ 74VHC125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC125MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDED J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS011632 www.fairchildsemi.com 74VHC125 Quad Buffer with 3-STATE Outputs August 1993 74VHC125 Logic Symbol Connection Diagram IEEE/IEC Function Table Pin Descriptions Pin Names An, Bn On Inputs Description Inputs Outputs An Bn On L L L L H H H X Z H HIGH Voltage Level L LOW Voltage Level Z HIGH Impedance X Immaterial www.fairchildsemi.com 2 Output Recommended Operating Conditions (Note 3) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r50 mA 65qC to 150qC Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) 0V to 5.5V Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) Lead Temperature (TL) VCC 3.3V r 0.3V 0 a 100 ns/V VCC 5.0V r 0.5V 0 a 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260qC (Soldering, 10 seconds) 2.0V to 5.5V Supply Voltage (VCC) Input Voltage (VIN) Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH VOL (V) TA Min 25qC 40qC to 85qC TA Typ Max Min 2.0 1.50 1.50 3.0 5.5 0.7 VCC 0.7 VCC 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 3-STATE Output 2.0 Units V VIN V Input Leakage ICC Quiescent Supply VIH IOH 50 PA or VIL 4.4 0.0 IOH V 0.1 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 IOH VIN V VIH IOL 4 mA 8 mA 50 PA or VIL 3.0 0.36 0.44 4.5 0.36 0.44 5.5 r0.25 r2.5 PA 0 5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 4.0 40.0 PA VIN VCC or GND V Off-State Current IIN Conditions V 2.0 HIGH Level Output LOW Level Output Max 3.0 5.5 Voltage Voltage IOZ VCC VIN VOUT IOL 4 mA IOL 8 mA VIH or VIL VCC or GND Current Current Noise Characteristics Symbol Parameter VOLP Quiet Output Maximum (Note 4) Dynamic VOL VOLV Quiet Output Minimum (Note 4) Dynamic VOL VIHD Minimum HIGH Level (Note 4) Dynamic Input Voltage VILD Maximum HIGH Level (Note 4) Dynamic Input Voltage TA VCC 25qC Units Conditions (V) Typ Limits 5.0 0.5 0.8 V CL 50 pF 5.0 0.5 0.8 V CL 50 pF 5.0 3.5 V CL 50 pF 5.0 1.5 V CL 50 pF Note 4: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC125 Absolute Maximum Ratings(Note 2) 74VHC125 AC Electrical Characteristics Symbol VCC Parameter tPLH Propagation Delay tPHL Time (V) 3.3 r 0.3 5.0 r 0.5 tPZL 3-STATE Output tPZH Enable Time 3.3 r 0.3 5.0 r 0.5 25qC TA Min TA 40qC to 85qC Typ Max Min Max 5.6 8.0 1.0 9.5 8.1 11.5 1.0 13.0 3.8 5.5 1.0 6.5 5.3 7.5 1.0 8.5 5.4 8.0 1.0 9.5 7.9 11.5 1.0 13.0 3.6 5.1 1.0 6.0 5.1 7.1 1.0 8.0 tPLZ 3-STATE Output 3.3 r 0.3 9.5 13.2 1.0 15.0 tPHZ Disable Time 5.0 r 0.5 6.1 8.8 1.0 10.0 tOSLH Output to Output Skew 3.3 r 0.3 1.5 1.5 5.0 r 0.5 1.0 1.0 10 10 tOSHL CIN Input Capacitance COUT Output Capacitance CPD Power Dissipation 4 Units Conditions CL 15 pF CL 50 pF CL 15 pF CL 50 pF 1 k: CL 15 pF CL 50 pF CL 15 pF CL 50 pF 1 k: CL 50 pF CL 50 pF CL 50 pF CL 50 pF ns ns ns RL ns ns ns RL (Note 5) pF VCC Open 6 pF VCC 5.0V 14 pF (Note 6) Capacitance Note 5: Parameter guaranteed by design. tOSLH |tPLHmax tPLHmin|; tOSHL |tPHLmax tPHLmin|. Note 6: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (OPR.) CPD * VCC * fIN ICC/4 (per bit). www.fairchildsemi.com 4 74VHC125 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com 74VHC125 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74VHC125 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com 74VHC125 Quad Buffer with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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