Revised May 2005 74VHC573 Octal D-Type Latch with 3-STATE Outputs General Description The VHC573 is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: tPD 5.0 ns (typ) at VCC ■ High Noise Immunity: VNIH VNIL 5V 28% VCC (Min) ■ Power Down Protection is provided on all inputs ■ Low Noise: VOLP 0.6V (typ) ■ Low Power Dissipation: ICC 4 PA (Max) @ TA 25qC ■ Pin and function compatible with 74HC573 Ordering Code: Order Number Package Number 74VHC573M 74VHC573SJ 74VHC573MTC 74VHC573N Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs © 2005 Fairchild Semiconductor Corporation DS011563 www.fairchildsemi.com 74VHC573 Octal D-Type Latch with 3-STATE Outputs March 1993 74VHC573 Functional Description Truth Table The VHC573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs, a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode, but, this does not interfere with entering new data into the latches. Inputs Outputs OE LE D On L H H H L H L L L L X O0 H X X Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) 0V to 5.5V Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) Lead Temperature (TL) VCC 3.3V r 0.3V 0 a 100 ns/V VCC 5.0V r 0.5V 0 a 20 ns/V Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260qC (Soldering, 10 seconds) 2.0V to 5.5V Supply Voltage (VCC) Input Voltage (VIN) Note 2: Unused inputs must be held HIGH or LOW They may not float. DC Electrical Characteristics Symbol VIH HIGH Level Input Voltage VIL VOL IOZ TA Min 25qC Typ 40qC to 85qC TA Max Min 2.0 1.50 1.50 3.0 5.5 0.7 VCC 0.7 VCC LOW Level Input Voltage VOH VCC (V) Parameter Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 2.58 2.48 4.5 3.94 3.80 0.0 0.1 Conditions V 3.0 5.5 HIGH Level Output Units V V VIN VIH or VIL IOH 50 PA IOH 4 mA IOH 8 mA V LOW Level Output 2.0 0.1 Voltage 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 V VIN VIH or VIL IOL 3.0 0.36 0.44 4.5 0.36 0.44 5.5 r0.25 r2.5 PA VIN 0 5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 4.0 40.0 PA VIN VCC or GND 3-STATE Output V Off-State Current Input Leakage Current ICC Quiescent Supply Current IOL 4 mA IOL 8 mA VIH or VIL VOUT IIN 50 PA VCC or GND Noise Characteristics Symbol Parameter TA 25qC VCC (V) Typ Limits Units Conditions VOLP (Note 3) Quiet Output Maximum Dynamic VOL 5.0 0.9 1.2 V CL 50 pF VOLV (Note 3) Quiet Output Minimum Dynamic VOL 5.0 0.8 1.0 V CL 50 pF VIHD (Note 3) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL 50 pF VILD (Note 3) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL 50 pF Note 3: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC573 Absolute Maximum Ratings(Note 1) 74VHC573 AC Electrical Characteristics Symbol VCC (V) Parameter tPLH Propagation Delay tPHL Time (LE to On) 3.3 r 0.3 5.0 r 0.5 tPLH Propagation Delay tPHL Time (D–On) 3.3 r 0.3 5.0 r 0.5 tPZL 3-STATE Output tPZH Enable Time 25qC TA Min 3.3 r 0.3 5.0 r 0.5 TA 40qC to 85qC Typ Max Min Max 7.6 11.9 1.0 14.0 10.1 15.4 1.0 17.5 5.0 7.7 1.0 9.0 6.5 9.7 1.0 11.0 7.0 11.0 1.0 9.5 14.5 4.5 CL 15 pF 50 pF CL 15 pF CL 50 pF 13.0 CL 15 pF 1.0 16.5 CL 50 pF 6.8 1.0 8.0 CL 15 pF 6.0 8.8 1.0 10.0 CL 50 pF 7.3 11.5 1.0 13.5 CL 15 pF 9.8 15.0 1.0 17.0 CL 50 pF 5.2 7.7 1.0 9.0 CL 15 pF 6.7 9.7 1.0 11.0 CL 50 pF CL 50 pF CL 50 pF CL 50 pF CL 50 pF 3-STATE Output 3.3 r 0.3 10.7 14.5 1.0 16.5 tPHZ Disable Time 5.0 r 0.5 6.7 9.7 1.0 11.0 tOSLH Output to Output Skew 3.3 r 0.3 1.5 1.5 5.0 r 0.5 1.0 1.0 10 10 CIN Input Capacitance COUT Output Capacitance CPD Power Dissipation Conditions CL tPLZ tOSHL Units 4 ns ns ns ns 1 k: RL ns ns ns 1 k: RL (Note 4) pF VCC Open 6 pF VCC 5.0V 29 pF (Note 5) Capacitance Note 4: Parameter guaranteed by design. tOSLH |tPLH max t PLH min|; tOSHL |tPHL max tPHL min| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN ICC/8 (per Latch). The total C PD when n pcs. of the Latch operates can be calculated by the equation: CPD(total) 21 8n. AC Operating Requirements Symbol Parameter TA VCC (V) Min 25qC Typ TA Max 40qC to 85qC Min tw(H) Minimum Pulse 3.3 r 0.3 5.0 5.0 tw(L) Width (LE) 5.0 r 0.5 5.0 5.0 tS Minimum Setup Time 3.3 r 0.3 3.5 3.5 5.0 r 0.5 3.5 3.5 3.3 r 0.3 1.5 1.5 5.0 r 0.5 1.5 1.5 tH Minimum Hold Time www.fairchildsemi.com 4 Max Units ns ns ns 74VHC573 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74VHC573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74VHC573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com 74VHC573 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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