Three-Phase Power MOSFET Controller A3938EQ, 32-pin PLCC A3938LQ, 36-pin QSOP A3938LD, 38-pin TSSOP The A3938 is a three-phase, brushless dc motor controller. The A3938 high-current gate drive capability allows driving of a wide range of power MOSFETs and can support motor supply voltages to 50 V. The A3938 integrates a bootstrapped high-side driver to minimize the external component count required to drive N-channel MOSFET drivers. Internal fixed off-time, PWM current-control circuitry can be used to regulate the maximum load current to a desired value. The peak load current limit is set by the user’s selection of an input reference voltage and external sensing resistor. A user-selected external RC timing network sets the fixed off-time pulse duration. For added flexibility, the PWM input can provide speed/torque control where the internal current control circuit sets a limit on the maximum current. The A3938 includes a synchronous rectification feature. This shorts out the current path through the power MOSFET reverse body diodes during PWM off-cycle current decay. This can minimize power dissipation in the MOSFETs, eliminate the need for external power clamp diodes, and potentially allow a more economical choice for the MOSFET drivers. The A3938 provides commutation logic for Hall sensors configured for 120-degree spacing. The Hall input pins are pulled-up to an internallygenerated 5 V reference. Power MOSFET protection features include: bootstrap capacitor charging current monitor, regulator undervoltage monitor, motor lead short-to-ground, and thermal shutdown. The LD package is available in a lead-free version (100% matte tin plated leadframe). ABSOLUTE MAXIMUM RATINGS Load Supply Voltage, VBB ...................................50 V VREG (Transient) ...............................................15 V Logic Input Voltage Range, VIN ...–0.3 V to VLCAP +0.3 V Sense Voltage, VSENSE ........................... –5 V to 1.5 V Pins: SA, SB, SC................................... –5 V to 50 V Pins: GHA, GHB, GHC .................. –5 V to VBB + 17 V Pins: CA, CB, CC ...........................SA/SB/SC + 17 V Operating Temperature Range Ambient Temperature, TA.............–20°C to +85°C Junction Temperature, TJ............................+150°C Storage Temperature, TS ..........–55°C to +150°C Thermal Impedance (Typical), at TA = +25ºC; measured on a JEDEC-standard "High-K" PCB A3938EQ, RθJA ........................................37°C/W A3938LD, RθJA ........................................38°C/W A3938LQ, RθJA ........................................44°C/W FEATURES Drives wide range of N-channel MOSFETs Low-side synchronous rectification Power MOSFET protection Adjustable dead time for cross-conduction protection Selectable coast or dynamic brake on power-down or RESET input Fast/slow current decay modes Internal PWM current control Motor lead short-to-ground protection Internal 5 V regulator Fault diagnostic output Thermal shutdown Undervoltage protection Use the following complete part numbers when ordering: Part Number Pins Package A3938SEQ 32 PLCC A3938SLQ 36 QSOP A3938SLD 38 TSSOP A3938SLD-T 38 TSSOP, Lead-free Data Sheet 26301.104B A3938 Three-Phase Power MOSFET Controller Functional Block Diagram (This diagram shows only one of the three outputs) FAULT Short to GND TSD A O.D. VBB Invalid Hall VREG Undervoltage + VREG LCAP 0.1 uF Regulator + + 10 uF 0.1 uF H1 CA Charge Pump H2 CBOOT 0.1 uF H3 PWM DIR Control Logic High-Side Protection Logic Turn-On Delay High-Side Driver To Phase C GHA RESET SA BRAKE VREG MODE Low-Side Protection Logic RC CT Turn-On Delay Low-Side Driver GLA To Phase B RC Blanking Fixed Off-Time RT SENSE RS REF PGND VREG DEAD Dead-Time Adjust BRKCAP VREGUVLO Power Loss Brake RESET BRKSEL + 4.7uF AGND A For 12 V applications, VBB must be shorted to VREG. For this condition, the absolute maximum rating of 15 V on VREG must be maintained to prevent damage to the A3938. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 2 Data Sheet 26301.104B A3938 Three-Phase Power MOSFET Controller ELECTRICAL CHARACTERISTICS1,2 Unless otherwise noted: TA = 25°C, VBB = 18 V to 50 V, CLCAP = 0.1 µF, CBOOT = 0.1 µF, CVREG = 10 µF, PWM = 22.5 kHz, square wave, two phases active Characteristics Quiescent Current Symbol IVBB Test Conditions RESET = 1, Coast mode, stopped Min. Typ.1 Max. Units – – 8.0 mA LCAP Regulator VLCAP Ilcap = –3.0 mA 4.75 5 5.25 V VREG =VBB Supply Voltage Range VREG VREG = VBB, observe maximum rating = 15 V 10.8 – 13.2 V – V VREG VBB – 2.5 – VREG Output Voltage 12.4 13 13.6 V VBB = 13.2 V to 18 V, Ivreg = –10 mA VBB = 18 V to 50 V, Ivreg = –10 mA VREG Load Regulation VREGLOAD Ivreg = –1 mA to –30 mA, Coast mode – 25 – mV VREG Line Regulation VREGLIN Ivreg = –10 mA, Coast mode – 40 – mV Control Logic VIN(1) Minimum high level for logical 1 2.0 – – V VIN(0) Maximum low level for logical 0 – – 0.8 V IIN(1) VIN = 2.0 V –30 – –90 µA IIN(0) VIN = 0.8 V –50 – –130 µA Low-Side Drive, Output High VHGL Igx = 0 – V High-Side Drive, Output High VHGH Igx = 0 Logic Input Voltage Logic Input Current Gate Drive VREG – 0.8 VREG – 0.5 10.4 11.6 12.8 V Pull-Up Switch Resistance RDS(ON) Igx = –50 mA – 14 – Ω Pull-Down Switch Resistance RDS(ON) Igx = 50 mA – 4 – Ω Low-Side Switching, 10/90 Rise Time trGL Cload = 3300 pF – 120 – ns Low-Side Switching, 10/90 Fall Time tfGL Cload = 3300 pF – 60 – ns High-Side Switching, 10/90 Rise Time trGH Cload = 3300 pF – 120 – ns High-Side Switching, 10/90 Fall Time tfGH Cload = 3300 pF – 60 – ns Propagation Delay; GHx,GLx Rising Tpr PWM to gate drive out, Cload = 3300 pF – 220 – ns Propagation Delay; GHx,GLx Falling Tpf PWM to gate drive out, Cload = 3300 pF – 110 – ns Dead Time, Maximum tDEAD Vdead = 0, GHx to GLx, Cload = 0 3.5 5.6 7.6 µs Dead Time, Minimum tDEAD IDEAD = 780 µA, GLx to GHx, Cload = 0 50 100 150 ns Continued on next page... www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3 Data Sheet 26301.104B A3938 Three-Phase Power MOSFET Controller ELECTRICAL CHARACTERISTICS1,2 (continued) Unless otherwise noted: TA = 25°C, VBB = 18 V to 50 V, CLCAP = 0.1 µF, CBOOT = 0.1 µF, CVREG = 10 µF, PWM = 22.5 kHz, square wave, two phases active Characteristics Symbol Test Conditions Min. Typ.1 Max. Units 10.4 11.6 12.8 V – 9 12 Ω 100 – – mA Bootstrap Capacitor Bootstrap Capacitor Voltage VCX Icx = 0, Vsx = 0, Vreg = 13 V Bootstrap ROUT RCX Icx = –50 mA Charge Current (Source) ICX Current Limit Circuitry Input Offset Voltage VIO 0 V < Vcmr < 1.5 V – – ±5 mV Input Current , Sense pin IB 0 V < Vcm, Vdiff < 1.5 V – –25 – µA Input Current , Reference pin IB 0 V < Vcm, Vdiff < 1.5 V – 0 – µA tBLANK R = 56 kΩ, C = 470 pF – 0.91 – µs IRC –0.9 –1 –1.1 mA VRCL 1.0 1.1 1.2 V VRCH 2.7 3.0 3.3 V – mA Blank Time RC Charge Current RC Voltage Threshold Protection Circuitry Bootstrap Charge Threshold Short to Ground, Drain-Source Monitor VREG Undervoltage Threshold Icx Vdsh UVLO GHx turns on, and GLx turns off, at Icx – –9 VBB – VSX, high side on 1.3 2.0 2.7 V VREG increasing 9.2 9.7 10.2 V VREG decreasing 8.6 9.1 9.6 V Fault Output Voltage VOUT IOL = 1 mA – – 0.5 V Brake Capacitor Supply Current IBRAKE VBB = 8 V, BRKSEL = 1 – 30 – µA Low Side Gate Voltage VGLBH VBB=0, BRKCAP = 8V – 6.6 – V Thermal Shutdown Temperature TJ – 165 – °C Thermal Shutdown Hysteresis ∆TJ – 10 – °C 1 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 2 Negative current is defined as conventional current coming out of (sourced from) the specified device terminal. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 4 Data Sheet 26301.104B A3938 Three-Phase Power MOSFET Controller Pin Descriptions RESET. A logic input that enables the device. Has internal 50 kΩ pull-up to LCAP. Setting RESET to 1 coasts or brakes the motor, depending on the state of the BRKSEL pin. Setting RESET to 0 enables the gate drive to follow commutation logic. Setting RESET to 1 overrides the BRAKE pin. GLA/GLB/GLC. Low-side gate drive outputs for external MOSFET drivers. External series gate resistors can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of Sx outputs. SA/SB/SC. Directly connected to the motor terminals, these pins sense the voltages switched across the load. The pins are also connected to the negative side of the bootstrap capacitors and the negative supply connections for the floating high-side drivers. GHA/GHB/GHC. High-side gate drive outputs for N-channel MOSFET drivers. External series gate resistors can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of Sx outputs. CA/CB/CC. High-side connections for bootstrap capacitors, providing positive supply for high-side gate drivers. The bootstrap capacitors are charged to approximately VREG when the output Sx terminals go low. When the outputs swing high, the voltages on these pins rise with the outputs to provide the boosted gate voltages needed for the N-channel power MOSFETs. MODE. Logic input to set current-decay mode. In response to a PWM Off command, Slow Decay mode (MODE = 1) switches off the high-side FET, and Fast Decay mode (MODE = 0) switches off the high-side and low-side FETs. Has an internal 50 kΩ pull-up to LCAP. H1/H2/H3. Hall sensor inputs with internal, 50 kΩ pull-ups to LCAP. Configured for 120-degree electrical spacing. DIR. Logic input to reverse rotation (see the table Commutation Truth Table, on the next page). Has internal, 50 kΩ pull-up to LCAP. FAULT. Open-drain output to indicate fault condition. Will be pulled high (usually by 5.1 kΩ external pull-up) for any of the following fault conditions: • Invalid Hall sensor input code (coasts the motor). • Undervoltage condition detected at VREG (coasts or brakes the motor depending on stored setting for BRKSEL). • Thermal shutdown (coasts the motor). • Motor lead (SA/SB/SC) connected to ground (turns off only the high-side power MOSFETs). Only the “short-to-ground” fault is latched, but it is cleared at each commutation. If the motor has stalled due to a shortto-ground being detected, toggling the RESET pin or repeating a power-up sequence clears the fault. BRAKE. Logic input for braking function. Setting BRAKE to 1 turns on low-side MOSFETs, and turns off the high-side MOSFETs. This effectively shorts the BEMF in the windings and brakes the motor. Internal 50 kΩ pull-up to LCAP. Setting RESET to 1 overrides this BRAKE pin. See also BRKSEL. BRKCAP. This pin is for connection of the reservoir capacitor used to provide the positive power supply for the sink drive outputs for a power-down condition. This allows predictable braking, if desired. Using a 4.7 µF capacitor will provide 6.5 V gate drive for 300 ms. If the power-down braking option is not needed (i.e., BRKSEL = 0), then this pin should be tied to VREG. BRKSEL. Logic input to enable/disable braking upon power-down condition or RESET = 1. Internal 50 kΩ pull-up to LCAP. Setting BRKSEL to 0 enables Coast mode. Setting BRKSEL to 1 enables Brake mode. PWM. Speed control input. Setting PWM to 1 turns on MOSFETs selected by Hall input logic. Setting PWM to 0 turns off the selected MOSFETs. Keep the PWM input held high to utilize internal current control circuitry. Internal 50 kΩ pull-up to LCAP. RC. Analog input. Connection for RT and CT to set the fixed off-time. CT also sets the BLANK time (see the section Application Information). It is recommended that the fixed off-time should not be less than 10 µs. The resistor should be in the range between 10 kΩ and 500 kΩ. VREG. Regulated 13 V supply for the low-side gate drive and the bootstrap capacitor charge circuit. As a regulator, use a 10 µF decoupling/storage capacitor (ESR < 1 Ω) from this pin to AGND, as close to the device pins as possible. Note: For 12 V applications, the VREG pin should be shorted to VBB. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5 Data Sheet 26301.104B A3938 Three-Phase Power MOSFET Controller VBB. Motor power supply connection for the A3938 and DEAD. Analog input. A resistor between DEAD and LCAP for power MOSFETs. It is good practice to connect a decoupling capacitor from this pin to AGND, as close to the device pins as possible. is selected to adjust turn-off time to turn-on time. This delay is needed to prevent cross-conduction in the external power MOSFETs. See the section Application Information for details on setting dead time. REF. Analog input to current limit comparator. Voltage applied here sets the peak load current according to the following equation: ITRIP = VREF / RSENSE SENSE. Analog input to the current limit comparator. Voltage representing load current appears on this pin. Voltage transients that are seen at this pin when the drivers turn on are ignored for period of time, tBLANK. LCAP. 5 V reference to power internal logic and provide AGND. Analog reference ground. low current for DEAD pin and FAULT pin. Connection for 0.1 µF external capacitor for decoupling. PGND. Return for low-side gate drivers. This should be connected to the PCB power ground. Commutation Truth Table H1 1 1 1 0 0 0 1 1 1 0 0 0 H2 0 0 1 1 1 0 0 0 1 1 1 0 H3 1 0 0 0 1 1 1 0 0 0 1 1 DIR 1 1 1 1 1 1 0 0 0 0 0 0 GLA 0 0 1 1 0 0 1 0 0 0 0 1 GLB 0 0 0 0 1 1 0 1 1 0 0 0 GLC 1 1 0 0 0 0 0 0 0 1 1 0 GHA 1 0 0 0 0 1 0 0 1 1 0 0 GHB 0 1 1 0 0 0 0 0 0 0 1 1 GHC 0 0 0 1 1 0 1 1 0 0 0 0 SA HI Z LO LO Z HI LO Z HI HI Z LO SB Z HI HI Z LO LO Z LO LO Z HI HI SC LO LO Z HI HI Z HI HI Z LO LO Z Input Logic MODE PWM RESET Quadrant Mode of Operation** PWM chop – current decay with opposite of selected low0* 0 0 Fast decay side drivers ON. Selected drivers ON. If current limiting, opposite of selected 0* 1 0 Fast Decay low-side drivers ON. 1 0 0 Slow decay PWM chop – current decay with both low-side drivers ON. 1 1 0 Slow Decay Selected drivers ON. If current limiting, both low-side drivers ON. All high-side drivers OFF, low-sides see BRKSEL stored. X X 1 X Clears storable faults. * Low-side, only, Synchronous Rectification mode. **See Commutation Truth Table for meaning of “both” and "selected." www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6 Data Sheet 26301.104B A3938 Three-Phase Power MOSFET Controller Application Information Synchronous Rectification. To reduce power consumption in the external MOSFETs, during the load current recirculation PWM-off cycle, the A3938 control logic turns on the appropriate low-side driver only. The reverse body diode of the power MOSFET conducts only during the dead time required at each PWM transition, as usual. However, unlike full synchronous rectification, the opposite high-side FET’s body diode (not the RdsON) will carry the re-circulating current, be self-extinguishing, and not force the motor to reverse direction. Dead Time. To prevent cross-conduction, it is required to have a delay between a high-side or low-side turn-off, and the next turn-on event. The potential for cross-conduction occurs with synchronous rectification, direction changes, PWM, or after a bootstrap capacitor charging cycle. This dead-time is set via a resistor from the DEAD pin to LCAP and can be varied from 100 ns to 5.5 µs. For a nominal case, given: • 25°C ambient temperature, and • 5.6 kΩ < Rdead < 470 kΩ, tdead (nom,ns) = 37 + [(11.9 ×10 ) × (R -3 dead + 500)] For predicting worst-case overvoltage and temperature extremes, use the following equations: tdead (min,ns) = 10 + [(6.55 ×10 ) × (R dead + 350)] ×10 ) ×(R dead + 650)] tdead (max,ns) = 63 + [(17.2 -3 -3 For nominal comparison with Idead currents, also at 25°C ambient temperature: Idead = (Vlcap – Vbe) / (Rdead + Rint) Decoupling. The internal reference VREG supplies current for the gate drive circuit. As the gates are driven high, they will require current from an external decoupling capacitor to support the transients. This capacitor should be placed as close as possible to the VREG pin. The value of the capacitor should be at least 20 times larger than the bootstrap capacitor. Additionally, a 1 nF (or larger) ceramic monolithic capacitor should be connected between LCAP and AGND, as close to the device pins as possible. Protection Circuitry. The A3938 has several protection features: • Bootstrap Monitor. The bootstrap capacitor is charged whenever a sink-side MOSFET is on, an Sx output goes low, or load current recirculates. This happens constantly during normal operation. Note: The high side will not be allowed to turn on before the charging has decayed to less than approximately 9 mA. • Undervoltage. VREG supplies the low-side gate driver and the bootstrap charge current. It is critical to ensure that the voltages are at a proper level before enabling any of the outputs. The undervoltage circuit is active during power-up and signals a fault, and also coasts or brakes (depending on the stored BRKSEL setting) the motor during that time period, until VREG is greater than approximately 10 V. On powering down, a fault is signaled and the motor is coasted or braked, depending on the stored setting for BRKSEL. • Hall Invalid. Illegal codes for the Hall sensor inputs (0,0,0 or 1,1,1) force a fault and coast the motor. Noisy Hall lines may cause Hall code errors, and therefore faults. Additional external pull-up loading and filtering may be required in some systems. where Vlcap = 5 V, Vbe = 0.7 V, and Rint = 500 Ω. Hint: Use dividers to the VREG terminal, than to the LCAP terminal, because the VREG terminal has more current capability. Rather than use Rdead values near 470 kΩ, set Vdead = 0 V, which activates an internal (Idead = 10 µA) current source. 165°C cause the A3938 to signal a fault and coast the motor. The choice of power MOSFET and external gate resistance determines the selection of the dead-time resistor. The dead time should be made long enough to cover the variation of the MOSFET capacitance and gate resistor tolerances (both external and internal to the A3938). • Motor Lead. The A3938 signals a fault if the motor lead is shorted to ground. A short-to-ground is assumed after a high- side is turned on and greater than 2 V is measured between the drain (VBB) and source (Sx) of the high-side power MOSFET. This fault is cleared at the beginning of • Thermal Shutdown. Junction temperatures greater than www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 7 Data Sheet 26301.104B A3938 Three-Phase Power MOSFET Controller each commutation. If a stalled motor results from a fault, the fault can only be cleared by toggling the RESET pin or by a power-up sequence. Current Regulation. Load current can be regulated by an internal fixed off-time, PWM-control circuit. When the outputs of the MOSFETs are turned on, current increases in the motor winding until it reaches a value given by: tBLANK = 1.9 ×C T / (1 × 10 -3 – [2 / RT]) The user must ensure that CT is large enough to cover the current spike duration. Braking. The A3938 dynamically brakes the motor by ITRIP = VREF / RSENSE At the trip point, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for the fixed offtime period. The current path during recirculation is determined by the configuration of the MODE and SR input pins. The fixed off-time is determined by an external resistor, RT, and capacitor, CT, connected in parallel from the RC terminal to AGND. The fixed off-time is approximated by: tOFF = RT of the power MOSFETs. To prevent false tripping of the sense comparator, the BLANK function disables the comparator for a time period defined by: ×C T tOFF should be in the range between 10 µs and 50 µs. Larger values for tOFF could result in audible noise problems. For proper circuit operation, 10 kΩ < RT < 500 kΩ. Torque control can be implemented by varying the REF input voltage as long as the PWM input stays high. If direct control of the torque/current is desired by PWM input, a voltage can be applied to the REF pin to set an absolute maximum current limit. PWM Blank. The capacitor CT also serves as the means to set the BLANK time duration. At the end of a PWM off-cycle, a high-side gate selected by the commutation logic turns on. At this time, large current transients can occur during the reverse recovery time, trr, of the intrinsic body diodes forcing all low-side power MOSFETs on, and all high-side power MOSFETs off. This effectively short-circuits the BEMF and brakes the motor. During braking, the load current can be approximated by: IBRAKEPEAK = VBEMF / RLOAD As the current does not flow through the sense resistor during a dynamic brake, care should be taken to ensure that the maximum ratings of the power MOSFETs are not exceeded. Note: On its rising edge, a RESET setting of 1 overrides the BRAKE input pin and latches the condition selected by the BRKSEL pin. Power Loss Brake. The BRKCAP and BRKSEL pins provide a power-down braking option. A Power-Loss Brake Trigger Event, which is either an undervoltage on VREG or a RESET = 1 rising edge, is sensed by the A3938, which then dynamically brakes or coasts (depending on the stored BRKSEL setting) the motor. The reservoir capacitor on the BRKCAP pin provides the positive voltage that forces the low-side gates of the power MOSFETs high, keeping them on, even after supply voltage is lost. A stored setting of BRKSEL = 1 brakes the motor, but a stored setting of BRKSEL = 0 coasts it. The combined effect of these settings is shown in the table Brake Control. Brake Control BRAKE 0 0 1 1 BRKSEL 0 1 0 1 Before Power Loss Brake Trigger Event Normal run mode Normal run mode Brake mode – All low-side gate drivers ON Brake mode – All low-side gate drivers ON After Power Loss Brake Trigger Event Coast mode – All gate drive outputs OFF Brake mode – All low-side gate drivers ON Coast mode – All gate drive outputs OFF Brake mode – All low-side gate drivers ON www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8 Data Sheet 26301.104B A3938 Three-Phase Power MOSFET Controller Terminal List Name Description 32-Lead A3938EQ PLCC 36-Lead A3938LQ QSOP 38-Lead A3938LD TSSOP PGND Low-Side Gate Drive Return 1 36 36 RESET Control Input 2 1 1 Low-Side Gate Drive Output, Phase C 3 2 2 Motor Connection, Phase C 4 3 3 GLC SC GHC High-Side Gate Drive Output, Phase C 5 6 6 CC Bootstrap Capacitor, Phase C 6 7 7 GLB Low-Side Gate Drive Output, Phase B 7 8 8 Motor Connection, Phase B 8 9 9 High-Side Gate Drive Output, Phase B 9 10 10 CB Bootstrap Capacitor, Phase B 10 11 11 GLA Low-Side Gate Drive Output, Phase A 11 12 12 Motor Connection, Phase A 12 13 13 High-Side Gate Drive Output, Phase A 13 14 14 Bootstrap Capacitor, Phase A 14 15 15 VREG Gate Drive Supply 15 16 16 LCAP 5 V Output 16 17 17 FAULT Diagnostic Output 17 19 19 MODE Control Input 18 20 20 VBB Load Supply 19 21 21 H1 Hall Control Input 20 22 22 H3 Hall Control Input 21 24 24 H2 Hall Control Input 22 25 25 DIR Control Input 23 26 26 BRAKE Control Input 24 27 27 BRKCAP Power Loss Brake Reservoir Capacitor 25 28 28 BRKSEL Control Input 26 29 29 PWM Control Input 27 30 30 Connection for Fixed Off-Time R and C 28 31 31 Sense Resistor 29 32 32 SB GHB SA GHA CA RC SENSE Current Limit Adjust 30 33 33 DEAD REF Dead Time Adjust 31 34 34 AGND Ground 32 35 35 4,5,18,23 4, 5, 18, 23, 37, 38 N/C Not Connected www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 9 Data Sheet 26301.104B A3938 A3938EQ, 32-pin PLCC .453 11.51 .447 11.35 30 REF 31 DEAD 1 PGND 32 AGND 2 RESET 3 GLC 4 SC .495 12.57 .485 12.32 GHC 5 1 .013 0.32 .008 0.19 32 29 SENSE CC 6 28 RC GLB 7 27 PWM SB 8 26 BRKSEL GHB 9 25 BRKCAP CB 10 24 BRAKE GLA 11 SA 12 .595 15.11 .585 14.86 23 DIR Control Logic Fault .553 14.05 .547 13.89 22 H2 .015 0.38 MIN H1 20 VBB 19 MODE 18 FAULT 17 LCAP 16 CA 14 21 H3 VREG 15 GHA 13 Seating Plane Base Plane .021 0.53 .013 0.33 .140 3.56 .125 3.18 .050 1.27 BSC .095 2.41 .060 1.52 Dimensions in inches Metric dimensions (mm) in brackets, for reference only If unit is intended to be socketed, it is advisable to review lead profile with socket supplier A3938LQ, 36-pin QSOP 15.40 .606 15.20 .598 RESET 1 36 PGND GLC 2 35 AGND SC 3 34 DEAD N/C 4 33 REF N/C 5 32 SENSE GHC 6 31 RC CC 7 30 PWM GLB 8 29 BRKSEL SB 9 28 BRKCAP GHB 10 SA 13 GHA 14 CA 15 0.32 .013 0.23 .009 7.60 .299 7.40 .291 1.27 .050 0.40 .016 10.51 .414 10.11 .398 27 BRAKE CB 11 GLA 12 8º 0º 36 Fault Control Logic 1 26 DIR 2 .355 0.014 BSC 25 H2 24 H3 Seating Plane Gauge Plane 23 N/C 22 H1 VREG 16 21 VBB LCAP 17 20 MODE N/C 18 19 FAULT 0.51 .020 0.28 .011 0.80 .031 REF 0.85 .033 BSC 2.64 .104 2.44 .096 0.30 .012 0.10 .004 Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 10 Data Sheet Three-Phase Power MOSFET Controller 26301.104B A3938 A3938LD, 38-pin TSSOP RESET 1 38 N/C GLC 2 37 N/C SC 3 36 PGND N/C 4 35 AGND N/C 5 34 DEAD GHC 6 33 REF CC 7 32 SENSE GLB 8 31 RC SB 9 Fault Control Logic 4.5 0.177 4.3 0.169 6.4 0.252 BSC 1 0.039 REF 1 2 0.75 0.030 0.45 0.018 27 BRAKE .25 0.010 BSC 26 DIR 25 H2 CA 15 24 H3 VREG 16 23 N/C LCAP 17 22 H1 N/C 18 0.20 0.008 0.09 0.004 28 BRKCAP GHA 14 FAULT 19 8º 0º 38 29 BRKSEL CB 11 SA 13 0.386 0.378 30 PWM GHB 10 GLA 12 9.8 9.6 Seating Plane Gauge Plane 0.27 0.011 0.17 0.007 21 VBB 20 MODE 1.10 0.043 MAX .50 .020 BSC 0.15 0.05 0.006 0.002 Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2003 AllegroMicrosystems, Inc. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 11 Data Sheet Three-Phase Power MOSFET Controller 26301.104B A3938