A8601 Multiple-Output Regulator for Automotive LCD Displays Features and Benefits Description • Automotive Grade AEC-Q100 qualified • Five individual output supplies • Independent control of each output voltage • 350 kHz to 2.25 MHz switching frequency with external synchronization capability • <10 μA shutdown current • Preprogrammed power-up and shutdown sequences • Overcurrent, overvoltage, short circuit, and thermal overload protection The A8601 is a fixed frequency, multiple-output supply for LCD bias. Its switching frequency can be either programmed or synchronized with an external clock signal between 350 kHz and 2.25 MHz, to minimize interference with AM and FM radio bands. A total of five output voltages are provided, from three linear regulators and two charge-pump regulators. Each output voltage can be adjusted independently. During power-up and shutdown, the outputs are turned on and off in preprogrammed sequences, to meet the sequencing requirements for specific LCD panels. Applications: • GPS • Infotainment • Medium LCDs Short circuit protection is provided for all outputs. The boost switch is protected against overcurrent and overvoltage. Input disconnect protection is achieved by driving an external P-MOSFET. Package: 28-pin TSSOP with exposed thermal pad (suffix LP) 28-pin exposed thermal pad TSSOP package allows operation at high ambient temperatures. It is lead (Pb) free with 100% matte-tin leadframe plating. Not to scale System Block Diagram RSC VIN VIN Optional Q1 L1 INS GATE D1 SW OUT DVDD VDVDD 3.3 V EN1 EN2 A8601 AVDD VAVDD 5 to 14 V LCD Panel External Sync FSET_SYNC VGH VVGH 10 to 25 V + VVGL – 5 to –12 V VVIN VGL + FAULT 1.5 to 3.2 V VINAMP VCOM VVCOM 3 to 6 V + Output voltages shown are for typical LCD Panel A8601-DS, Rev. 1 A8601 Multiple-Output Regulator for Automotive LCD Displays Selection Guide Part Number A8601KLPTR-T Packing* Programming 4000 pieces per 13-in. reel Contact Allegro Sales for VCOM regulator factory trim option *Contact Allegro® for additional packing options. Absolute Maximum Ratings1,2 Characteristic VIN and INS Pin Voltage Symbol VVIN, VINS Rating Unit All voltages measured with respect to GND Notes –0.3 to 6.5 V Continuous –0.6 to 22 V –1 to 40 V SW Pin Voltage3,4 VSW OUT Pin Voltage VOUT –0.3 to 22 V VAVDD , VFB2 –0.3 to VOUT + 0.3 V AVDD and FB2 Pin Voltage Voltage spikes (pulse width < 100 ns) CP11 Pin Voltage VCP11 Positive charge pump –0.3 to VCP12 + 0.3 V CP12 Pin Voltage VCP12 Positive charge pump –0.3 to 27 V VGH Pin Voltage VVGH Positive charge pump –0.3 to 27 V FB4 Pin Voltage VFB4 Positive charge pump –0.3 to VVGH + 0.3 V CP21 Pin Voltage VCP21 Negative charge pump –0.3 to 14 V CP22, VGL and FB3 Pin Voltage VCP22, VVGL, VFB3 Negative charge pump –14 to 0.3 V ¯¯A¯¯U¯¯L¯¯T ¯ Pin Voltage EN1, EN2, and ¯F VEN1, VEN2, VFAULT –0.3 to 5.5 V BIAS Pin Voltage VBIAS –0.3 to lower of: 5.5 or VVIN + 0.3 V VCOM Pin Voltage VVCOM –0.3 to lower of: 7 or VAVDD + 0.3 V VPGND, VGNDVCOM –0.3 to 0.3 V – –0.3 to 7 V PGND and GNDVCOM Pin Voltage All other pins5 Operating Ambient Temperature TA –40 to 125 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature K temperature range 1Stresses beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability. 2All voltages referenced to AGND. 3The SW pin has internal clamp diodes to GND. Applications that forward bias this diode should take care not to exceed the IC package power dissipation limits. Note: Exact energy specification to be determined. 4The switch DMOS is self-protected. If voltage spikes exceeding 40 V are applied, the device would conduct and absorb the energy safely. 5When V VIN = 0 (no power), all inputs are limited by -0.3 to 5.5 V. Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* On 4-layer PCB based on JEDEC standard Value Unit 28 ºC/W *Additional thermal information available on the Allegro website. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A8601 Multiple-Output Regulator for Automotive LCD Displays Table of Contents Characteristic Performance 10 Functional Description 15 15 15 16 18 19 20 21 22 23 23 Linear Regulators VCOM Regulator Charge Pumps Boost Controller Switching Frequency Continuous Conduction Mode Operation Input Disconnect Switch FAULT Conditions Pre-Output Fault Detection General Fault Detection Application Information Output Voltage Selection Output Capacitance Operating with Separate VIN and Boost Supplies Thermal Analysis Component Selection Recommendations I/O pin Equivalent Circuit Diagrams 24 24 25 26 26 28 29 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A8601 Multiple-Output Regulator for Automotive LCD Displays Functional Block Diagram RSC Q1 L1 D1 5 V DC to DC Converter ( 4 V min.) COUT INS GATE OUT SW Drive AVDD OCP 6 VIN VDVDD 3.3 V DVDD Boost Regulator REG with Soft Start LDO 1 FB1 ON OFF LDO 2 X1.94 OP AMP 5 ON EN1 External . Sync + VCOM EN2 + GNDVCOM COMP Enable/ Disable ON 2x Charge Pump OFF OFF VVIN 4 CP11 6 VVCOM 3 to6 V CVCOM CFLY1 CP12 VGH FB4 ON CAVDD 1.5 to 3.2 V from Microprocessor VINAMP – FSET_SYNC CCOMP + FB2 6 VAVDD 10V + 6 VVGH 18 V FAULT + Fault ON OFF VIN BIAS BIAS Regulator ON 90% CP21 + - – 10% Inverted Charge Pump 3 CFLY2 6 VVGL -8 V CP22 VGL FB3 + OFF 3.6 V OFF + – 90% PGND AGND 1 to 5 See Terminal List Table 6 Output voltages shown are for a typical LCD panel Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A8601 Multiple-Output Regulator for Automotive LCD Displays Pin-out Diagram 28 SW GATE 1 INS 2 27 PGND VIN 3 26 OUT 25 AVDD DVDD 4 24 FB2 FB1 5 COMP 6 VINAMP 7 23 CP11 PAD 22 CP12 21 VGH VCOM 8 20 FB4 GNDVCOM 9 FSET_SYNC 10 19 CP21 BIAS 11 18 CP22 FAULT 12 17 VGL EN1 13 16 FB3 EN2 14 15 AGND Terminal List Table Number Name Function Number Name Function Gate driver for input disconnect P-MOSFET 15 AGND Analog GND reference for signals; connect to ground plane 16 FB3 (VGL) Connect to resistor divider network to set VVGL 17 VGL Inverted charge pump output (item 3 in Functional Block Diagram) 18 CP22 Capacitor terminal for inverted charge pump (item 3 in Functional Block Diagram); refer to Negative Charge Pump section for usage 19 CP21 Capacitor terminal for inverted charge pump (item 3 in Functional Block Diagram) 20 FB4 (VGH) Connect to resistor divider network to set VVGH 21 VGH Ground reference for VCOM 22 CP12 23 CP11 FSET_SYNC Input for synchronizing boost and charge pump signals switching frequency to external clock signal; alternatively, it can be connected to an external resistor to set the switching frequency 24 FB2 (AVDD) 25 AVDD 11 BIAS Output from internal 3.6 V bias regulator; connect to GND via 0.1 μF ceramic capacitor Output from internal LDO (item 2 in Functional Block Diagram) powered by VOUT 26 OUT 12 ¯F ¯¯A¯¯U¯¯L¯¯T ¯ Open-drain output, pulls low in error condition Connect to boost output for internal LDO and charge pump regulators EN1 Enable pin for DVDD output; system can only be enabled after VVIN is above UVLO level (refer to Startup Timing Diagram) 27 PGND 28 SW Boost converter switch node EN2 Enable pin for the voltage outputs other than DVDD; it can be activated only after VVIN is above UVLO and EN1 = high. – PAD Exposed pad (substrate of IC); solder to GND plane for better thermal conduction 1 GATE 2 INS High-side sense for input overcurrent detection 3 VIN Input supply voltage (4.0 to 5.5 V) for the IC Output from internal LDO (item 1 in Functional Block Diagram) powered by VIN 4 DVDD 5 FB1 (DVDD) Connect to resistor divider network to set DVDD 6 COMP Compensation pin, connect to external COMP capacitor 7 VINAMP Control voltage from external microprocessor 8 VCOM 9 GNDVCOM 10 13 14 Output from operational amplifier (item 5 in Functional Block Diagram), controlled by VINAMP 2x charge pump (item 4 in Functional Block Diagram) output Capacitor terminals for charge pump (item 4 in Functional Block Diagram) Connect to external resistor network to set VAVDD Power ground for internal boost switch; connect this pin to ground terminal of output ceramic capacitor(s) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A8601 Multiple-Output Regulator for Automotive LCD Displays ELECTRICAL CHARACTERISTICS1 Valid at VVIN = 5 V, EN1 = EN2 = high, fSW = 2 MHz, VDVDD = 3.3 V, VAVDD = 10 V, VVGH = 20 V, VVGL = –8 V, TJ = TA = 25°C, except Characteristics indicates specifications guaranteed for TJ = TA = −40°C to 125°C; unless otherwise specified Symbol Test Conditions Min. Typ. Max. Unit 4.0 – 5.5 V 3.6 – 4.0 V Input Voltage and Current Input Voltage VVIN VIN Pin Undervoltage Lockout (UVLO) Threshold VUVLO VVIN rising VIN Pin UVLO Hysteresis VUVLO(HYS) – 0.15 0.25 V Shutdown Bias Current IVINBIAS(SD) Current into VIN pin, EN1 = low – 5 50 μA Standby Bias Current IVINBIAS(STB) EN1 = high, EN2 = low, no load at DVDD pin – 2 – mA Operating Bias Current IVINBIAS(OP) EN1 = high, EN2 = high – 6.5 – mA 1.3 – 2.0 A – 0.5 – Ω Boost Switch Switch Peak Current Limit ISW(MAX) Cycle-by-cycle current limit Switch On-Resistance RDS(on) ISW = 0.5 A Switch Minimum On-Time tON(MIN) 50 72 95 ns Switch Minimum Off-Time tOFF(MIN) 33 50 75 ns SW Pin Leakage Current ISW(LKG) VSW = 5 V, EN1 = low – 0.1 – μA OUT Pin Leakage Current IOUT(LKG) VOUT = 5 V, EN1 = low – 0.1 – μA SW Pin Secondary Overvoltage Protection (OVP) VSW(OVP) 17.4 19.2 21.2 V SW Pin Secondary OVP Minimum Pulse Width4 tSW(OVP) – 40 – ns VSW ≥ OVP level Switching Frequency / Synchronization FSET_SYNC Pin Voltage VFSETSYNC FSET_SYNC Pin Current IFSETSYNC Switching Frequency Synchronization Frequency fSW fSYNC – 1.0 – V 34 – 220 μA RFSET_SYNC = 5.1 kΩ 1.81 2.0 2.17 MHz External logic signal connected to FSET_SYNC pin 0.35 – 2.25 MHz Without using external synchronization signal Synchronization Minimum On-Time tSYNC(ON) 150 – – ns Synchronization Minimum Off-Time tSYNC(OFF) 150 – – ns – 100 – μA Input Disconnect IGATE(SNK) VGATE = VVIN , no fault GATE Pin Source Current IGATE(SRC) VGATE = 0 V, fault tripped GATE Voltage at Off Condition VGATE(OFF) EN1 = EN2 = low, or fault tripped GATE Pin Sink Current – 130 – mA – VVIN – V INS Trip Point VINS(TRIP) Between VIN and INS pins 85 100 115 mV INS Trip Blanking Time tINS(BLANK) Sensed voltage = 2 × input current limit 1.5 – 3 μs Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A8601 Multiple-Output Regulator for Automotive LCD Displays ELECTRICAL CHARACTERISTICS1 (continued) Valid at VVIN = 5 V, EN1 = EN2 = high, fSW = 2 MHz, VDVDD = 3.3 V, VAVDD = 10 V, VVGH = 20 V, VVGL = –8 V, TJ = TA = 25°C, except otherwise specified Characteristics indicates specifications guaranteed for TJ = TA = −40°C to 125°C; unless Symbol Test Conditions Min. Typ. Max. Unit Feedback Pins Feedback Sense Voltage VFBx Output Overvoltage Fault Threshold VFBx(OV) Output Undervoltage Fault Threshold VFBx(UV) Feedback Input Currents IFBx Feedback Load Resistance2 RFBx FB1, FB2, and FB4 pins – 2.40 – V FB3 pin – –1.8 – V FB1, FB2, and FB4 pins; VFBx rising – 2.88 – V VFB3 falling – –2.16 – V FB1, FB2, and FB4 pins; VFBx falling – 1.92 – V VFB3 rising – –1.44 – V FB1, FB2, and FB4 pins; VFBx = 2.4 V – –0.5 – μA VFB3 = –1.8 V – 0.5 – μA FB1 pin 9 10 11 kΩ FB2 pin 24 25 26 kΩ FB3 and FB4 pins 49 50 51 kΩ VDVDD VVIN = 4.0 to 5.5 V 2.4 – VVIN – 0.6 V AVDD Output Voltage VAVDD VVIN = 4.0 to 5.5 V 4.4 – 14.8 V VCOM Output Voltage VVCOM VVIN = 4.0 to 5.5 V, VAVDD > VVCOM + 1.5 V 2.9 – 6.8 V Output Regulators DVDD Output Voltage VGH Output Voltage VVGH VVIN = 4.0 to 5.5 V 2.4 – 26 V VGL Output Voltage VVGL VVIN = 4.0 to 5.5 V –12.9 – –5 V Dropout for DVDD Regulator VDVDD(DO) Between VIN and DVDD pins; VFB1 = 2.33 V, IOUT = 50 mA – – 0.6 V Boost Minimum Headroom for AVDD Regulator VAVDD(DO) Defined as VOUT – VAVDD; VFB2 = 2.33 V, IOUT = 100 mA – 2 – V Boost Minimum Headroom for VGH Regulator VVGH(DO) Defined as VOUT – VVGH / 2; VFB4 = 2.33 V, IOUT = 8 mA – 2.4 – V Boost Minimum Headroom for VGL Regulator VVGL(DO) Defined as VOUT – (–VVGL); VFB3 = –1.75 V, IOUT = –8 mA – 3.6 – V Output Pull-Down Resistor During Shutdown (AVDD, VCOM, VGH, VGL) ROUTPD EN1 = high, EN2 = low – 250 – Ω 1.8 – – V Logic Inputs Input Logic High Input Logic Low Internal Pull-Down Resistance to AGND VIH EN1, EN2, FSET_SYNC pins VIL EN1, EN2, FSET_SYNC pins – – 0.8 V EN1, EN2 pins – 100 – kΩ RENx(PD) Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A8601 Multiple-Output Regulator for Automotive LCD Displays ELECTRICAL CHARACTERISTICS1 (continued) Valid at VVIN = 5 V, EN1 = EN2 = high, fSW = 2 MHz, VDVDD = 3.3 V, VAVDD = 10 V, VVGH = 20 V, VVGL = –8 V, TJ = TA = 25°C, except otherwise specified Characteristics indicates specifications guaranteed for TJ = TA = −40°C to 125°C; unless Symbol Test Conditions Min. Typ. Max. Unit Output Current Capacity DVDD Overcurrent Protection (OCP) Trip Level IDVDD(OCP) 50 – 90 mA AVDD OCP Trip Level IAVDD(OCP) Includes iVCOM 200 – 350 mA 60 – 110 mA VCOM OCP Trip Level iVCOM VGH OCP Trip Level iVGH VGL OCP Trip Level iVGL Current into VGL pin 14 – 32 mA 14 – 32 mA Output Voltage Accuracy DVDD Load Regulation AVDD, VGL and VGH Load Regulation VDVDDreg VDVDD = 3.3 V, ILOAD = 10 to 50 mA –0.1 – 0.1 V Vxreg ILOAD = 10% to 100% of Ix(OCP)(min) –0.1 – 0.1 V DVDD Accuracy3 errDVDD VDVDD = 3.30 V –2.5 – 2.5 % AVDD Accuracy3 errAVDD VAVDD = 10.0 V –2.1 – 2.1 % VGH Accuracy3 errVGH VVGH = 20.0 V –2.5 – 2.5 % VGL Accuracy3 errVGL VVGL = –8.0 V –2.5 – 2.5 % AVCOM Defined as VVCOM / VVINAMP ; 1.5 V < VVINAMP < 3.21 V, –30°C < TA < 85°C, ILOAD = 25 mA 1.92 1.94 1.96 V/V VCOM Operational Amplifier VCOM Gain4 VCOM Load Regulation4 VVCOMreg ILOAD = 5 to 50 mA –5 – 5 mV VCOM Temperature Coefficient4 TCVCOM –30°C < TA < 85°C, ILOAD = 25 mA –50 – 50 μV/°C Input Resistance to AGND RVINAMP(PD) VINAMP pin – 100 – kΩ Dropout for VCOM from AVDD VVCOM(DO) VAVDD = 7 V, IVCOM = 60 mA – – 1.5 V ¯F ¯¯A¯¯U¯¯L ¯¯T ¯ Pin ¯F ¯¯A¯¯U¯¯L¯¯T ¯ Pull-Down Voltage VFAULT(PD) Fault condition asserted, pull-up current = 1 mA – – 0.4 V ¯F ¯¯A¯¯U¯¯L¯¯T ¯ Pin Leakage Current VFAULT(LKG) Fault condition cleared, pull-up to 5 V – – 1 μA Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A8601 Multiple-Output Regulator for Automotive LCD Displays ELECTRICAL CHARACTERISTICS1 (continued) Valid at VVIN = 5 V, EN1 = EN2 = high, fSW = 2 MHz, VDVDD = 3.3 V, VAVDD = 10 V, VVGH = 20 V, VVGL = –8 V, TJ = TA = 25°C, except otherwise specified Characteristics Symbol indicates specifications guaranteed for TJ = TA = −40°C to 125°C; unless Test Conditions Min. Typ. Max. Unit Fault Timers Soft Start Time-Out tSS(TO) Maximum time allowed for any output to reach 90% of its target 40 50 60 ms Shutdown Time-Out tSDN(TO) Maximum time allowed for VGH to fall to 10% and VGL to 30% of their respective targets; EN1 = high, EN2 = low 40 50 60 ms Overcurrent Protection (OCP) Time-Out tOCP(TO) Maximum time allowed for any output to stay in an overcurrent fault condition before shutdown 40 50 60 ms Restart Delay tRESTART Delay time after fault shutdown until the next retry (repeats until Fault counter = 8) 80 100 120 ms tfault Time required after setting EN1 = low until Fault counter clears 1 – – μs TTSD Temperature rising – 165 – °C – 20 – °C Fault Counter Reset Time Thermal Shutdown (TSD) Protection TSD Threshold TSD Hysteresis4 TTSD(HYS) 1For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). 2Net parallel resistance required at FBx pin in order to meet accuracy. 3Output voltage is set to required nominal value using external sense resistor network. Output current at 50% of minimum OCP trip level. Accuracy does not include mismatch error caused by external sense resistor network. 4Ensured by design and characterization, not production tested. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A8601 Multiple-Output Regulator for Automotive LCD Displays Characteristic Performance Startup and Shutdown Sequences (Normal Operation) VIN EN1 EN2 DVDD AVDD VGL VGH 90% t<100 ms 90% 30% 90% 90% 10% VINAMP VCOM Notes: • Normal system startup should follow the above sequence (VIN → EN1 → EN2). • EN1 can only be asserted after VIN is above UVLO level, VUVLO. If asserted before that, it is ignored until VIN rises above VUVLO. • EN2 can only be asserted when DVDD is >90% target voltage. If asserted before that, it is ignored until the condition is met. • VGH is enabled only after the magnitude of VGL has reached >90% of its target voltage. • VCOM output is enabled only after VGH has reached >90% of its target voltage. (A valid VINAMP must be asserted prior to this.) • System shutdown should start with EN2 = low, followed by EN1 = low. • VGL shutdown can only start after VGH has dropped to 10% its original target voltage, or the VGH shutdown time-out interval has expired. • EN1 = low can only be asserted when VGL has fallen below 30% of its target voltage. If asserted before that, it is ignored until the condition is met or the VGL shutdown time-out interval has expired. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A8601 Multiple-Output Regulator for Automotive LCD Displays Startup and Shutdown Sequences (Irregular) VUVLO VIN VIN EN1 EN1 EN1 EN2 EN2 EN2 DVDD AVDD VGL VGH 90% DVDD 90% 90% 90% AVDD VGL VGH VIN 90% DVDD 90% 90% 90% AVDD VGH VINAMP VINAMP VINAMP VCOM VCOM VCOM Case 1 (startup) 30% VGL Case 2 (startup) 10% Case 3 (shutdown) Notes: • Case 1 (startup). During a startup sequence, if EN2 goes high before EN1 goes high, EN2 is ignored until EN1 also goes high and DVDD has risen to 90% of its target voltage. • Case 2 (startup). During a startup sequence, while VIN is below the UVLO level, VUVLO , the IC is in sleep mode. If either EN1 or EN2 goes high while the IC is still in sleep mode, they are ignored until VIN exceeds VUVLO . • Case 3 (shutdown). During a shutdown sequence, if EN1 goes low before EN2 goes low, EN1 is ignored until EN2 also goes low and VGL has fallen to 30% of its target voltage, or the VGL shutdown time-out interval has expired. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A8601 Multiple-Output Regulator for Automotive LCD Displays Startup Timing Diagram >100 μs (determined by GATE pin capacitance) IC waits until GATE pin < (VVIN – 3.5 V) EN1 DVDD EN1 ignored ≈ 4 ms for 48 μF capacitor loading 90% ≈ 12 ms for typical capacitor loading EN2 AVDD VGL VGH VCOM EN2 ignored ≈ 3 ms for 48 μF capacitor loading 90% ≈ 4 ms for 24 μF capacitor loading 90% ≈ 4 ms for 10 μF capacitor loading ≈ 2 ms for 10 μF capacitor loading 90% 90% Notes: • Startup ramps are based on internal timing and are assumed to have ± 20% variation. • An internal pull-down resistor of 250 Ω is applied to each of the regulator outputs AVDD, VGL, VGH, and VCOM as soon as EN1 = high. That means if any output capacitor was previously charged, it would be discharged by this pull-down resistor. The pull-down is removed just before each regulator is enabled. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A8601 Multiple-Output Regulator for Automotive LCD Displays Shutdown Timing Diagram EN2 ≈22 ms for 40 μF capacitor discharge AVDD VCOM VGH 10% ≈6 ms for 10 μF capacitor discharge 10% ≈6 ms for 10 μF capacitor discharge 10% 30% VGL ≈ 7 ms for 24 μF capacitor discharge Cumulative ≈ 13 ms capacitor discharge for 10 μF on VGH and 24 μF on VGL EN1 EN1 ignored EN1 active after AVDD, VGH, and VCOM decay to <10%, and VGL decays to <30%, of their target values DVDD Device enters sleep mode Notes: • All exponential decays are based on external capacitance and internal pull-down resistance (250 Ω each for AVDD, VCOM, VGH, and VGL). The external DC load is assumed to be off or negligible. • If any of the outputs AVDD, VCOM, or VGH does not decay to below 10% of target voltage after 50 ms, starting from EN2 is low, it is by-passed and the rest of the shutdown sequence continues without it. • For VGL, the shutdown detection threshold is set at 30%. Only if the magnitude of VGL has dropped below 30%, when EN1 goes low the IC will shut down completely. After shutdown, all internal pull-down resistors are released, and output capacitor voltages will decay according to external load resistances. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A8601 Multiple-Output Regulator for Automotive LCD Displays Typical Load Current during Normal Operation AVDD VGL IAVDD(av) = 140.25 mA IVGL(av) = 8.9 mA 500 mA 30 mA 100 mA 4 mA 3.2 μs 3.2 μs 6 μs 31.8 μs 6 μs 31.8 μs VGH VCOM IVGH(av) = 7.9 mA IVCOM(av) = 18.3 mA 30 mA 50 mA 4 mA 15 mA 4.8 μs 31.8 μs 4.8 μs 6 μs 6 μs 63.6 μs Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A8601 Multiple-Output Regulator for Automotive LCD Displays Functional Description The A8601 is a flexible multi-voltage regulator designed for LCD panel bias applications. It utilizes a high-efficiency boost converter, together with space-saving low-dropout regulator and charge pump circuits to provide five independently-adjustable voltage outputs: • DVDD: Typically 3.3 V. Nominal output current 20 mA, maximum 100 mA. This output is from a low-dropout regulator (item 1 in the Functional Block Diagram) powered by VIN. It is available while EN1 is high. • AVDD: Typically between 5 and 13.3 V. Nominal current 100 mA. This output is from a low-dropout regulator (item 2 in the Functional Block Diagram) powered by VOUT. It is only available when both EN1 and EN2 are high. • VCOM: Typically between 3 and 6 V at 50 mA. This voltage is programmable by applying a control voltage at the VINAMP pin (1.5 to 3.2 V from the application microprocessor). The power supply of this regulator is internally connected to AVDD. • VGL: Typically between –11 and –5.4 V at 4 mA. This voltage is generated by an inverted charge pump, which is powered by VOUT. • VGH: Typically between 14.5 and 24.6 V at 4 mA. This voltage is generated by a 2X charge pump, which is powered by VOUT. Linear Regulators The A8601 uses low-dropout linear regulators (LDO) to provide DVDD from VIN, and AVDD from boost output voltage. A representative block diagram is shown in figure 1. Each LDO is protected against output short or over-loading by its own internal OCP limits. Refer to the Fault Conditions section for details. The AVDD circuit monitors the voltage drop across its LDO (item 2 in the Functional Block Diagram). If this voltage drop is less than 2 V, the AVDD circuit sends a control signal to cause the boost voltage to increase. This ensures there is always enough headroom for regulation. VCOM Regulator The VCOM output voltage is determined by the input voltage of VINAMP (see figure 2), according to the following relation: VVCOM = VVINAMP × 1.94 A8601 (1) A8601 From boost output AVDD Regulator From AVDD VCOM Regulator OCP OCP Enable Enable + – VVIN 30 kΩ + – + – VOUT To boost controller Fold back FB2 5 kΩ Rsc Rsc To boost controller Fold back Trimmed resistor divider PMOS + – PMOS AVDD + – 2.4 V 250 Ω Discharge AGND Figure 1. Representative linear regulator (AVDD shown) VCOM 250 Ω VINAMP 100 kΩ Discharge GNDVCOM Figure 2. VCOM regulator Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A8601 Multiple-Output Regulator for Automotive LCD Displays The valid range for VINAMP is between 1.5 and 3.2 V, which gives a VVCOM range of 2.9 to 6.2 V (provided that AVDD is at least 1.5 V higher than VVCOM). Beyond this range, the linearity of VCOM cannot be guaranteed. DVDD 3.3 V The supply voltage of VCOM is taken from AVDD. In order to ensure there is enough headroom, AVDD must be at least 1.5 V higher than VCOM . VINAMP During the startup sequence, VCOM is allowed to ramp up only after VGH has reached 90% of its target voltage. A valid VINAMP must be asserted prior to VCOM ramp up. If VINAMP starts low (< 1.2 V), the A8601 waits as long as 50 ms for a valid VINAMP to be asserted. If VINAMP is not asserted by that time limit, a fault is generated. AVDD >7 V CVCOM 0.1 μF 100 kΩ GNDVCOM If VCOM is not required, the VCOM pin can be left open, but a small output capacitor (approximately 0.1 μF) must be present to prevent oscillation. Make sure to connect VINAMP to a suitable voltage such as DVDD at 3.3 V. The connection to DVDD can be divided as shown in figure 3, according to the AVDD level required. Charge Pumps The A8601 uses a 2X charge pump to generate VGH from boost voltage, and an inverting charge pump to generate VGL . Representative block diagrams are shown in figure 4. A8601 DVDD 3.3 V A8601 AVDD 5V 10 kΩ 40.2 kΩ VINAMP 100 kΩ 2.45 V CVCOM 0.1 μF GNDVCOM The frequency of the charge pumps is the same as the boost switching frequency (or external SYNC frequency) When an external SYNC signal is used, it is internally converted into a clock signal with the same frequency, but at 50% duty cycle. Recommended values of the external flying capacitor, CFLYx , on Figure 3. Configuration for unused VCOM: (upper panel) VAVDD > 7 V, and (lower panel) VAVDD = 5 V. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A8601 Multiple-Output Regulator for Automotive LCD Displays A8601 VGH Regulator From boost output VVIN OCP Enable FB4 5 kΩ + – 55 kΩ 2X Charge Pump D1 CFLY1 CP12 D2 S2 Linear Regulator To boost controller + CP11 S1 2.4 V Switching Sequence: • S1 closed and D1 charges CFLY1 • S2 closed and D2 dumps CFLY1 to VGH 250 Ω VGH Discharge AGND Figure 4A. 2X charge pump for VGH regulator A8601 VGL Regulator From boost output OCP Enable FB3 + – 1X Charge Pump S1 To boost controller Switching Sequence: • S1 closed and D1 charges CFLY2 • S2 closed and D2 dumps CFLY2 to VGL CFLY2 CP21 Linear Regulator S2 + D1 D2 (Si) CP22 1.8 V 250 Ω VGL Discharge AGND Figure 4B. Inverting (negative) charge pump for VGL regulator, AC version A8601 VGL Regulator From boost output OCP Enable FB3 + – Linear Regulator 1X Charge Pump S1 To boost controller Switching Sequence: • S1 closed and D3 charges CFLY2 • S2 closed and D2 dumps CFLY2 to VGL CFLY2 CP21 S2 D1 + D2 (Si) D3 (Si) CP22 1.8 V 250 Ω VGL Discharge AGND Figure 4C. Inverting (negative) charge pump for VGL regulator, AC version full output current (14 mA) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 A8601 Multiple-Output Regulator for Automotive LCD Displays the CPxx pins depends on the switching frequency as shown in the following table; a voltage rating of 25 V is sufficient: Switching Frequency (MHz) Boost Controller The A8601 contains an integrated DMOS switch and PWM controller to drive a boost converter. The input voltage, VVIN , (5 V nominal) is boosted to an intermediate voltage, VOUT , which is the lowest voltage required to keep all outputs within regulation. That is, the effective boost voltage is the highest of the boost requirement of the individual regulators, as illustrated in figure 5. CFLYx (μF) 2 ≈ 0.1 1 0.22 0.350 0.47 For the inverted (negative) charge pump, an external silicon diode is used between the VGL and CP22 pins. However, at high temperatures and switching frequencies (such as 125°C and 2 MHz), the maximum VGL output current is limited to about 8 mA. To achieve the full output current, 14 mA, it is necessary to use two external diodes, as shown in figure 4C. The value of the flying capacitor can be calculates as follows: 1. The equivalent series resistance of the flying capacitor is: ESRFLY2 = 1 / ( fSW × CFLY2 ) (2) 2. Assuming a flying capacitor ripple voltage of 100 mV, and a maximum output current of 20 mA, the series resistance is: For example: assume the output requirements for a certain LCD panel are: VAVDD = 10 V, VVGH = 18.5 V and VVGL = –7 V, then: • AVDD (LDO 2): VOUT ≥ VAVDD + 2 (V) = 12 V • VGH (2X Charge Pump): VOUT ≥ 0.5 × VVGH + 2.4 (V) = 11.65 V • VGL (Inverted Charge Pump): VOUT ≥ –VVGL + 3.6 (V) = 10.6 V In this example, AVDD has the highest requirement, so the intermediate voltage will be regulated at a VOUT of 12 V approximately. However, if VVGH were increased to 23 V, it would be the highest, and then the boost converter would increase the intermediate voltage to 13.9 V to satisfy the charge pump circuit. RFLY2 = 0.1 (V) / 0.02 (A) ≤ 5 Ω 3. Therefore at an fSW of 2 MHz, the required capacitance, CFLY2 , is 0.1 μF. 16 Boost Voltage, VBOOST (V) 14 VBOOST(AVDD) (VAVDD + 2 V) 12 VBOOST(VGH) (VVGH / 2 + 2.4 V) 10 8 6 VBOOST(VGL) ( –VVGL + 3.6 V) 4 2 0 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 Regulated Output (V) Figure 5. Boost voltage requirement with respect to VGL, AVDD, and VGH Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 A8601 Multiple-Output Regulator for Automotive LCD Displays A block diagram of the A8601 boost controller circuit is shown in figure 6. The external COMP capacitor, CCOMP , is typically a 0.1 to 1 μF MLCC. The controller is protected against overvoltage and overcurrent fault conditions. • The OVP threshold, VSW(OVP) , is internally set at approximately 19 V typical. Under normal operating conditions, the boost voltage should always be lower than 16 V (as shown in figure 5), so only in the event of a fault will OVP be tripped (for example: output diode open, or wrong sense resistor values). clock signal, and the boost switching frequency is synchronized to it. If no periodic signal is detected, the bias current flowing through FSET_SYNC pin is used to determine the switching frequency. The bias current is set by an external resistor, RFSET , on the FSET_SYNC pin. The relation between RFSET and switching frequency is given as: RFSET = 10.21 / (fSW – 0.0025) where RFSET is in kΩ and fSW is in MHz. This relationship is charted in figure 7. For example, to get a switching frequency of 2 MHz requires an RFSET of 5.11 kΩ. • The switching current limit, ISW(MAX) , is protected by a pulseby-pulse OCP threshold (1.5 A typical). In the event of a heavy load or during a transient, the SW peak current may reach OCP level momentarily. In this case, the present on-time period is terminated immediately, but no signal is generated on the ¯F¯A¯¯U¯¯L ¯¯T ¯ pin. 2.4 2.2 2.0 1.8 1.6 fsw (MHz) • In the event of a catastrophic failure (such as shorted inductor), the SW current may exceed 150% of the OCP threshold. In this case, the IC is shut down immediately. 1.4 1.2 1.0 0.8 Switching Frequency The boost stage switching frequency, fSW , of the A8601 can be programmed by using an external resistor between the FSET_SYNC pin to GND, or it can be synchronized to an external clock frequency between 350 kHz and 2.25 MHz. During startup, the A8601 senses the FSET_SYNC pin for any external SYNC signal. If periodic logic transitions are detected (Low < 0.8 V or High > 1.8 V), this is evaluated as an external (3) 0.6 0.4 0.2 0 0 5 10 15 RFSET (kΩ) 20 25 30 Figure 7. Switching frequency versus FSET resistance SW A8601 Slope Compensation OVP Oscillator Enable PWM Control DMOS OCP AVDD VGH VGL + – Multi-Input Transconductance Amplifier RSC Gm COMP CCOMP PGND Figure 6. Boost controller circuit Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 A8601 Multiple-Output Regulator for Automotive LCD Displays Suppose the A8601 is started up with a valid external SYNC signal, but the SYNC signal is lost during normal operation. In that case, one of the following happens: During SW off-time, tOFF : • If the external SYNC signal is high impedance (open), the A8601 continues normal operation, at the switching frequency ¯¯T ¯ flag is generated. set by RFSET . No ¯F¯A¯¯U¯¯L therefore: • If the external SYNC signal is low (shorted to ground), the A8601 begins a shutdown sequence, at the switching frequency ¯¯T ¯ pin is pulled set by the internal 1 MHz oscillator. The ¯F¯A¯¯U¯¯L low and the internal error counter is increased by 1. In order to operate in CCM, the minimum inductor current must be greater than zero amperes. This means: Note: If the outcome of the second scenario is not acceptable, the circuit shown in figure 8 can be used to prevent generating a fault when the external SYNC signal goes low. When the circuit is used, after the external SYNC signal goes low, the A8601 will continue to operate normally at the switching frequency set by ¯¯T ¯ flag is generated. RFSET . No ¯F¯A¯¯U¯¯L Continuous Conduction Mode Operation It is often preferable for a boost converter to operate in continuous conduction mode (CCM) in order to reduce switching noise and input ripple. However, whether the converter can operate in CCM or discontinuous conduction mode (DCM) is determined by many parameters, including input/output voltages, output current, switching frequency, and inductor value. This is explained as follows, using simplified basic equations for a boost converter (refer to figure 9): iripple = (VOUT + VD1 – VVIN ) / L × tOFF (5) = (VOUT + VD1 – VVIN ) / L × T × (1 – D) (7) VOUT + VD1 = VVIN × 1 / (1 – D) (8) iSW(min) = iSW(av) – iripple / 2 ≥ 0, or (9) iripple ≤ 2 × iSW(av) Average input current is directly related to the input power and voltage, as given by: iSW(av) = PVIN / VVIN = (POUT / η ) / VVIN (10) where η is the efficiency of the boost converter (typically around 80%). Ripple current is determined by inductance, period, and duty cycle, as given by: iripple = VVIN / L × T × D (11) where D is 1 – VVIN /(VOUT + VD1) from equation 8. L D1 VOUT CVIN COUT VIN SW OUT A8601 During SW on-time, tON : DMOS iripple = VVIN / L × tON = VVIN / L × T × D (4) (5) where T is the switching period of the boost converter and D is the duty cycle, tON / T. PGND VSW VOUT+VD 0 External synchronization signal FSET_SYNC A8601 220 pF Schottky barrier diode RFSET 10.2 kΩ t Switching Period, T iSW tON tOFF iSW(max) iSW(av) iripple iSW(min) t Figure 8. Low FSET_SYNC signal fault counteraction circuit Figure 9. Continuous and discontinuous conduction mode factors Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 A8601 Multiple-Output Regulator for Automotive LCD Displays For a given VVIN and VOUT , the duty cycle is fixed. Furthermore, for a given output power, the average input current also is fixed. Therefore the only way to reduce ripple current is either to switch at a higher frequency (a shorter period) or to use a larger inductance. For example, assume fSW is 2 MHz (T = 500 ns), tON(MIN) is 95 ns, and tOFF(MIN) is 75 ns. Then: Figure 10 shows that the minimum inductance required to ensure CCM operation increases with higher output voltage (hence also with higher duty cycle), for a boost regulator with fixed input voltage and output power. Note that the chart is calculated at an fSW of 1 MHz. If the frequency is reduced by half, to 500 kHz, the inductance requirement is doubled. Further, assume VVIN is 4.0 to 5.5 V and VD1 is 0.4 V. Then the possible VOUT is between 6.4 and 20.7 V. This is wider than the range required by individual regulators under all possible output combinations. Therefore the minimum on-time and off-time are not limiting factors in output regulation. When selecting the boost inductor, pay attention to the following parameters: • Inductance. This usually determines whether the boost converter operates in DCM or CCM. Refer to figure 10, or calculate minimum required inductance using the equations provided. • DCR. Lower resistance is preferred to reduce conduction loss. • Saturation current. ISAT should be greater than 1.5 A, and preferably 2 A. • Heating current. IHEATING should be greater than 1.5 ARMS • Physical size. Smaller size typically means lower ISAT and higher DCR. The minimum SW on-time and off-time determine the range of duty cycle, and hence the range of boost output voltage. They do not affect whether the converter operates in CCM or DCM. D(min) = tON(MIN) / T = 95 (ns)/ 500 (ns) = 19% D(max) = 1 – tOFF(MIN) / T = 1 – 75 (ns)/ 500 (ns) = 85% VOUT(min) = VVIN(max) × 1/(1 – D(min)) –VD1 = 6.4 V VOUT(max) = VVIN(min) × 1/(1 – D(max)) –VD1 = 26.7 V Input Disconnect Switch The A8601 has a gate driver for an external PMOS, in order to provide input disconnect protection function (figure11). During normal startup, the PMOS is turned on gradually to avoid a large inrush current. In the event there is a direct short at the boost stage (either SW or OUT shorted to GND), a high input current would cause the PMOS to turn off. See the Fault Conditions section for details. The input disconnect current threshold is calculated by: IVIN(MAX) = VINS(TH) / RINS (12) where VINS(TH) = 100 mV typical. 9 8 POUT = 1 W POUT = 1.33 W 6 L D VOUT CGS (optional) VIN 5 INS GATE SW OUT COUT A8601 POUT = 2 W 4 VIN 3.5 V + – 100 mV + – 3 + – Inductance (μH) RINS VS 7 + – Gate_OK 2 Overcurrent 1 Fault 100 μA 0 10 11 12 13 14 Output Voltage (V) 15 16 Figure 10. Minimum inductance for CCM as a function of output voltage (at VVIN = 5.5 V and fSW = 1 MHz) Figure 11. Input disconnect switch circuit Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 A8601 Multiple-Output Regulator for Automotive LCD Displays Under normal operation, the input current is protected by the cycle-by-cycle boost switch current limit, ISW(MAX) ,1.5 A (typ). Only in the event of a direct short at the boost output (SW pin) will the input disconnect switch be activated. Therefore the input disconnect current threshold should be set slightly higher than the switch current limit; for example, choose an RINS of 0.047 Ω to set an IVIN(MAX) of 2 A approximately. During a normal power-up sequence, as soon as EN1 reaches high, the A8601 begins pulling the GATE pin low by a 100 μA current. How quickly the external PMOS turns on depends on the gate capacitance CGS . If the gate capacitance is very low, the inrush current may momentarily exceed 2 A and trip the input disconnect protection. In this case, an external CGS capacitor may be added to slow down the PMOS turn-on. A typical value of 4.7 nF should be sufficient in most cases. When selecting the external PMOS, check the following parameters: • Drain-source breakdown voltage, V(BR)VDSS , should exceed –20 V • Gate threshold voltage should be fully conducting at VGS = –4 V, and cut-off at –1 V • RDS(on) is rated at VGS = –4.5 V or similar, not at –10 V; derate for higher temperatures FAULT Conditions The A8601 has extensive fault detection mechanisms, to protect against all perceivable faults at the IC level (pin open, pin short to GND, pin short to neighboring pins, and so forth) and at the system level (external component open/short, component value changes from –50% to +100%, and so forth). All feedback pins (FB1, FB2, FB3, and FB4) are monitored for overvoltage and undervoltage faults during normal operation. VDVDD, VAVDD VVCOM Target Target In case of an output short, or an open/short in the sense resistor network, the magnitude of the sensed voltage may make a sudden change that is either +20% over, or –20% under the target voltage. This will trigger the OVP/UVP fault and force the A8601 to shut down. OVP/UVP detections are disabled during the startup sequence. If any output fails to reach 90% of its target voltage within a timeout period, tSS(TO) (50 ms typical), a fault is generated and then the A8601 shuts down. Each regulator output (DVDD, AVDD, VGH, VGL and VCOM) is protected by its own independent overcurrent limit. When an output current exceeds its limit, the corresponding regulator goes into overcurrent protection mode to protect itself from damage. See figure 11 for illustrations of the protection characteristics. If the overcurrent condition persists for 50 ms, all regulators are turned off following the normal shutdown sequence. The same applies when there is an overvoltage fault detected at any of the feedback pins, except that the offending regulator is turned off immediately. The other outputs then shut down following normal sequence. In general, if a fault is detected, the A8601 halts operation and ¯¯T ¯ pin low. It then attempts to restart operation pulls the ¯F¯A¯¯U¯¯L after a delay, tRESTART , of 100 ms typical. Internally there is a Fault counter that keeps track of how many times any fault has occurred. If the Fault counter reaches eight, the A8601 is completely shut down. The Fault counter is cleared by a completed shutdown sequence with EN1 = EN2 = low, or by a power reset (VVIN drops below UVLO). During startup, all regulators go through a soft-start process, to prevent excessive inrush current from tripping OCP. The same applies to the turn-on of the external input disconnect PMOS. VVGH, VVGL Target 3V 0 0 0 33 100 Output Current, IDVDD, IAVDD (%) 0 0 33 100 Output Current, IVCOM (%) 0 100 Output Current, IVGH, IVGL (%) Figure 11. Overcurrent protection characteristics for DVDD, AVDD, VCOM, VGH, and VGL Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22 A8601 Multiple-Output Regulator for Automotive LCD Displays Pre-Output Fault Detection When EN1 turns on the A8601, a startup sequence is followed before the regulators are powered up. The sequence checks for extreme conditions and proceeds as described in table 1. General Fault Detection The faults described in table 2 are continuously monitored, whether during startup, normal operation, or shutdown. Table 1. Pre-Output Fault Detection Sequence Step Number Step Description Fault Tripped? Fault Description 1 Check VIN UVLO A8601 remains powered-down until VVIN is above VUVLO. No 2 Power-up internal rail A8601 initializes. No 3 Check internal rail UVLO BIAS charges internal rail indefinitely, until VBIAS is above UVLO. No 4 Check all FBx pins for short to GND Any FBx pin is detected as shorted after tSS(TO). Yes 5 Turn on input disconnect Pull-down on GATE pin does not reach < VVIN – 3.5 V after tSS(TO). Yes 6 Turn on DVDD FB1 pin does not reach >90% of target (2.4 V) after tSS(TO). Yes 7 Turn on AVDD FB2 pin does not reach >90% of target (2.4 V) after tSS(TO). Yes 8 Turn on VGL FB3 pin does not reach >90% of target (–1.8 V) after tSS(TO). Yes 9 Turn on VGH FB4 pin does not reach >90% of target (2.4 V) after tSS(TO). Yes 10 Turn on VCOM VCOM pin does not reach >90% of target (VVINAMP × AVCOM ) after tSS(TO). Yes Table 2. General Fault Detection Fault Description A8601 Response to Fault Fault Tripped? TTSD exceeded Shutdown using shutdown sequence. Fault counter increased by one, retry after tRESET . ¯¯A¯U¯¯L¯¯T ¯ set during tRESET Yes; ¯F VFB1, VFB2, VFB3, or VFB4 20% under target Shutdown using shutdown sequence. Fault counter increased by one, retry after tRESET . ¯¯A¯U¯¯L¯¯T ¯ set during tRESET Yes; ¯F VFB1, VFB2, VFB3, or VFB4 20% over target Over-target regulator rail shut down without shutdown sequence. Other regulator rails shut down using shutdown sequence. Fault counter increased by one, retry after tRESET . ¯¯A¯U¯¯L¯¯T ¯ set during tRESET Yes; ¯F VUVLO reached Shutdown without using shutdown sequence. Fault counter reset to 0, retry after tRESET . No BIAS UVLO Shutdown without using shutdown sequence. Fault counter reset to 0, retry after tRESET . No Overcurrent limit for iDVDD, iAVDD, iVCOM, iVGH, or iVGL exceeded Over-limit regulator rail goes into current fold-back or current limit. Shutdown using shutdown sequence after tOCP(TO) . Fault counter increased by one, retry after tRESET . ¯¯A¯U¯¯L¯¯T ¯ set during tRESET Yes; ¯F VINS(TRIP) exceeded Shutdown without using shutdown sequence. Fault counter increased by one, retry after tRESET . ¯¯A¯U¯¯L¯¯T ¯ set during tRESET Yes; ¯F VSW(OVP) exceeded Shutdown without using shutdown sequence. Fault counter increased by one, retry after tRESET . ¯¯A¯U¯¯L¯¯T ¯ set during tRESET Yes; ¯F ISW(MAX) × 150% of OCP limit exceeded Shutdown without using shutdown sequence. Fault counter increased by one, retry after tRESET . ¯¯A¯U¯¯L¯¯T ¯ set during tRESET Yes; ¯F Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 23 A8601 Multiple-Output Regulator for Automotive LCD Displays Application Information Output Voltage Selection Each output voltage of DVDD, AVDD, VGH, or VGL is selected using a simple voltage-sensing (resistor divider) network, as shown in figure 12. external equivalent resistance, that is, the parallel resistance of R1 and R2, as follows: Pin Parallel Resistance (kΩ) FB1 (DVDD) 10 ± 1 FB2 (AVDD) 25 ± 1 FB3 (VGL) 50 ± 2.5 FB4 (VGH) 50 ± 2.5 In actual implementation there is a small bias current that is flowing out from each positive FBx pin, and the direction is reversed for any negative FBx pin. This is necessary to detect any pin-open fault at an FBx pin. As shown in figure 13, a common bias current is injected into both the (+) and the (–) terminals of the operational-amplifier. Due to the principal of superposition, the same set of equations as in figure 1 can be used to determine values for R1 and R2 in figure 13. • To reduce the mismatch error of the sensing network, consider using 0.5% or 0.2% resistors for the resistor divider. VFB is the regulation voltage for the feedback pins, and it is specified as 2.40 V for FB1 (DVDD), FB2 (AVDD), and FB4 (VGH). For FB3 it is specified as –1.80 V. The following considerations affect voltage selection: • To reduce effects of switching noises coupled into the FBx pins, add an external filter capacitor (typically a 47 pF MLCC) between the FBx pin and GND. The capacitor should be placed as close as possible to the respective FBx pin. • To cancel the offset error introduced by input bias currents, and to assure regulation loop stability, it is necessary to keep the Table 3 provides some examples of voltage sensing network component values, using E96 1% resistors. VOUT VOUT A8601 R1 A8601 5 kΩ FBx R2 30 kΩ VREF + – Output voltage sensing network VOUT = VFB × (R1 + R2) / R2 where: VFB = VREF R1 FBx R2 AGND RZ 25 kΩ A8601 5 kΩ 30 kΩ VREF AGND Output voltage sensing network VOUT = VFB × (R1 + R2) / R2 where: iBIAS = 0 A AGND A8601 VREF FBx VBIAS iBIAS iBIAS 5 kΩ + – 30 kΩ VREF + – Equivalent Circuit RZ = R1 × R2 / (R1 + R2) VREF FBx RZ 25 kΩ Combining the two equations: R1 = RZ × VOUT / VREF VBIAS iBIAS iBIAS 5 kΩ + – 30 kΩ VREF AGND Equivalent Circuit RZ = R1 × R2 / (R1 + R2) Based on the principle of superposition, the same equations can be used where iBIAS > 0 A: R1 = RZ × VOUT / VREF R2 = R1 × VREF / (VOUT – VREF ) R2 = R1 × VREF / (VOUT – VREF ) where: RZ is 25 kΩ and VREF is 2.4 V for AVDD where: RZ is 25 kΩ and VREF is 2.4 V for AVDD Figure 12. The output voltage sensing network and the equivalent circuit Figure 13. The figure 12 circuits with the same bias current injected into both inputs of the operational amplifier Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 24 A8601 Multiple-Output Regulator for Automotive LCD Displays Output Capacitance The boost stage requires an output capacitor, COUT . Use an MLCC with a capacitance of approximately 4.7 to 10 μF and a voltage rating of 25 V. The temperature rating should be either X5R or X7R. Do not use Y5V, which has a very large variation with temperature. Another point to note is the capacitance of MLCC is specified at a 0 V bias. To account for the degradation when the rated DC voltage is applied to an MLCC, the capacitance should be derated by as much as 50%. The derating factor is typically less if the capacitor is physically larger (for example, choose a 1206 package instead of an 0805) and has a higher voltage rating (for example, 50 V instead of 25 V). AVDD Current, IAVDD (mA) 500 di = 400 mA 100 0 To ensure system stability, each output (DVDD, AVDD, VGL, VGH, and VCOM) is required to have an external MLCC with a minimum output capacitance of 2 ±0.1 μF. However, greater capacitance may be required to satisfy transient current requirements. This is illustrated in figure 14. The AVDD load current makes a step from 100 mA (steady state current) to 500 mA, for a duration of 3.2 μs only. Because the linear regulator for AVDD takes a finite time to respond to this load change, the voltage dip is determined primarily by the output capacitance, CAVDD . t dt = 3.2 μs Period = 31.8 μs AVDD Voltage Target dV1 dV2 dV1 = di ×ESR dV2 = di ×dt / CAVDD The corresponding voltage step, dV1, is determined by the ESR of the output capacitor. When using an MLCC with very low ESR (several mΩ), this drop is only several mV and can be omitted. t Figure 14. AVDD output voltage transient caused by a step change in load current Table 3. Examples of Sensing Network Component Values Goal Output Values Output [Pin] VFBx (V) DVDD [FB1] Calculated Resistor Divider Values RZ (kΩ) VOUT (V) R1 (kΩ) R2 (kΩ) 2.4 10 3.3 13.75 36.67 AVDD [FB2] 2.4 25 VGH [FB4] 2.4 50 VGL [FB3] –1.8 50 Actual Resistor Divider Values R1 (kΩ) 13.7 36.5 RZ (kΩ) 9.96 VOUT (V) VOUT Resistor Divider Error (%) 3.3 0.02 7 72.92 38.04 38.3 25.14 6.99 –0.19 12.8 133.33 30.77 133 30.9 25.07 12.73 –0.55 14.5 302.08 59.92 300 59 49.3 14.6 0.71 24.6 512.5 55.41 511 54.9 49.57 24.74 0.56 –5.4 –11 73.2 R2 (kΩ) Calculated Output Values 150 75 150 75 50 305.56 59.78 309 60.4 50.52 –5.4 0.00 –11.01 0.08 Note: Use of series E96 1% resistors assumed. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 25 A8601 Multiple-Output Regulator for Automotive LCD Displays A8601 output regulators in figure 15. Higher VOUT levels result in excessive power loss and may trigger OVP at the SW pin. The second voltage step, dV2, is determined by the output capacitance. For example, assume CAVDD = 20 μF, then: dV2 = 0.4 (A) × 3.2 (μs) / 20 (μF) = 64 mV Operating with Separate VIN and Boost Supplies If necessary, the A8601 can be powered by a 5 V LDO for VIN, while the boost stage can be powered by a different supply such as 3.3 V. This is illustrated in figure 15. Thermal Analysis The thermal resistance, RθJA , of the TSSOP-28 thermally enhanced package is 28°C/W. For long term reliability, the package junction temperature should be kept at 150°C or below. Assuming a maximum ambient temperature of 85°C, the power dissipation budget, PD(max), is: The LDO for VIN should have an output voltage of 5 V ±10%. The LDO supply current is the sum of the A8601 bias current (approximately 6 mA at 2 MHz) and the DVDD output current. The boost supply voltage is independent from the VIN voltage. A reasonable range for the boost supply is between 3.3 and 10 V. The boost supply current is determined by the output power of boost stage, as outlined in the Thermal Analysis section. The boost output voltage, VOUT , is always higher than its input, VBOOSTS. Therefore it is necessary to keep the boost supply voltage below a certain level. This can be determined for a boost converter as follows: VOUT = VBOOSTS / (1 – D) PD(max) = (TJ(max) – TA(max)) / RθJA = (150 (°C) – 85 (°C)) / 28 (°C/W) = 2.3 W The power losses of the IC come from two main contributors, the boost stage and the linear regulators. These losses are calculated separately, then summed, as follows. To estimate the dissipation of the boost stage, calculate and sum the losses due to switching losses, PSW , and conduction losses in the switch, PCOND: PD(BOOST) = PCOND + PSW Assume a boost PWM frequency of 2 MHz (period = 500 ns). The A8601 minimum on-time, tON(MIN) , is 95 ns worst-case. That results in a minimum PWM duty cycle of 19%. LDO VBOOSTS 3.3 to 10 V POUT(max) = VOUT(max) × IOUT (max) (16) IOUT = IAVDD + IVCOM + IVGL + 2 × IVGH (17) Based on the average load current waveforms during normal operation (see Characteristic Performance section), the average output current for the boost stage is estimated to be: IOUT = 140 (mA) +18.3 (mA) + 8.9 (mA) + (2 × 7.9 (mA)) For a VBOOSTS of 12 V, and a D of 0.19, the calculated VOUT would be 14.8 V. This is higher than the 14 V required by the 5V (15) 1. Estimate the maximum output power for boost stage: (13) where D is the duty cycle. VINS 8 to 16 V (14) ≈ 183 mA L VOUT ≈ 14 V D1 COUT VIN Enable EN1 INS A8601 SW OUT AVDD 12 V EN2 VGH 23 V DVDD VGL –7 V FB1 VCOM ≈4.2 V Figure 15. Typical dual supply application Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 26 A8601 Multiple-Output Regulator for Automotive LCD Displays So at a maximum VOUT of 16 V, the maximum POUT is: is the regulator for VGL, LDO4 is the regulator for VGH, and LDO5 is the regulator for VCOM. POUT(max) = 16(V) × 0.183 (A) = 3 W 2. Estimate the maximum input current: IVIN = PVIN / VVIN (18) PVIN = POUT / η (19) Estimate the maximum output power for each regulator as follows, using the same worst-case values as for the boost stage calculations: 1. For DVDD: where η is efficiency (%). Substituting into equation 10: PLDO1 = (VVIN – VDVDD) × IDVDD IVIN = (3 (W) / 0.85) / 4 (V) = 0.88 A. Substituting into equation 17: 3. Estimate conduction loss for the internal switch: PCOND = I2VIN × RDS(on) × D D = 1 – VVIN / (VOUT + VD1) (20) (21) where VD1 is the forward voltage drop of the external boost diode. Subsituting into equation 20: PLDO1 = (4 (V) – 3.3 (V)) × 20 (mA) = 0.03 W 2. For AVDD (which is usually the largest contributor of power loss): PCOND = (0.88 (A))2 × 0.7 (Ω) × [1 – 4 (V) / (16(V) + 0.4 (V))] = 0.78 × 0.7 × 0.756 = 0.41 W 4. Estimate switching loss for the internal switch: (22) where tr is the rise time, and tf the fall time, of VSW . Subtituting into equation 14: PSW = 0.88 (A) × 16.4 (V) × (10 (ns) + 10 (ns)) × 2 (MHz) / 2 = 0.29 W (23) ILDO2 = IAVDD + IVCOM (27) PLDO2 = (16 (V) – 10 (V)) × (140 (mA) + 18.3 (mA)) = 0.95 W 3. For VGL (magnitude of VGL): PLDO3 = (VOUT – |VVGL|) × |IVGL| (28) Substituting into equation 20: PLDO3 = (16 (V) – 12 (V)) × 8.9 (mA) = 0.036 W 4. For VGH: (29) Substituting into equation 29: PLDO4 = (2 × 16 (V) – (18.5 (V)) × 7.9 (mA) = 0.107 W Substituting into equation 7: 5. For VCOM: PD(BOOST) = PCOND + PSW PLDO5 = (VAVDD – VVCOM) × IVCOM = 0.41 (W) + 0.29 (W) = 0.70 W (30) Substituting into equation 30: Therefore a total of 0.70W is dissipated on the boost stage. Note that this analysis is done under the worst-case combination (maximum VOUT , minimum VVIN , maximum fSW , and so forth). Under typical operating conditions, the power loss is lower. The linear regulator power dissipations are the sum of the individual linear regulators: PD(LINREG) = PLDO1 + PLDO2 + PLDO3 + PLDO4 + PLDO5 (26) PLDO4 = (2 × VOUT – VVGH) × IVGH Assuming ISW equals IVIN and VSW = VOUT + VD1 PLDO2 = (VOUT – VAVDD) × ILDO2 Substituting into equation 18: where RDS(on) is 0.5 Ω typical, plus 40% of typical for temperature compensation at 125°C. PSW = ISW × VSW × ( tr + tf ) × fSW / 2 (25) (24) Referring to the Functional Block Diagram notes, LDO1 is the regulator for DVDD, LDO2 is the regulator for AVDD, LDO3 PLDO5 = (10 (V) – (4.5 (V)) × 18.3 (mA) = 0.101 W 6. Finally, the IC consumes a bias current of approximately 6 mA from VIN when EN1 and EN2 are both high. This adds power consumption of approximately 0.024 W at minimum VVIN. Substituting into equation 16, including the bias currrent factor: PD(LINREG) = 0.03 (W) + 0.95 (W) + 0.036 (W) + 0.107 (W)+ 0.101 (W)+ 0.024 (W) = 1.25 W Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 27 A8601 Multiple-Output Regulator for Automotive LCD Displays Therefore the sum of the power dissipations for all of the linear regulators is 1.25 W. The total power dissipation if the IC is then the sum of the boost stage and the linear regulators: 1.95 W (0.70 W plus 1.25 W). This corresponds to a temperature rise of 60°C. At an ambient temperature of 85°C, the junction temperature could reach 140°C under the above worst-case conditions. Component Selection Recommendations Final component selection is dependent on many system parameters, such as switching frequency, output power, and PCB area. The following recommendations should be used as a starting point only. Table 4. External Component Recommendations Component Manufacturer Fairchild FDS6675 V(BR)VDSS V(BR)VDSS V(BR)VDSS Vishay IHLP2020BZER3R3M01 L = 3.3 μH, DCR = 79 mΩ (typ), IHEATING = 3.3 A, 5.2 × 5.5 × 2 mm TOKO D63CB #A916CY-6R2M L = 6.2 μH, DCR = 29 mΩ (typ), ISAT = 1.84 A, 6.2 × 6.3 × 3.5 mm Renesas uPA1830 External PMOS Boost Inductor Description Toshiba TPC8125 = –30 V (min), VGS(off) = –2.0 V (typ), RDS(on) = 28 mΩ (max) at Vgs = –4 V, SOP-8 = –30 V (min), Vth = –2.0 V (max), RDS(on) = 17 mΩ (max) at Vgs = –4.5 V, SOP-8 = –30 V (min), VGS(th) = –3 V (max), RDS(on) = 20 mV (max) at VGS = –4.5 V, SOP-8 TDK SLF6045T-100M1R6-3PF L = 10 μH, DCR = 39 mΩ (typ), ISAT = 1.6 A, 6 × 6 × 4.5 mm Sumida CDR7D28MNNP-15Ø N L = 15 μH, DCR = 65 mΩ (typ), ISAT = 2.1 A at 20°C, 7.3 × 7.3 × 3 mm Output Diode ON-Semi MBR130 30 V, 1 A, Vf = 0.47 V (typ) at If = 1 A, SOD-123 Boost Output Capacitor Murata GRM31CR61E106KA12L 10 μF, 25 V, X5R, 1206 1N4148W Switching diode, 100 V, 0.15 A, CT = 2 pF, SOD-123 Rohm DAN217 Dual Switching diode, 80 V, 0.1 A, CT = 3.5 pF, SOT-346 Negative Charge Pump External Diode Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 28 A8601 Multiple-Output Regulator for Automotive LCD Displays I/O pin Equivalent Circuit Diagrams 1 2 GATE 3 INS VVIN ≈9.5 V AGND ≈9.5 V AGND 4 5 GATE VVIN ≈9.5 V 2 kΩ ≈12 V AGND 7 VBIAS VINAMP 9 10 kΩ VAVDD ≈9.5 V AGND 10 GNDVCOM 2 kΩ AGND VBIAS AGND 11 12 VVIN BIAS 12 kΩ FAULT 40 kΩ ≈9.5 V ≈9.5 V AGND AGND 13 AGND 14 10 kΩ ≈6.5 V AGND 1.5 kΩ AGND 8 VCOM ≈9.5 V VBIAS COMP AGND EN1 6 FB1 ≈9.5 V ≈9.5 V AGND VBIAS 2Ω ≈9.5 V VVIN 300 kΩ ≈9.5 V FSET _SYNC VIN VVIN 100 kΩ 15 10 kΩ EN2 90 kΩ ≈9.5 V ≈6.5 V AGND Main ESD ring substrate tie 90 kΩ AGND Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 29 A8601 Multiple-Output Regulator for Automotive LCD Displays 16 17 VBIAS 18 19 VGL CP22 FB3 20 kΩ 50 kΩ ≈20 V 80 kΩ CP21 ≈20 V AGND ≈20 V VVGL AGND AGND VOUT ≈20 V AGND 200 kΩ VOUT 20 21 VVGH 22 CP12 23 CP11 VBIAS VOUT VGH FB4 ≈30 V 2 kΩ 240 kΩ AGND AGND VOUT AGND 24 ≈30 V 25 26 VOUT VBIAS VOUT AGND OUT FB2 AVDD ≈26 V 2 kΩ AGND AGND AGND 27 VBIAS 28 SW 1 pF PGND ≈50 V 125 kΩ AGND PGND Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 30 A8601 Multiple-Output Regulator for Automotive LCD Displays Package LP, 28-Pin TSSOP with Exposed Thermal Pad 0.45 9.70±0.10 28 0.65 28 8º 0º 0.20 0.09 1.65 B 3 NOM 4.40±0.10 3.00 6.40±0.20 6.10 0.60 ±0.15 A 1 2 1.00 REF 5.08 NOM 0.25 BSC Branded Face 28X SEATING PLANE 0.10 C 0.30 0.19 0.65 BSC 1 2 5.00 SEATING PLANE C GAUGE PLANE C PCB Layout Reference View For Reference Only; not for tooling use (reference MO-153 AET) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 1.20 MAX 0.15 0.00 A Terminal #1 mark area B Exposed thermal pad (bottom surface); dimensions may vary with device C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 31 A8601 Multiple-Output Regulator for Automotive LCD Displays Revision History Revision Revision Date Rev. 1 September 27, 2012 Description of Revision Change in ISW(MAX) and tOFF(MIN) Copyright ©2012, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 32