INTEGRATED CIRCUITS DATA SHEET 74ALVCH16652 16-bit transceiver/register with dual enable; 3-state Product specification Supersedes data of 1998 Aug 31 File under Integrated Circuits, IC24 1999 Nov 23 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 Depending on the select inputs nSAB and nSBA data can directly go from input to output (real-time mode) or data can be controlled by the clock (storage mode), when OE inputs permit this operating mode. FEATURES • In accordance with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTE flow-through pin-out architecture The output enable inputs nOEAB and nOEBA determine the operation mode of the transceiver. When nOEAB is LOW, no data transmission from nBn to nAn is possible and when nOEBA is HIGH, no data transmission from nBn to nAn is possible. • Low inductance, multiple supply and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • All data inputs have bus hold When nSAB and nSBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling nOEAB and nOEBA. In this configuration each output reinforces its input. • Output drive capability 50 Ω transmission lines at 85 °C • Current drive ±24 mA at 3.0 V. DESCRIPTION Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and nSBA) or output enable (nOEAB and nOEBA) control inputs. QUICK REFERENCE DATA Ground = 0; Tamb = 25 °C; tr = tf = 2.5 ns. SYMBOL PARAMETER tPHL/tPLH propagation delay nAn, nBn to nBn, nAn fmax CI CPD power dissipation capacitance per latch CONDITIONS CL = 50 pF; VCC = 3.3 V UNIT 2.6 ns maximum clock frequency 350 MHz input capacitance 4.0 pF outputs enabled 22 pF outputs disabled 4.0 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in Volts; Σ (CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. 1999 Nov 23 TYPICAL 2 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 FUNCTION TABLE See note 1. INPUTS DATA I/O FUNCTION nOEAB nOEBA nCPAB nCPBA nSAB nSBA nA0 to nA7 nB0 to nB7 L L H H H or L ↑ H or L ↑ X X X X input input X H H H ↑ ↑ H or L ↑ X L X X input input unspecified(2) store A, hold B output store A in both registers L L X L H or L ↑ ↑ ↑ X X X L unspecified(2) input output input hold A, store B store B in both registers L L L L X X X H or L X X L H output input real-time B data to A bus stored B data to A bus H H H H X H or L X X L H X X input output real-time A data to B bus stored A data to B bus H L H or L H or L H H output output isolation store A and B data stored A data to B bus and stored B data to A bus Notes 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH. 2. The data output functions may be enabled or disabled by various signals at the nOEAB and nOEBA inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs. 1999 Nov 23 3 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 ORDERING INFORMATION PACKAGE OUTSIDE NORTH AMERICA 74ALVCH16652DGG NORTH AMERICA ACH16652 DGG TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +85 °C 56 TSSOP plastic SOT364-1 PINNING PIN SYMBOL DESCRIPTION 1 and 28 1OEAB, 2OEAB output enable A-to-B 2 and 27 1CPAB, 2CPAB clock input A-to-B 3 and 26 1SAB, 2SAB select input A-to-B 5, 6, 8, 9, 10, 12, 13 and 14 1A0 to 1A7 ‘1A’ data inputs/outputs 4, 11, 18, 25, 32, 39, 46 and 53 GND ground (0 V) 7, 22, 35, 50 VCC positive supply voltage 15, 16, 17, 19, 20, 21, 23 and 24 2A0 to 2A7 ‘2A’ data inputs/outputs 29 and 56 2OEBA, 1OEBA output enable B-to-A 30 and 55 2CPBA, 1CPBA clock input B-to-A 31 and 54 2SBA, 1SBA select input B-to-A 33, 34, 36, 37, 38, 40, 41 and 42 2B0 to 2B7 ‘2B’ data inputs/outputs 43, 44, 45, 47, 48, 49, 51 and 52 1B7 to 1B0 ‘1B’ data inputs/outputs 1999 Nov 23 4 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 handbook, halfpage 1OEAB 1 56 1OEBA 1CPAB 2 55 1CPBA 1SAB 3 54 1SBA GND 4 53 GND 1A0 5 52 1B0 1A1 6 51 1B1 VCC 7 50 VCC 1A2 8 49 1B2 1A3 9 48 1B3 1A4 10 47 1B4 GND 11 46 GND 1A5 12 45 1B5 1A6 13 44 1B6 handbook, halfpage data input Fig.2 Bus hold circuit. 16652 2A0 15 42 2B0 2A1 16 41 2B1 2A2 17 40 2B2 GND 18 39 GND 2A3 19 38 2B3 2A4 20 37 2B4 2A5 21 36 2B5 VCC 22 35 VCC 2A6 23 34 2B6 2A7 24 33 2B7 GND 25 32 GND 2SAB 26 31 2SBA 2CPAB 27 30 2CPBA 2OEAB 28 29 2OEBA MNA315 Fig.1 Pin configuration. 1999 Nov 23 to internal circuit MNA318 43 1B7 1A7 14 VCC 5 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 56 1 55 54 2 3 handbook, full pagewidth 5 6 29 28 30 31 27 26 EN1[BA] EN2 [AB] C3 G4 C5 G6 ≥1 1 4 5D 6 1 6 3D 52 EN7 [BA] EN8 [AB] C9 G10 C11 G12 ≥1 7 15 4 1 ≥1 2 74ALVCH16652 11D 12 1 12 10 9D 42 10 1 ≥1 8 51 16 8 49 17 40 41 9 48 19 38 10 47 20 37 12 45 21 36 13 44 23 34 14 43 24 33 MNA317 Fig.3 IEC logic symbol. handbook, full pagewidth 5 6 8 9 10 12 13 14 56 1 3 54 2 55 1A0 1B0 1A1 1B1 1A2 1B2 1A3 1B3 1A4 1B4 1A5 1B5 1A6 1B6 1A7 1B7 52 15 51 16 49 17 48 19 47 20 45 21 44 23 43 24 1OEBA 29 1OEAB 28 1SAB 26 1SBA 31 1CPAB 27 1CPBA 30 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 6 42 2B2 2B3 40 2B4 2B5 2B6 2B7 2OEBA 2OEAB 2SAB 2SBA 2CPAB 2CPBA Fig.4 Logic symbol. 1999 Nov 23 2B0 2B1 MNA316 41 38 37 36 34 33 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 handbook, full pagewidth nOEBA nOEAB nSBA nCPBA nSAB nCPAB VCC S Y D1 nAn MUX D2 Q D FFn CP VCC S D1 Y MUX D Q nBn D2 FFn CP 8 IDENTICAL CHANNELS MNA319 Fig.5 Logic diagram (one section). 1999 Nov 23 7 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC supply voltage for maximum speed performance CL = 30 pF 2.3 2.5 2.7 V for maximum speed performance CL = 50 pF 3.0 3.3 3.6 V 1.2 2.4 3.6 V VI DC input voltage for low-voltage applications 0 − VCC V VO DC output voltage 0 − VCC V Tamb operating ambient temperature in free air −40 − +85 °C tr, tf input rise and fall times VCC = 2.3 to 3.0 V 0 − 20 ns/V VCC = 3.0 to 3.6 V 0 − 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +4.6 V IIK DC input diode current VI < 0 − −50 mA VI DC input voltage note 1 −0.5 +4.6 V mA IOK DC output diode current VO > VCC or VO < 0 − ±50 VO DC output voltage note 1 −0.5 VCC + 0.5 V IO DC output source or sink current VO = 0 to VCC − ±50 mA ICC, IGND DC VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation 600 mW for temperature range: −40 to +125 °C; − note 2 Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 55 °C the value of Ptot derates linearly with 8 mW/K. 1999 Nov 23 8 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 TO +85 °C TEST CONDITIONS SYMBOL PARAMETER VI (V) VIH HIGH-level input voltage VIL LOW-level input voltage VOH VOL HIGH-level output voltage LOW-level output voltage VCC (V) VIH or VIL VIH or VIL TYP.(1) MIN. UNIT MAX. 1.2 − 2.7 to 3.6 2.0 1.5 − 2.3 to 2.7 − 1.2 0.7 2.7 to 3.6 − 1.5 0.8 2.3 to 2.7 1.7 IO = −100 µA 2.3 to 3.6 VCC − 0.2 VCC IO = −6 mA 2.3 VCC − 0.3 VCC − 0.08 − − IO = −12 mA 2.3 VCC − 0.6 VCC − 0.26 − IO = −12 mA 2.7 VCC − 0.5 VCC − 0.14 − IO = −12 mA 3.0 VCC − 0.6 VCC − 0.09 − IO = −24 mA 3.0 VCC − 1.0 VCC − 0.28 − IO = 100 µA 2.3 to 3.6 − GND 0.20 IO = 6 mA 2.3 − 0.07 0.40 IO = 12 mA 2.3 − 0.15 0.70 IO = 12 mA 2.7 − 0.14 0.40 IO = 24 mA 3.0 − V V V V 0.27 0.55 2.3 to 3.6 − 0.1 5 µA VO = VCC or GND 2.3 to 3.6 − 0.1 10 µA IO = 0 2.3 to 3.6 − 0.2 40 µA IO = 0 2.3 to 3.6 − 150 750 µA 0.7(2) 2.3(2) 45 − − µA 0.8(2) 3.0(2) 75 150 − 1.7(2) 2.3(2) −45 − − 2.0(2) 3.0(2) Il input leakage current VCC or GND IOZ 3-state output OFF-state current VIH or VIL ICC quiescent supply voltage VCC or GND ∆ICC additional quiescent supply VCC − 0.6 current given per data I/O pin with bus hold IBHL bus hold LOW sustaining current bus hold HIGH sustaining current IBHH OTHER µA −75 −175 − IBHLO bus hold LOW overdrive current 3.6(2) 500 − − µA IBHHO bus hold LOW overdrive current 3.6(2) −500 − − µA Notes 1. All typical values are measured at Tamb = 25 °C. 2. Valid for data inputs of bus hold parts. 1999 Nov 23 9 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 AC CHARACTERISTICS FOR VCC = 2.3 TO 2.7 V Ground = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH VCC (V) Tamb = −40 TO +85 °C MIN. TYP.(1) UNIT MAX. propagation delay nAn, nBn to nBn, nAn see Figs 6 and 10 2.3 to 2.7 1.0 2.7 4.8 ns propagation delay nCPAB, nCPBA to nBn, nAn see Figs 8 and 10 2.3 to 2.7 1.0 3.4 6.8 ns propagation delay nSAB, nSBA to nBn, nAn see Figs 7 and 10 2.3 to 2.7 1.0 3.4 5.6 ns tPZH/tPZL 3-state output enable time nOEAB to nBn see Figs 9 and 10 2.3 to 2.7 1.0 2.6 4.5 ns tPHZ/tPLZ 3-state output disable time nOEAB to nBn see Figs 9 and 10 2.3 to 2.7 1.6 2.7 4.5 ns tPZH/tPZL 3-state output enable time nOEBA to nAn see Figs 9 and 10 2.3 to 2.7 3.3 2.8 4.5 ns tPHZ/tPLZ 3-state output disable time nOEBA to nAn see Figs 9 and 10 2.3 to 2.7 3.3 2.5 4.5 ns tW clock pulse width HIGH or LOW nCPAB or nCPBA see Figs 8 and 10 2.3 to 2.7 2.2 1.2 − ns tsu set-up time nAn, nBn to nCPAB, nCPBA see Figs 8 and 10 2.3 to 2.7 2.2 0.2 − ns th hold time nAn, nBn to nCPAB, nCPBA see Figs 8 and 10 2.3 to 2.7 0.6 0.1 − ns fmax maximum clock pulse frequency see Figs 8 and 10 2.3 to 2.7 150 300 − MHz Note 1. All typical values are measured at Tamb = 25 °C and VCC = 2.5 V. 1999 Nov 23 10 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 AC CHARACTERISTICS FOR VCC = 2.7 V AND VCC = 3.0 TO 3.6 V Ground = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF. Tamb = −40 TO +85 °C TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPZH/tPZL tPHZ/tPLZ tW tsu th fmax propagation delay nAn, nBn to nBn, nAn see Figs 6 and 10 propagation delay nCPAB, nCPBA to nBn, nAn see Figs 8 and 10 propagation delay nSAB, nSBA to nBn, nAn see Figs 7 and 10 3-state output enable time nOEAB to nBn see Figs 9 and 10 3-state output disable time nOEAB to nBn see Figs 9 and 10 3-state output enable time nOEBA to nAn see Figs 9 and 10 3-state output disable time nOEBA to nAn see Figs 9 and 10 clock pulse width HIGH or LOW nCPAB or nCPBA see Figs 8 and 10 set-up time nAn, nBn to nCPAB, nCPBA see Figs 8 and 10 hold time nAn, nBn to nCPAB, nCPBA see Figs 8 and 10 maximum clock pulse frequency see Figs 8 and 10 2. Typical values at VCC = 3.3 V. 11 TYP.(1) UNIT MAX. 2.8 4.5 3.0 to 3.6 1.0 2.6(2) 3.9 2.7 − 3.1 5.2 3.0 to 3.6 1.4 2.9(2) 4.5 2.7 − 3.5 6.4 3.0 to 3.6 1.3 3.1(2) 5.3 2.7 − 2.4 4.6 3.0 to 3.6 1.0 2.2(2) 4.0 2.7 − 3.4 5.1 3.0 to 3.6 1.4 2.7(2) 4.5 2.7 − 3.0 4.6 3.0 to 3.6 1.0 2.2(2) 4.0 2.7 − 3.1 5.1 3.0 to 3.6 1.1 2.9(2) 4.5 2.7 3.3 1.0 − 3.0 to 3.6 3.3 0.7(2) − 2.7 1.7 0.2 − 1.4 0.3(2) − 2.7 0.4 0.1 − 3.0 to 3.6 0.7 0.2(2) − 2.7 150 320 − 150 320(2) − 3.0 to 3.6 1. All typical values are measured at Tamb = 25 °C. MIN. − 2.7 3.0 to 3.6 Notes 1999 Nov 23 VCC (V) ns ns ns ns ns ns ns ns ns ns MHz Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 AC WAVEFORMS handbook, halfpageVI handbook, halfpage VI nAn, nBn nSAB, nSBA VM input GND GND tPHL tPHL tPLH VOH nBn, nAn output nBn, nAn VM VM output VOL MNA320 Fig.7 The inputs nAn, nBn to outputs nBn, nAn propagation delay times. handbook, full pagewidth tPLH VOH VOL Fig.6 VM input MNA321 The inputs nSAB, nSBA to outputs nBn, nAn propagation delays. VI nAn, nBn VM input GND th th tsu tsu VOH nCPAB, nCPBA VM output VOL tW 1/fmax VOH nBn, nAn output VOL tPHL tPLH MNA322 Fig.8 The nAn, nBn to nCPAB, nCPBA set-up and hold times, clock nCPAB, nCPBA pulse width, maximum clock pulse frequency and the nCPAB, nCPBA to output nBn, nAn propagation delay times. 1999 Nov 23 12 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 VI handbook, full pagewidth nOEAB input VM GND VI nOEBA input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ tPZH VOH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled MNA323 Fig.9 The OE inputs (nOEAB, nOEBA) to outputs nAn, nBn enable and disable times and the input rise and fall times. Notes: VCC = 2.3 to 2.7 V VM = 0.5VCC; VX = VOL + 150 mV; VY = VOH − 150 mV; VI = VCC; VOL and VOH are typical output voltage drop that occur with the output load. Notes: VCC = 3.0 to 3.6 V and VCC = 2.7 V VM = 1.5 V; VX = VOL + 300 mV; VY = VOH − 300 mV; VI = 2.7 V; VOL and VOH are typical output voltage drop that occur with the output load. 1999 Nov 23 13 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 S1 handbook, full pagewidth VCC VI PULSE GENERATOR RL 500 Ω VO 2 × VCC open GND D.U.T. CL 50 pF RT RL 500 Ω MNA296 TEST S1 VCC VI tPLH/tPHL open tPLZ/tPZL 2 × VCC <2.7 V tPHZ/tPZH GND 2.7 to 3.6 V 2.7 V VCC Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”). RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.10 Load circuitry for switching times. APPLICATION INFORMATION handbook, halfpage OEAB L OEBA L CPAB X CPBA X SAB X SBA L OEAB H MNA325 OEBA H CPAB X CPBA X SAB L SBA X MNA326 Fig.11 Real-time transfer; bus B to bus A. 1999 Nov 23 BUS B BUS A BUS A BUS B handbook, halfpage Fig.12 Real-time transfer; bus A to bus B. 14 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state handbook, halfpage 74ALVCH16652 OEAB OEBA X H L X L H CPAB CPBA X X BUS B BUS A BUS A BUS B handbook, halfpage OEAB OEBA CPAB CPBA SAB X SBA X H H H or L X H X X X L L X H or L X H X X H L H or L H or L H H SAB SBA MNA328 MNA327 Fig.14 Transfer A stored data to B bus or B stored data to A bus or both at the same time. Fig.13 Store A, B or A and B in one register. handbook, halfpage OEAB OEAB H SAB X SBA X L L X L CPAB CPBA BUS B BUS A BUS A BUS B handbook, halfpage X OEAB OEBA CPAB CPBA SAB SBA L H H or L H or L X X MNA330 MNA329 Fig.15 Store bus A in both registers or store bus B in both registers. 1999 Nov 23 Fig.16 Isolation. 15 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 PACKAGE OUTLINE TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 28 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1.0 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 1999 Nov 23 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-02-03 95-02-10 MO-153EE 16 o Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state SOLDERING 74ALVCH16652 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Nov 23 17 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state 74ALVCH16652 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Nov 23 18 Philips Semiconductors Product specification 16-bit transceiver/register with dual enable; 3-state NOTES 1999 Nov 23 19 74ALVCH16652 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 68 © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245004/02/pp20 Date of release: 1999 Nov 23 Document order number: 9397 750 05256