a 16-Bit, 160 MSPS 2/4/8 Interpolating Dual TxDAC+ D/A Converter AD9777* ® FEATURES 16-Bit Resolution, 160/400 MSPS Input/Output Data Rate Selectable 2/4/8 Interpolating Filter Programmable Channel Gain and Offset Adjustment f S/4, fS/8 Digital Quadrature Modulation Capability Direct IF Transmission Mode for 70 MHz + IFs Enables Image Rejection Architecture Fully Compatible SPI Port Excellent AC Performance SFDR –73 dBc @ 2 MHz–35 MHz WCDMA ACPR 71 dB @ IF = 71 MHz Internal PLL Clock Multiplier Selectable Internal Clock Divider Versatile Clock Input Differential/Single-Ended Sine Wave or TTL/CMOS/LVPECL Compatible Versatile Input Data Interface Two’s Complement/Straight Binary Data Coding Dual-Port or Single-Port Interleaved Input Data Single 3.3 V Supply Operation Power Dissipation: Typical 1.2 W @ 3.3 V On-Chip 1.2 V Reference 80-Lead Thermally Enhanced TQFP Package APPLICATIONS Communications Analog Quadrature Modulation Architectures 3G, Multicarrier GSM, TDMA, CDMA Systems Broadband Wireless, Point-to-Point Microwave Radios Instrumentation/ATE GENERAL DESCRIPTION The AD9777 is the 16-bit member of the AD977x pin compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+ family. The AD977x family features a serial port interface (SPI) providing a high level of programmability, thus allowing for enhanced system level options. These options include: selectable 2×/4×/8× interpolation filters; fS/2, fS/4, or fS/8 digital quadrature modulation with image rejection; a direct IF mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or two’s complement data interface; and a single-port or dual-port data interface. The selectable 2×/4×/8× interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the TxDAC+ family’s pass-band noise/distortion performance. The independent channel gain and offset adjust registers allow the user to calibrate LO feedthrough and sideband suppression (continued on page 2) FUNCTIONAL BLOCK DIAGRAM IDAC COS AD9777 I AND Q NONINTERLEAVED OR INTERLEAVED DATA SELECT GAIN DAC OFFSET DAC SIN I LATCH 16 Q LATCH 16 16 16 16 fDAC/2, 4, 8 IMAGE REJECTION/ DUAL DAC MODE BYPASS MUX I/Q DAC GAIN/OFFSET REGISTERS SIN 16 WRITE HALFHALFBAND BAND FILTER 2* FILTER 3* IOFFSET 16 HALFBAND FILTER 1* VREF DATA ASSEMBLER MUX CONTROL 16 16 16 FILTER BYPASS MUX COS IDAC /2 IOUT (fDAC) CLOCK OUT /2 /2 /2 PRESCALER SPI INTERFACE AND CONTROL REGISTERS * HALF-BAND FILTERS ALSO CAN BE CONFIGURED FOR "ZERO STUFFING ONLY" DIFFERENTIAL CLK PHASE DETECTOR AND VCO PLL CLOCK MULTIPLIER AND CLOCK DIVIDER TxDAC+ is a registered trademark of Analog Devices, Inc. *Protected by U.S. Patent Numbers, 5568145, 5689257, and 5703519. Other patents pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD9777 (continued from page 1) errors associated with analog quadrature modulators. The 6 dB of gain adjustment range can also be used to control the output power level of each DAC. PRODUCT HIGHLIGHTS 1. The AD9777 is the 16-bit member of the AD977x pincompatible, high performance, programmable 2× /4×/8× interpolating TxDAC+ family. The AD9777 features the ability to perform fS/2, fS/4, and fS/8 digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, the AD9777 accepts I and Q complex data (representing a single or multicarrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process. Another digital modulation mode (i.e., the Direct IF Mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the DAC update rate. 2. Direct IF transmission is possible for 70 MHz + IFs through a novel digital mixing process. 3. fS/2, fS/4, and fS/8 digital quadrature modulation and user-selectable image rejection simplify/remove cascaded SAW filter stages. 4. A 2×/4×/8× user-selectable interpolating filter eases data rate and output signal reconstruction filter requirements. 5. User-selectable two’s complement/straight binary data coding. 6. User programmable channel gain control over 1 dB range in 0.01 dB increments. 7. User-programmable channel offset control ± 10% over the FSR. 8. Ultra high speed 400 MSPS DAC conversion rate. 9. Internal clock divider provides data rate clock for easy interfacing. The AD977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. An internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks. It can also be disabled to allow the use of a higher performance external clock source. An internal programmable divider simplifies clock generation in the converter when using an external clock source. A flexible data input interface allows for straight binary or two’s complement formats and supports single-port interleaved or dual-port data. 10. Flexible clock input with single-ended or differential input, CMOS, or 1 V p-p LO sine wave input capability. Dual high performance DAC outputs provide a differential current output programmable over a 2 mA to 20 mA range. The AD9777 is manufactured on an advanced 0.35 micron CMOS process, operates from a single supply of 3.1 V to 3.5 V, and consumes 1.2 W of power. 11. Low power: Complete CMOS DAC operates on 1.2 W from a 3.1 V to 3.5 V single supply. The 20 mA full-scale current can be reduced for lower power operation, and several sleep functions are provided to reduce power during idle periods. Targeted at wide dynamic range, multicarrier and multistandard systems, the superb baseband performance of the AD9777 is ideal for wideband CDMA, multicarrier CDMA, multicarrier TDMA, multicarrier GSM, and high performance systems employing high order QAM modulation schemes. The image rejection feature simplifies and can help to reduce the number of signal band filters needed in a transmit signal chain. The direct IF mode helps to eliminate a costly mixer stage for a variety of communications systems. 12. On-chip voltage reference: The AD9777 includes a 1.20 V temperature compensated band gap voltage reference. 13. 80-lead thermally enhanced TQFP. –2– REV. 0 AD9777 AD9777–SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, unless DC SPECIFICATIONS otherwise noted.) Parameter Min RESOLUTION DC Accuracy1 Integral Nonlinearity Differential Nonlinearity 16 –6.5 ANALOG OUTPUT (for 1R and 2R Gain Setting Modes) Offset Error Gain Error (with Internal Reference) Gain Matching Full-Scale Output Current2 Output Compliance Range Output Resistance Output Resistance Gain, Offset Cal DACs, Monotonicity Guaranteed –0.025 –1.0 –1 2 –1.0 Max 1.14 REFERENCE INPUT Input Compliance Range Reference Input Resistance (REFLO = 3 V) Small Signal Bandwidth ±6 ±3 ± 0.01 ± 0.1 1.20 100 0.1 +6.5 % of FSR % of FSR % of FSR mA V kΩ pF 1.26 V nA 1.25 V MΩ MHz 0 50 POWER SUPPLY AVDD Voltage Range Analog Supply Current (IAVDD)4 IAVDD in SLEEP Mode CLKVDD (PLL OFF) Voltage Range Clock Supply Current (ICLKVDD)4 CLKVDD (PLL ON) Clock Supply Current (ICLKVDD) DVDD Voltage Range Digital Supply Current (IDVDD)4 Nominal Power Dissipation4 PDIS5 PDIS in PWDN Power Supply Rejection Ratio—AVDD ppm of FSR/°C ppm of FSR/°C ppm/°C 3.1 3.3 72.5 23.3 3.5 76 26 V mA mA 3.1 3.3 8.5 3.5 V mA 23.5 3.1 OPERATING RANGE –40 NOTES 1 Measured at I OUTA driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32× the IREF current. 3 Use an external amplifier to drive any external load. 4 100 MSPS fDAC with fOUT = 1 MHz, all supplies = 3.3 V, no interpolation, no modulation. 5 400 MSPS f DAC, fDATA = 50 MSPS, fS/2 modulation, PLL enabled. Specifications subject to change without notice. –3– LSB LSB +0.025 +1.0 +1 20 +1.25 10 0.5 TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (With Internal Reference) Reference Voltage Drift Unit Bits 200 3 REFERENCE OUTPUT Reference Voltage Reference Output Current3 REV. 0 Typ 3.3 34 380 1.75 6.0 ± 0.4 mA 3.5 41 410 V mA mW W mW % of FSR/V +85 °C AD9777 DYNAMIC SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA, Interpolation = 2, Differential Transformer Coupled Output, 50 Doubly Terminated, unless otherwise noted.) Parameter Min DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) Output Settling Time (tST) (to 0.025%) Output Rise Time (10% to 90%)* Output Fall Time (10% to 90%)* Output Noise (IOUTFS = 20 mA) Typ 400 AC LINEARITY—BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS) fDATA = 100 MSPS, fOUT = 1 MHz fDATA = 65 MSPS, fOUT = 1 MHz fDATA = 65 MSPS, fOUT = 15 MHz fDATA = 78 MSPS, fOUT = 1 MHz fDATA = 78 MSPS, fOUT = 15 MHz fDATA = 160 MSPS, fOUT = 1 MHz fDATA = 160 MSPS, fOUT = 15 MHz Spurious-Free Dynamic Range within a 1 MHz Window (fOUT = 0 dBFS, fDATA = 100 MSPS, fOUT = 1 MHz) Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = –6 dBFS) fDATA = 65 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz fDATA = 65 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz fDATA = 78 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz fDATA = 78 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz fDATA = 160 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz fDATA = 160 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz Total Harmonic Distortion (THD) fDATA = 100 MSPS, fOUT = 1 MHz; 0 dBFS Signal-to-Noise Ratio (SNR) fDATA = 78 MSPS, fOUT = 5 MHz; 0 dBFS fDATA = 160 MSPS, fOUT = 5 MHz; 0 dBFS Adjacent Channel Power Ratio (ACLR) WCDMA with MHz BW, MHz Channel Spacing IF = Baseband, fDATA = 76.8 MSPS IF = 19.2 MHz, fDATA = 76.8 MSPS Four-Tone Intermodulation 21 MHz, 22 MHz, 23 MHz, and 24 MHz at –12 dBFS (fDATA = MSPS, Missing Center) AC LINEARITY—IF MODE Four-Tone Intermodulation at IF = 200 MHz 201 MHz, 202 MHz, 203 MHz, and 204 MHz at –12 dBFS (fDATA = 160 MSPS, fDAC = 320 MHz) Max Unit 11 0.8 0.8 50 MSPS ns ns ns pA√Hz 71 85 85 84 85 83 85 83 dBc dBc dBc dBc dBc dBc dBc 73 99.1 –71 85 78 85 78 85 84 dBc dBc dBc dBc dBc dBc –83 dB 79 75 dB dB 77 73 dBc dBc 76 dBFS 72 dBFS *Measured single ended into 50 Ω load. Specifications subject to change without notice. –4– REV. 0 AD9777 DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.) Parameter DIGITAL INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance Min Typ 2.1 3 0 –10 –10 Max Unit 0.9 +10 +10 V V µA µA pF 5 CLOCK INPUTS Input Voltage Range Common-Mode Voltage Differential Voltage 0 0.75 0.5 3 2.25 1.5 1.5 V V V Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min Max Unit AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD AGND, DGND, CLKGND REFIO, REFLO, FSADJ1/2 IOUTA, IOUTB P1B15–P1B0, P2B15–P2B0 DATACLK, PLL_LOCK CLK+, CLK–, RESET LPF SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO Junction Temperature Storage Temperature Lead Temperature (10 sec) AGND, DGND, CLKGND AVDD, DVDD, CLKVDD AGND, DGND, CLKGND AGND AGND DGND DGND CLKGND CLKGND DGND –0.3 –4.0 –0.3 –0.3 –1.0 –0.3 –0.3 –0.3 –0.3 –0.3 +4.0 +4.0 +0.3 AVDD + 0.3 AVDD + 0.3 DVDD + 0.3 DVDD + 0.3 CLKVDD + 0.3 CLKVDD + 0.3 DVDD + 0.3 V V V V V V V V V V –65 +125 +150 +300 °C °C °C *Stresses above those listed under the ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range AD9777BSV –40°C to +85°C AD9777EB THERMAL CHARACTERISTICS Package Description Package Option* Thermal Resistance 80-Lead TQFP Evaluation Board SV-80 *With thermal pad soldered to PCB. 80-Lead Thermally Enhanced TQFP Package JA = 23.5 °C/W* *SV = Thin Plastic Quad Flatpack CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9777 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– WARNING! ESD SENSITIVE DEVICE AD9777 AGND AVDD AVDD AGND AVDD AGND AGND IOUTA2 IOUTB2 AGND AGND AGND IOUTA1 IOUTB1 AVDD AGND AGND AVDD AGND AVDD PIN CONFIGURATION 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CLKVDD 1 60 FSADJ1 59 FSADJ2 CLKVDD 3 58 REFIO CLKGND 4 57 RESET CLK+ 5 56 SPI_CSB CLK– 6 55 SPI_CLK CLKGND 7 DATACLK/PLL_LOCK 8 54 SPI_SDIO 53 SPI_SDO 52 DGND 51 DVDD 50 P2B0 (LSB) P1B14 12 49 P1B13 13 48 P2B1 P2B2 P1B12 14 47 P2B3 P1B11 15 46 P2B4 P1B10 16 45 P2B5 DGND 17 44 DGND DVDD 18 43 DVDD P1B9 19 42 P2B6 P1B8 20 41 P2B7 PIN 1 IDENTIFIER AD9777 TxDAC+ DGND 9 DVDD 10 TOP VIEW (Not to Scale) P1B15 (MSB) 11 –6– P2B8 P2B9 P2B10 P2B11 DGND DVDD P2B13 P2B12 ONEPORTCLK/P2B14 P1B1 P1B3 P1B2 DVDD P1B4 DGND P1B5 P1B7 P1B6 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P1B0 (LSB) IQSEL/P2B15 (MSB) LPF 2 REV. 0 AD9777 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic 1, 3 2 4, 7 5 6 8 CLKVDD LPF CLKGND CLK+ CLK– DATACLK/PLL_LOCK Description Clock Supply Voltage PLL Loop Filter Clock Supply Common Differential Clock Input Differential Clock Input With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic “1” indicates the PLL is in the locked state. Logic “0” indicates the PLL has not achieved lock. This pin may also be programmed to act as either an input or output (Address 02h, Bit 3) DATACLK signal running at the input data rate. 9, 17, 25, 35, 44, 52 DGND Digital Common 10, 18, 26, 36, 43, 51 DVDD Digital Supply Voltage 11–16, 19–24, 27–30 P1B15 (MSB) to P1B0 (LSB) Port “1” Data Inputs 31 IQSEL/P2B15 (MSB) In “1” port mode, IQSEL = 1 followed by a rising edge of the differential input clock will latch the data into the I channel input register. IQSEL = 0 will latch the data into the Q channel input register. In “2” port mode, this pin becomes the port “2” MSB. 32 ONEPORTCLK/P2B14 With the PLL disabled and the AD9777 in “1” port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9777 to accept and demux interleaved I and Q data to the I and Q input registers. 33, 34, 37–42, 45–50 P2B13 to P2B0 (LSB) Port “2” Data Inputs 53 SPI_SDO In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an output, SDO enters a High-Z state. 54 SPI_SDIO Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 00h. The default setting for this bit is “0,” which sets SDIO as an input. 55 SPI_CLK Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output on the SPI port is registered on the falling edge. 56 SPI_CSB Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port logic and initializes instruction cycle. 57 RESET Logic “1” resets all of the SPI port registers, including Address 00h, to their default values. A software reset can also be done by writing a Logic “1” to SPI Register 00h, Bit 5. However, the software reset has no effect on the bits in Address 00h. 58 REFIO Reference Output, 1.2 V Nominal 59 FSADJ2 Full-Scale Current Adjust, Q Channel 60 FSADJ1 Full-Scale Current Adjust, I Channel 61, 63, 65, 76, 78, 80 AVDD Analog Supply Voltage 62, 64, 66, 67, 70, 71, AGND Analog Common 74, 75, 77, 79 68, 69 IOUTA2, IOUTB2 Differential DAC Current Outputs, Q Channel 72, 73 IOUTA1, IOUTB1 Differential DAC Current Outputs, I Channel REV. 0 –7– AD9777 DIGITAL FILTER SPECIFICATIONS 20 0 Half-Band Filter No. 1 (43 Coefficients) 1, 43 2, 42 3, 41 4, 40 5, 39 6, 38 7, 37 8, 36 9, 35 10, 34 11, 33 12, 32 13, 31 14, 30 15, 29 16, 28 17, 27 18, 26 19, 25 20, 24 21, 23 22 8 0 –29 0 67 0 –134 0 244 0 –414 0 673 0 –1079 0 1772 0 –3280 0 10364 16384 1, 19 2, 18 3, 17 4, 16 5, 15 6, 14 7, 13 8, 12 9, 11 10 19 0 –120 0 438 0 –1288 0 5047 8192 Coefficient 1, 11 2, 10 3, 9 4, 8 5, 7 6 7 0 –53 0 302 512 –80 –120 0 1.0 1.5 0.5 fOUT – Normalized to Input Data Rate 2.0 Figure 1a. 2 Interpolating Filter Response 20 0 –20 –40 –60 –80 –100 –120 0 1.0 1.5 0.5 fOUT – Normalized to Input Data Rate 2.0 Figure 1b. 4 Interpolating Filter Response 20 0 Half-Band Filter No. 3 (11 Coefficients) Tap –60 ATTENUATION – dBFS Coefficient –40 –100 Half-Band Filter No. 2 (19 Coefficients) Tap –20 ATTENUATION – dBFS Coefficient ATTENUATION – dBFS Tap –20 –40 –60 –80 –100 –120 0 4 6 2 fOUT – Normalized to Input Data Rate 8 Figure 1c. 8 Interpolating Filter Response –8– REV. 0 AD9777 Offset Error DEFINITIONS OF SPECIFICATIONS Adjacent Channel Power Ratio (ACPR) The deviation of the output current from the ideal of “0” is called offset error. For IOUTA, 0 mA output is expected when the inputs are all “0.” For IOUTB, 0 mA output is expected when all inputs are set to “1.” A ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Output Compliance Range Complex Modulation Frequency band in which any input applied therein passes unattenuated to the DAC output. The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Pass Band The process of passing the real and imaginary components of a signal through a complex modulator (transfer function = ejt = cost + jsint) and realizing real and imaginary components on the modulator output. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Differential Nonlinearity (DNL) Signal-to-Noise Ratio (SNR) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to “1,” minus the output when all inputs are set to “0.” Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV–S. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Group Delay Number of input clocks between an impulse applied at the device input and peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range. Stop-Band Rejection Impulse Response The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band. Response of the device to an impulse applied to the input. Temperature Drift Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that would typically appear around fDAC (output data rate) can be greatly suppressed. Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. Linearity Error (Also Called Integral Nonlinearity or INL) Total Harmonic Distortion (THD) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB). Monotonicity A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. REV. 0 –9– AD9777 –Typical Performance Characteristics (T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, Interpolation = 2, Differential Coupled Transformer Output, 50 Doubly Terminated, unless otherwise noted.) 10 90 0 85 90 0dBFS 80 80 75 75 –12dBFS –30 –40 –50 –60 SFDR – dBc –20 SFDR – dBc AMPLITUDE – dBm –10 0dBFS 85 –6dBFS 70 –12dBFS 65 70 –6dBFS 65 60 60 55 55 –70 –80 50 –90 0 65 FREQUENCY – MHz 0 130 TPC 1. Single-Tone Spectrum @ fDATA = 65 MSPS with fOUT = fDATA/3 10 15 20 FREQUENCY – MHz 25 50 30 0 TPC 2. In-Band SFDR vs. fOUT @ fDATA = 65 MSPS 5 10 15 20 FREQUENCY – MHz 25 30 TPC 3. Out-of-Band SFDR vs. fOUT @ fDATA = 65 MSPS 90 10 90 0 85 85 80 80 –10 0dBFS 0dBFS –20 –30 –40 –50 –60 75 SFDR – dBc SFDR – dBc AMPLITUDE – dBm 5 –6dBFS 70 –12dBFS 65 75 70 –6dBFS –12dBFS 65 60 60 55 55 –70 –80 50 50 –90 0 100 50 FREQUENCY – MHz 0 150 TPC 4. Single-Tone Spectrum @ fDATA = 78 MSPS with fOUT = fDATA/3 5 10 15 20 FREQUENCY – MHz 25 0 30 TPC 5. In-Band SFDR vs. fOUT @ fDATA = 78 MSPS 10 15 20 FREQUENCY – MHz 25 30 TPC 6. Out-of-Band SFDR vs. fOUT @ fDATA = 78 MSPS 90 90 10 5 0dBFS 0 –6dBFS 80 80 75 75 –30 –40 –50 SFDR – dBc –20 SFDR – dBc AMPLITUDE – dBm 85 85 –10 70 –12dBFS 65 –12dBFS –6dBFS 70 65 0dBFS –60 60 60 55 55 –70 –80 50 50 –90 0 200 100 FREQUENCY – MHz TPC 7. Single-Tone Spectrum @ fDATA = 160 MSPS with fOUT = fDATA/3 300 0 10 20 30 40 FREQUENCY – MHz TPC 8. In-Band SFDR vs. fOUT @ fDATA = 160 MSPS –10– 50 0 10 20 30 40 FREQUENCY – MHz 50 TPC 9. Out-of-Band SFDR vs. fOUT @ fDATA = 160 MSPS REV. 0 AD9777 (T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, Interpolation = 2, Differential Coupled Transformer Output, 50 Doubly Terminated, unless otherwise noted.) 90 90 0dBFS 85 0dBFS 85 80 80 –3dBFS –3dBFS –6dBFS 70 65 75 –3dBFS IMD – dBc 75 IMD – dBc –6dBFS 70 65 65 60 55 55 55 0 10 15 20 FREQUENCY – MHz 5 25 50 50 30 TPC 10. Third Order IMD Products vs. Two-Tone fOUT @ fDATA = 65 MSPS 0 5 10 15 20 FREQUENCY – MHz 25 90 0 30 TPC 11. Third Order IMD Products vs. Two-Tone fOUT @ fDATA = 78 MSPS 90 85 85 80 80 80 2 65 1 2 70 65 75 65 60 60 55 55 55 20 30 40 FREQUENCY – MHz 10 50 50 –15 60 TPC 13. Third Order IMD Products vs. Two-Tone fOUT and Interpolation Rate 1⫻ fDATA = 160 MSPS, 2⫻ fDATA = 160 MSPS, 4⫻ fDATA = 80 MSPS, 8⫻ fDATA = 50 MSPS 50 3.1 0 90 90 85 85 –6dBFS SNR – dB 75 70 65 80 80 75 75 70 PLL ON 65 FDATA = 65MSPS 60 55 55 55 3.4 3.5 TPC 16. Third Order IMD Products vs. AVDD @ fOUT = 10 MHz, fDAC = 320 MSPS, fDATA = 160 MSPS 50 0 50 100 INPUT DATA RATE – MSPS 150 TPC 17. SNR vs. Data Rate for fOUT = 5 MHz –11– 160MSPS 65 60 REV. 0 3.5 70 60 3.3 AVDD – V 3.4 PLL OFF –3dBFS 3.2 3.3 AVDD – V 78MSPS 0dBFS 80 50 3.1 3.2 TPC 15. SFDR vs. AVDD @ fOUT = 10 MHz, fDAC = 320 MSPS, fDATA = 160 MSPS TPC 14. Third Order IMD Products vs. Two-Tone AOUT and Interpolation Rate fDATA = 50 MSPS for All Cases 1⫻ fDAC = 50 MSPS, 2⫻ fDAC = 100 MSPS, 4⫻ fDAC = 200 MSPS, 8⫻ fDAC = 400 MSPS 90 85 –10 –5 AOUT – dBFS –12dBFS 70 60 50 60 –6dBFS SFDR – dBc IMD – dBc 1 70 75 50 0dBFS 4 75 0 20 30 40 FREQUENCY – MHz 90 85 8 10 TPC 12. Third Order IMD Products vs. Two-Tone fOUT @ fDATA = 160 MSPS 8 4 IMD – dBc –6dBFS 70 60 50 IMD – dBc 75 60 SFDR – dBc IMD – dBc 80 90 0dBFS 85 50 –50 50 0 TEMPERATURE – C 100 TPC 18. SFDR vs. Temperature @ fOUT = fDATA/11 AD9777 (T = 25C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, Interpolation = 2, Differential Coupled Transformer Output, 50 Doubly Terminated, unless otherwise noted.) 0 0 0 –10 –10 –20 –40 –50 –60 –70 –20 AMPLITUDE – dBm –30 AMPLITUDE – dBm AMPLITUDE – dBm –20 –40 –60 –30 –40 –50 –60 –70 –80 –80 –100 –100 –80 –90 –90 –100 0 50 100 FREQUENCY – MHz 0 150 TPC 19. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 150 MSPS, No Interpolation 10 20 30 40 FREQUENCY – MHz 50 TPC 20. Two-Tone IMD Performance, fDATA = 150 MSPS, No Interpolation 0 200 100 150 FREQUENCY – MHz 250 300 TPC 21. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 150 MSPS, Interpolation = 2 0 0 50 0 –10 –20 –40 –60 –20 –30 AMPLITUDE – dBm AMPLITUDE – dBm AMPLITUDE – dBm –20 –40 –50 –60 –70 –80 –80 –40 –60 –80 –90 –100 –100 0 5 10 15 20 25 30 35 FREQUENCY – MHz 40 TPC 22. Two-Tone IMD Performance, fDATA = 90 MSPS, Interpolation = 4⫻ 0 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –70 –80 50 250 150 100 200 FREQUENCY – MHz –100 300 0 TPC 23. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 80 MSPS, Interpolation = 4⫻ AMPLITUDE – dBm AMPLITUDE – dBm 0 45 5 10 20 15 FREQUENCY – MHz 25 TPC 24. Two-Tone IMD Performance, fOUT = 10 MHz, fDATA = 50 MSPS, Interpolation = 8⫻ –40 –50 –60 –70 –80 –90 –90 –100 –100 0 300 100 200 FREQUENCY – MHz TPC 25. Single-Tone Spurious Performance, fOUT = 10 MHz, fDATA = 50 MSPS, Interpolation = 8⫻ 400 0 20 60 40 FREQUENCY – MHz 80 TPC 26. Eight-Tone IMD Performance, fDATA = 160 MSPS, Interpolation = 8⫻ –12– REV. 0 AD9777 MODE CONTROL (VIA SPI PORT) Table I. Mode Control via SPI Port (Default Values Are Highlighted) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 00h SDIO Bidirectional 0 = Input 1 = I/O LSB, MSB First 0 = MSB 1 = LSB Software Reset on Logic “1” Sleep Mode Logic “1” shuts down the DAC output currents. Power-Down Mode Logic “1” shuts down all digital and analog functions. 1R/2R Mode DAC output current set by one or two external resistors. 0 = 2R, 1 = 1R PLL_LOCK Indicator 01h Filter Interpolation Rate (1×, 2×, 4×, 8×) Filter Interpolation Rate (1×, 2×, 4×, 8×) Modulation Mode (None, fS/2, fS/4, fS/8) Modulation Mode (None, fS/2, fS/4, fS/8) 0 = No Zero Stuffing on Interpolation Filters, Logic “1” enables zero stuffing. 1 = Real Mix Mode 0 = Complex Mix Mode 0 = e–j 1 = e+j DATACLK/ PLL_LOCK Select 0 = PLLLOCK 1 = DATACLK 02h 0 = Signed Input Data 1 = Unsigned 0 = Two Port Mode 1 = One Port Mode DATACLK Driver DATACLK Invert Strength 0 = No Invert 1 = Invert ONEPORTCLK Invert 0 = No Invert 1 = Invert IQSEL Invert 0 = No Invert 1 = Invert Q First 0 = I First 1 = Q First PLL Divide (Prescaler) Ratio PLL Divide (Prescaler) Ratio PLL Charge Pump Control PLL Charge Pump Control PLL Charge Pump Control IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Coarse Gain Adjustment IDAC Coarse Gain Adjustment IDAC Coarse Gain Adjustment IDAC Coarse Gain Adjustment IDAC Offset Adjustment Bit 5 IDAC Offset Adjustment Bit 4 IDAC Offset Adjustment Bit 3 IDAC Offset Adjustment Bit 2 IDAC Offset Adjustment Bit 1 IDAC Offset Adjustment Bit 0 03h 04h 0 = PLL OFF 1 = PLL ON 0 = Automatic Charge Pump Control 1 = Programmable 05h IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment IDAC Fine Gain Adjustment 06h 07h IDAC Offset Adjustment Bit 9 08h IDAC IOFFSET Direction 0 = IOFFSET on IOUTA 1 = IOFFSET on IOUTB 09h QDAC Fine Gain Adjustment IDAC Offset Adjustment Bit 8 QDAC Fine Gain Adjustment IDAC Offset Adjustment Bit 7 QDAC Fine Gain Adjustment IDAC Offset Adjustment Bit 6 QDAC Fine Gain Adjustment 0Ah 0Bh QDAC Offset Adjustment Bit 9 0Ch QDAC IOFFSET Direction 0 = IOFFSET on IOUTA 1 = IOFFSET on IOUTB 0Dh REV. 0 QDAC Offset Adjustment Bit 8 QDAC Offset Adjustment Bit 7 QDAC Offset Adjustment Bit 6 Bit 0 QDAC Fine Gain Adjustment QDAC Fine Gain Adjustment QDAC Fine Gain Adjustment QDAC Fine Gain Adjustment QDAC Coarse Gain Adjustment QDAC Coarse Gain Adjustment QDAC Coarse Gain Adjustment QDAC Coarse Gain Adjustment QDAC Offset Adjustment Bit 5 QDAC Offset Adjustment Bit 4 QDAC Offset Adjustment Bit 3 QDAC Offset Adjustment Bit 2 QDAC Offset Adjustment Bit 1 QDAC Offset Adjustment Bit 0 Version Register Version Register Version Register –13– Version Register AD9777 REGISTER DESCRIPTION Address 00h Bit 7 Logic “0” (default) causes the SDIO pin to act as an input during the data transfer (Phase 2) of the communications cycle. When set to “1,” SDIO can act as an input or output, depending on Bit 7 of the instruction byte. Bit 6 Logic “0” (default). Determines the direction (LSB/MSB first) of the communications and data transfer communications cycles. Refer to the section MSB/LSB Transfers for a detailed description. Bit 5 Writing a “1” to this bit resets the registers to their default values and restarts the chip. The RESET bit always reads back “0.” Register Address 00h bits are not cleared by this software reset. However, a high level at the RESET pin forces all registers, including those in Address 00h, to their default state. Bit 4 Sleep mode. A Logic “1” to this bit shuts down the DAC output currents. Bit 3 Power-Down. Logic “1” shuts down all analog and digital functions except for the SPI port. Bit 2 1R/2R Mode. The default (“0”) places the AD9777 in two resistor mode. In this mode, the IREF currents for the I and Q DAC references are set separately by the RSET resistors on FSADJ1 and FSADJ2 (Pins 60 and 59). In the 2R mode, assuming the coarse gain setting is full scale and the fine gain setting is “0,” IFULLSCALE1 = 32 × VREF/FSADJ1 and IFULLSCALE2 = 32 × VREF/FSADJ2. With this bit set to “1,” the reference currents for both I and Q DACs are controlled by a single resistor on Pin 60. IFULLSCALE in one resistor mode for both the I and Q DACs is half of what it would be in the 2R mode, assuming all other conditions (RSET, register settings) remain unchanged. The full-scale current of each DAC can still be set to 20 mA by choosing a resistor of half the value of the RSET value used in the 2R mode. Bit 1 Bits 5, 4 Bit 1 Logic “0” (default) causes the complex modulation to be of the form e–jt, resulting in the rejection of the higher frequency image when the AD9777 is used with an external quadrature modulator. A Logic “1” causes the modulation to be of the form e+jt, which causes rejection of the lower frequency image. Bit 0 In two port mode, a Logic “0” (default) causes Pin 8 to act as a lock indicator for the internal PLL. A Logic “1” in this register causes Pin 8 to act as a DATACLK, either generating or acting as an input clock (see Register 02h, Bit 3) at the input data rate of the AD9777. Address 02h Logic “0” (default) causes data to be accepted on the inputs as two’s complement binary. Logic “1” causes data to be accepted as straight binary. Bit 6 Logic “0” (default) places the AD9777 in two port mode. I and Q data enters the AD9777 via Ports 1 and 2, respectively. A Logic “1” places the AD9777 in one port mode in which interleaved I and Q data is applied to Port 1. See the Pin Function Descriptions for DATACLK/PLL_LOCK, IQSEL, and ONEPORTCLK for detailed information on how to use these modes. Bit 5 DATACLK Driver Strength. With the internal PLL disabled and this bit set to Logic “0,” it is recommended that DATACLK be buffered. When this bit is set to Logic “1,” DATACLK acts as a stronger driver capable of driving small capacitive loads. Filter interpolation rate according to the following table: Bit 4 Default Logic “0.” A value of “1” inverts DATACLK at Pin 8. 00 01 10 11 Bit 2 Default Logic “0.” A value of “1” inverts ONEPORTCLK at Pin 32. Bit 1 The default of Logic “0” causes IQSEL = 1 to direct input data to the I channel, while IQSEL = 0 directs input data to the Q channel. A Logic “1” in this register inverts the sense of IQSEL. Bit 0 The default of Logic “0” defines IQ pairing as IQ, IQ... while programming a Logic “1” causes the pair ordering to be QI, QI... PLL_LOCK Indicator. When the PLL is enabled, reading this bit will give the status of the PLL. A Logic “1” indicates the PLL is locked. A Logic “0” indicates an unlocked state. 1× 2× 4× 8× Modulation mode according to the following table: 00 01 10 11 Bit 3 Default (“1”) enables the real mix mode. The I and Q data channels are individually modulated by fS/2, fS/4, or fS/8 after the interpolation filters. However, no complex modulation is done. In the complex mix mode (Logic “0”), the digital modulators on the I and Q data channels are coupled to create a digital complex modulator. When the AD9777 is applied in conjunction with an external quadrature modulator, rejection can be achieved of either the higher or lower frequency image around the second IF frequency (i.e., the second IF frequency is the LO of the analog quadrature modulator external to the AD9777) according to the bit value of Register 01h, Bit 1. Bit 7 Address 01h Bits 7, 6 Bit 2 none fS/2 fS/4 fS/8 Logic “1” enables zero stuffing mode for interpolation filters. –14– REV. 0 AD9777 Address 03h Address 05h, 09h Bits 1, 0 Bits 7–0 Setting this divide ratio to a higher number allows the VCO in the PLL to run at a high rate (for best performance) while the DAC input and output clocks run substantially slower. The divider ratio is set according to the following table: 00 01 10 11 ⫼1 ⫼2 ⫼4 ⫼8 These bits represent an 8-bit binary number (Bit 7 MSB) that defines the fine gain adjustment of the I (05h) and Q (09h) DAC according to the equation given below. Address 06h, 0Ah Bits 3–0 These bits represent a 4-bit binary number (Bit 3 MSB) that defines the coarse gain adjustment of the I (06h) and Q (0Ah) DACs according to the equation below. Address 04h Address 07h, 0Bh Bit 7 Logic “0” (default) disables the internal PLL. Logic “1” enables the PLL. Bits 7–0 Bit 6 Logic “0” (default) sets the charge pump control to automatic. In this mode, the charge pump bias current is controlled by the divider ratio defined in Address 03h, Bits 1 and 0. Logic “1” allows the user to manually define the charge pump bias current using Address 04h, Bits 2, 1, and 0. Adjusting the charge pump bias current allows the user to optimize the noise/settling performance of the PLL. Bits 1, 0 Address 08h, 0Ch Address 08h, 0Ch Bit 7 Bits 2, 1, 0 With the charge pump control set to manual, these bits define the charge pump bias current according to the following table: 000 001 010 011 100 50 µA 100 µA 200 µA 400 µA 800 µA 6 × IREF IOUTA = 8 6 × IREF IOUTB = 8 The 10 bits from these two address pairs (07h, 08h and 0Bh, 0Ch) represent a 10-bit binary number that defines the offset adjustment of the I and Q DACs according to the equation below (07h, 0Bh–Bit 7 MSB/08h, 0Ch–Bit 0 LSB). This bit determines the direction of the offset of the I (08h) and Q (0Ch) DACs. A Logic “0” will apply a positive offset current to IOUTA, while a Logic “1” will apply a positive offset current to IOUTB. The magnitude of the offset current is defined by the bits in Addresses 07h, 0Bh, 08h, 0Ch according to the formulas given below. COARSE + 1 3 × IREF – 32 16 FINE 1024 DATA × 256 24 216 COARSE + 1 3 × IREF – 32 16 FINE 1024 216 – DATA – 1 × 256 24 216 (1) OFFSET IOFFSET = 4 × IREF 1024 Equation 1 shows IOUTA and IOUTB as a function of fine gain, coarse gain, and offset adjustment when using the 2R mode. In the 1R mode, the current IREF is created by a single FSADJ resistor (Pin 60). This current is divided equally into each channel so that a scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset. REV. 0 –15– AD9777 FUNCTIONAL DESCRIPTION SERIAL INTERFACE FOR REGISTER CONTROL The AD9777 dual interpolating DAC consists of two data channels that can be operated completely independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the AD9777 capable of 2×, 4×, or 8× interpolation. High speed input and output data rates can be achieved within the following limitations: The AD9777 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel SSR protocols. The interface allows read/write access to all registers that configure the AD9777. Single- or multiple-byte transfers are supported as well as MSB first or LSB first transfer formats. The AD9777’s serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO). Interpolation Rate (MSPS) Input Data Rate (MSPS) DAC Sample Rate (MSPS) 1× 2× 4× 8× 160 160 100 50 160 320 400 400 GENERAL OPERATION OF THE SERIAL INTERFACE Both data channels contain a digital modulator capable of mixing the data stream with an LO of fDAC/2, fDAC/4, or fDAC/8, where fDAC is the output data rate of the DAC. A zero stuffing feature is also included and can be used to improve pass-band flatness for signals being attenuated by the SIN(x)/x characteristic of the DAC output. The speed of the AD9777, combined with its digital modulation capability, enables direct IF conversion architectures at 70 MHz and higher. The digital modulators on the AD9777 can be coupled to form a complex modulator. By using this feature with an external analog quadrature modulator, such as the Analog Devices AD8345, an image rejection architecture can be enabled. To optimize the image rejection capability, as well as LO feedthrough in this architecture, the AD9777 offers programmable (via the SPI port) gain and offset adjust for each DAC. Also included on the AD9777 are a phase-locked loop (PLL) clock multiplier and a 1.20 V band gap voltage reference. With the PLL enabled, a clock applied to the CLK+/CLK– inputs is frequency multiplied internally and generates all necessary internal synchronization clocks. Each 16-bit DAC provides two complementary current outputs whose full-scale currents can be determined either from a single external resistor, or independently from two separate resistors (see 1R/2R mode). The AD9777 features a low jitter, differential clock input that provides excellent noise rejection while accepting a sine or square wave input. Separate voltage supply inputs are provided for each functional block to ensure optimum noise and distortion performance. SDIO (PIN 54) SCLK (PIN 55) A logic high on the CSB pin, followed by a logic low, will reset the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the midst of an instruction cycle or a data transfer cycle, none of the present data will be written. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9777 and the system controller. Phase 2 of the communication cycle is a transfer of 1, 2, 3, to 4 data bytes as determined by the instruction byte. Normally, using one multibyte transfer is the preferred method. However, single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. INSTRUCTION BYTE The instruction byte contains the information shown below. SLEEP and power-down modes can be used to turn off the DAC output current (SLEEP) or the entire digital and analog sections (power-down) of the chip. An SPI-compliant serial port is used to program the many features of the AD9777. Note that in power-down mode, the SPI port is the only section of the chip still active. SDO (PIN 53) There are two phases to a communication cycle with the AD9777. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9777 coincident with the first eight SCLK rising edges. The instruction byte provides the AD9777 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9777. N1 N0 Description 0 0 1 1 0 1 0 1 Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes R/W Bit 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates read operation. Logic zero indicates a write operation. AD9777 SPI PORT INTERFACE CSB (PIN 56) Figure 2. SPI Port Interface –16– REV. 0 AD9777 N1, N0 SDIO (Pin 54)—Serial Data I/O Bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in the following table: Data is always written into the AD9777 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register Address 00h. The default is Logic “0,” which configures the SDIO Pin as unidirectional. MSB I7 R/W LSB I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 SDO (Pin 53)—Serial Data Out Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9777 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. I0 A0 A4, A3, A2, A1, A0 Bits 4, 3, 2, 1, and 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9777. MSB/LSB TRANSFERS The AD9777 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by Register Address 00h, Bit 6. The default is MSB first. When this bit is set active high, the AD9777 serial port is in LSB first format. That is, if the AD9777 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the most significant byte. In MSB first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. Multibyte data transfers in LSB first format can be completed by writing an instruction byte that includes the register address of the least significant byte. In LSB first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK (Pin 55)—Serial Clock The Serial Clock Pin is used to synchronize data to and from the AD9777 and to run the internal state machines. SCLK maximum frequency is 15 MHz. All data input to the AD9777 is registered on the rising edge of SCLK. All data is driven out of the AD9777 on the falling edge of SCLK. CSB (Pin 56)—Chip Select Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO Pins will go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. The AD9777 serial port controller address will increment from 1Fh to 00h for multibyte I/O operations if the MSB first mode is active. The serial port controller address will decrement from 00h to 1Fh for multibyte I/O operations if the LSB first mode is active. DATA TRANSFER CYCLE INSTRUCTION CYCLE CS SCLK SDIO R/W I6 (N) I5 (N) I4 I3 I2 I1 I0 SDO D7N D6N D20 D10 D00 D7N D6N D20 D10 D00 Figure 3a. Serial Register Interface Timing MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I0 I1 I2 I3 I4 I5 (N) I6 (N) R/W SDO D00 D10 D20 D6N D7N D00 D10 D20 D6N D7N Figure 3b. Serial Register Interface Timing LSB First REV. 0 –17– AD9777 tDS tSCLK CS tPWH tPWL SCLK tDS SDIO tDH INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 4. Timing Diagram for Register Write to AD9777 CS SCLK tDV SDIO DATA BIT N DATA BIT N–1 SDO Figure 5. Timing Diagram for Register Read from AD9777 NOTES ON SERIAL PORT OPERATION DAC OPERATION The AD9777 serial port configuration bits reside in Bits 6 and 7 of Register Address 00h. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The dual 16-bit DAC output of the AD9777, along with the reference circuitry, gain, and offset registers, is shown in Figure 6. Referring to the transfer functions in Equation 1, a reference current is set by the internal 1.2 V reference, the external RSET resistor, and the values in the coarse gain register. The fine gain DAC subtracts a small amount from this and the result is input to IDAC and QDAC, where it is scaled by an amount equal to 1024/24. Figures 7a and 7b show the scaling effect of the coarse and fine adjust DACs. IDAC and QDAC are PMOS current source arrays, segmented in a 5-4-7 configuration. The five most significant bits control an array of 31 current sources. The next four bits consist of 15 current sources whose values are all equal to 1/16 of an MSB current source. The seven LSBs are binary weighted fractions of the middle bit’s current sources. All current sources are switched to either IOUTA or IOUTB, depending on the input code. The same considerations apply to setting the reset bit in Register Address 00h. All other registers are set to their default values, but the software reset doesn’t affect the bits in Register Address 00h. It is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset. A write to Bits 1, 2, and 3 of Address 00h with the same logic levels as for Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to Address 00h with reset bit low and serial port configuration as specified above (XY) reprograms the OSC IN multiplier setting. A changed fSYSCLK frequency is stable after a maximum of 200 fMCLK cycles (equals wake-up time). The fine adjustment of the gain of each channel allows for improved balance of QAM modulated signals, resulting in improved modulation accuracy and image rejection. In the Applications section of this data sheet, performance data is included that shows to what degree image rejection can be improved when the AD9777 is used with an AD8345 quadrature modulator from ADI. –18– REV. 0 AD9777 The offset control defines a small current that can be added to IOUTA or IOUTB (not both) on the IDAC and QDAC. The selection of which IOUT this offset current is directed toward is programmable via Register 08h, Bit 7 (IDAC) and Register 0Ch, Bit 7 (QDAC). Figure 9 shows the scale of the offset current that can be added to one of the complementary outputs on the IDAC and QDAC. Offset control can be used for suppression of LO leakage resulting from modulation of dc signal components. If the AD9777 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the AD9777 as well as the input offset on the modulator. Figure 9 shows a typical example of the effect that the offset control has on LO suppression. FINE REFERENCE CURRENT – mA 0 –0.5 1R MODE –1.0 –1.5 2R MODE –2.0 –2.5 –3.0 FINE GAIN DAC GAIN CONTROL REGISTERS 1.2VREF 5 10 15 FINE GAIN REGISTER CODE – Assuming RSET1, 2 = 1.9k 20 Figure 7b. Fine Gain Effect on IFULLSCALE FINE GAIN DAC IOUTA1 IDAC IOUTB1 REFIO COARSE GAIN DAC 0.1F 0 OFFSET CONTROL OFFSET DAC REGISTERS COARSE GAIN DAC IOUTA2 QDAC IOUTB2 FSADJ1 FSADJ2 RSET1 RSET2 OFFSET CONTROL OFFSET DAC REGISTERS GAIN CONTROL REGISTERS Figure 6. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust In Figure 9, the negative scale represents an offset added to IOUTB, while the positive scale represents an offset added to IOUTA of the respective DAC. Offset Register 1 corresponds to IDAC, while Offset Register 2 corresponds to QDAC. Figure 9 represents the AD9777 synthesizing a complex signal that is then dc-coupled to an AD8345 quadrature modulator with an LO of 800 MHz. The dc-coupling allows the input offset of the AD8345 to be calibrated out as well. The LO suppression at the AD8345 output was optimized first by adjusting Offset Register 1, in the AD9777. When an optimal point was found (roughly Code 54), this code was held in Offset Register 1, and Offset Register 2 was adjusted. The resulting LO suppression is 70 dBFS. These are typical numbers, and the specific code for optimization will vary from part to part. 25 20 4 OFFSET CURRENT – mA COARSE REFERENCE CURRENT – mA 5 2R MODE 15 10 1R MODE 5 3 2R MODE 2 1R MODE 1 0 0 5 10 15 COARSE GAIN REGISTER CODE – Assuming RSET1, 2 = 1.9k 20 0 0 Figure 7a. Coarse Gain Effect on IFULLSCALE 200 400 600 800 COARSE GAIN REGISTER CODE – Assuming RSET1, 2 = 1.9k Figure 8. DAC Output Offset Current REV. 0 –19– 1000 AD9777 0 AD9777 –10 0.1F LO SUPPRESSION – dBFS OFFSET REGISTER 1 ADJUSTED 1k CLK+ 1k –20 ECL/PECL –30 0.1F 0.1F –40 1k 1k CLKVDD CLK– CLKGND –50 –60 OFFSET REGISTER 2 ADJUSTED, WITH OFFSET REGISTER 1 SET TO OPTIMIZED VALUE –70 –80 –1024 –768 –512 –256 0 256 512 DAC1, DAC2 – Offset Register Codes 768 Figure 11. Differential Clock Driving Clock Inputs A transformer, such as the T1-1T from Mini-Circuits, can also be used to convert a single-ended clock to differential. This method is used on the AD9777 evaluation board so that an external sine wave with no dc offset can be used as a differential clock. 1024 Figure 9. Offset Adjust Control, Effect on LO Suppression 1R/2R MODE In the 2R mode, the reference current for each channel is set independently by the FSADJ resistor on that channel. The AD9777 can be programmed to derive its reference current from a single resistor on Pin 60 by placing the part in the 1R mode. The transfer functions in Equation 1 are valid for the 2R mode. In the 1R mode, the current developed in the single FSADJ resistor is split equally between the two channels. The result is that in the 1R mode, a scale factor of one-half must be applied to the formulas in Equation 1. The full-scale DAC current in the 1R mode can still be set to as high as 20 mA by using the internal 1.2 V reference and a 950 Ω resistor, instead of the 1.9 kΩ resistor typically used in the 2R mode. CLOCK INPUT CONFIGURATIONS The clock inputs to the AD9777 can be driven differentially or single-ended. The internal clock circuitry has supply and ground (CLKVDD, CLKGND) separate from the other supplies on the chip to minimize jitter from internal noise sources. Figure 10 shows the AD9777 driven from a single-ended clock source. The CLK+/CLK– Pins form a differential input (CLKIN), so that the statically terminated input must be dc-biased to the midswing voltage level of the clock driven input. AD9777 R SERIES CLK+ CLKVDD CLK– VTHRESHOLD 0.1F CLKGND Figure 10. Single-Ended Clock Driving Clock Inputs A configuration for differentially driving the clock inputs is given in Figure 11. DC-blocking capacitors can be used to couple a clock driver output whose voltage swings exceed CLKVDD or CLKGND. If the driver voltage swings are within the supply range of the AD9777, the dc-blocking capacitors and bias resistors are not necessary. PECL/ECL drivers require varying termination networks, the details of which are left out of Figures 10 and 11 but can be found in application notes such as AND8020/D from On Semiconductor. These networks depend on the assumed transmission line impedance and power supply voltage of the clock driver. Optimum performance of the AD9777 is achieved when the driver is placed very close to the AD9777 clock inputs, thereby negating any transmission line effects such as reflections due to mismatch. The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver circuitry should provide the AD9777 with a low jitter clock input that meets the min/max logic levels while providing fast edges. Although fast clock edges help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform, the high gain bandwidth product of the AD9777’s differential comparator can tolerate sine wave inputs as low as 0.5 V p-p, with minimal degradation of the output noise floor. PROGRAMMABLE PLL CLKIN can function either as an input data rate clock (PLL enabled) or as a DAC data rate clock (PLL disabled) according to the state of Address 02h, Bit 7 in the SPI port register. The internal operation of the AD9777 clock circuitry in these two modes is illustrated in Figures 12 and 13. The PLL clock multiplier and distribution circuitry produce the necessary internal synchronized 1×, 2×, 4×, and 8× clocks for the rising edge triggered latches, interpolation filters, modulators, and DACs. This circuitry consists of a phase detector, charge pump, voltage controlled oscillator (VCO), prescaler, clock distribution, and SPI port control. The charge pump and VCO are powered from PLLVDD while the differential clock input buffer, phase detector, prescaler, and clock distribution are powered from CLKVDD. PLL lock status is indicated by the logic signal at the PLL_LOCK Pin, as well as by the status of Bit 1, Register 00h. To ensure optimum phase noise performance from the PLL clock multiplier, and distribution, PLLVDD and CLKVDD should originate from the same clean analog supply. The speed of the VCO with the PLL enabled also has an effect on phase noise. Optimal phase noise with respect to VCO speed is achieved by running the VCO in the range of 450 MHz to 550 MHz. The VCO speed is a function of the input data rate, the interpolation rate, and the VCO prescaler, according to the following function: VCO Speed ( MHz ) = Input Data Rate ( MHz ) × InterpolationRate × Prescaler –20– REV. 0 AD9777 0 CLK+ CLK– PLLVDD PLL_LOCK 1 = LOCK 0 = NO LOCK –20 4 PHASE DETECTOR CHARGE PUMP PHASE NOISE – dBFS AD9777 INTERPOLATION FILTERS, MODULATORS, AND DACS 2 –10 LPF 8 1 –40 –50 –60 –70 –80 –90 CLOCK DISTRIBUTION CIRCUITRY INPUT DATA LATCHES –30 PRESCALER VCO –100 –110 INTERPOLATION RATE CONTROL PLL_LOCK 1 = LOCK 0 = NO LOCK 4 AD9777 PHASE DETECTOR CHARGE PUMP PRESCALER VCO 8 INTERPOLATION RATE CONTROL CLOCK DISTRIBUTION CIRCUITRY PLL DIVIDER (PRESCALER) CONTROL INTERNAL SPI CONTROL REGISTERS SPI PORT 5 The AD9777 has three voltage supplies: AVDD, DVDD, and CLKVDD. Figures 15, 16, and 17 show the current required from each of these supplies when each is set to the 3.3 V nominal specified for the AD9777. Power dissipation (PD) can easily be extracted by multiplying the given curves by 3.3. As Figure 15 shows, IDVDD is very dependent on the input data rate, the interpolation rate, and the activation of the internal digital modulator. IDVDD, however, is relatively insensitive to the modulation rate by itself. In Figure 16, IAVDD shows the same type of sensitivity to data, interpolation rate, and the modulator function but to a much lesser degree (<10%). In Figure 17, ICLKVDD varies over a wide range yet is responsible for only a small percentage of the overall AD9777 supply current requirements. 1 INPUT DATA LATCHES 4 POWER DISSIPATION CLK+ CLK– 2 2 3 FREQUENCY OFFSET – MHz It is important to note that the resistor/capacitor needed for the PLL loop filter is internal on the AD9777. This will suffice unless the input data rate is below 10 MHz, in which case an external series RC is required between the LPF and PLLVDD Pins. Figure 12. PLL and Clock Circuitry with PLL Enabled INTERPOLATION FILTERS, MODULATORS, AND DACS 1 Figure 14. Phase Noise Performance PLL CONTROL (PLL ON) MODULATION RATE CONTROL SPI PORT 0 PLL DIVIDER (PRESCALER) CONTROL INTERNAL SPI CONTROL REGISTERS 400 MODULATION RATE CONTROL PLL CONTROL (PLL ON) 8, (MOD. ON) 350 4 , (MOD. ON) 2 , (MOD. ON) 300 fDATA PLL Prescaler Ratio 125 MSPS 125 MSPS 100 MSPS 75 MSPS 50 MSPS Disabled Enabled Enabled Enabled Enabled div1 div2 div2 div4 REV. 0 IDVDD – mA Figure 13. PLL and Clock Circuitry with PLL Disabled In addition, if the zero stuffing option is enabled, the VCO will double its speed again. Phase noise may be slightly higher with the PLL enabled. Figure 14 illustrates typical phase noise performance of the AD9777 with 2× interpolation and various input data rates. The signal synthesized for the phase noise measurement was a single carrier at a frequency of fDATA/4. The repetitive nature of this signal eliminated quantization noise and distortion spurs as a factor in the measurement. Although the curves blend together in Figure 14, the different conditions are called out here for clarity. 8 250 4 2 200 150 100 1 50 0 0 50 100 fDATA – MHz 150 200 Figure 15. IDVDD vs. fDATA vs. Interpolation Rate, PLL Disabled –21– AD9777 76.0 8 , (MOD. ON) ONE/TWO PORT INPUT MODES 2, (MOD. ON) The digital data input ports can be configured as two independent ports or as a single (one port mode) port. In two port mode, the AD9777 can be programmed to generate an externally available data rate clock (DATACLK) for the purpose of data synchronization. Data at the two input ports can be latched into the AD9777 on every rising clock edge of DATACLK. In one port mode, P2B14 and P2B15 from input data Port 2 are redefined as IQSEL and ONEPORTCLK, respectively. The input data in one port mode is steered to one of the two internal data channels based on the logic level of IQSEL. A clock signal, ONEPORTCLK, is generated by the AD9777 in this mode for the purpose of external data synchronization. ONEPORTCLK runs at the input interleaved data rate, which is 2× the data rate at the internal input to either channel. 75.5 4 , (MOD. ON) IAVDD – mA 75.0 74.5 8 74.0 4 2 73.5 73.0 1 72.5 72.0 0 50 100 fDATA – MHz 150 200 Test configurations showing the various clocks that are required and produced by the AD9777 in the PLL and one/two port modes are given in Figures 55 through 58. Jumper positions needed to operate the AD9777 evaluation board in these modes are given as well. Figure 16. IAVDD vs. fDATA vs. Interpolation Rate, PLL Disabled 35 2 4 25 ICLKVDD – mA PLL ENABLED, TWO PORT MODE (Control Register 02h, Bits 6–0 and 04h, Bits 7–1) 8 30 20 15 1 10 5 0 0 50 100 fDATA – MHz 150 200 Figure 17. ICLKVDD vs. fDATA vs. Interpolation Rate, PLL Disabled SLEEP/POWER-DOWN MODES (Control Register 00h, Bits 3 and 4) The AD9777 provides two methods for programmable reduction in power savings. The sleep mode, when activated, turns off the DAC output currents but the rest of the chip remains functioning. When coming out of sleep mode, the AD9777 will immediately return to full operation. Power-down mode, on the other hand, turns off all analog and digital circuitry in the AD9777 except for the SPI port. When returning from power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle. Note that optimal performance with the PLL enabled is achieved with the UCO in the PLL control loop running at 450 MHz – 550 MHz. With the phase-locked loop (PLL) enabled and the AD9777 in two port mode, the speed of CLKIN is inherently that of the input data rate. In two port mode, Pin 8 (DATACLK/PLL_ LOCK) can be programmed (Control Register 01h, Bit 0) to function as either a lock indicator for the internal PLL or as a clock running at the input data rate. When Pin 8 is used as a clock output (DATACLK), its frequency is equal to that of CLKIN. Data at the input ports is latched into the AD9777 on the rising edge of the CLKIN. Figure 18 shows the delay, tOD, inherent between the rising edge of CLKIN and the rising edge of DATACLK, as well as the setup and hold requirements for the data at Ports 1 and 2. Note that the setup and hold times given in Figure 18 are the input data transitions with respect to CLKIN. tOD can vary with CLKIN speed, PLL divider setting, and interpolation rate. It is therefore highly recommended that the input data be synchronized to CLKIN rather than DATACLK when the PLL is enabled. Note that in two port mode (PLL enabled or disabled), the data rate at the interpolation filter inputs is the same as the input data rate at Ports 1 and 2. The DAC output sample rate in two port mode is equal to the clock input rate multiplied by the interpolation rate. If zero stuffing is used, another factor of two must be included to calculate the DAC sample rate. DATACLK Inversion (Control Register 02h, Bit 4) By programming this bit, the DATACLK signal shown in Figure 18 can be inverted. With inversion enabled, tOD will refer to the time between the rising edge of CLKIN and the falling edge of DATACLK. No other effect on timing will occur. –22– REV. 0 AD9777 the data for the I or Q channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9777 is in one port mode) on the rising edge of ONEPORTCLK. IQSEL = 1 under these conditions will latch the data into the I channel on the clock rising edge, while IQSEL = 0 will latch the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic “1”). Figure 20 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in one port mode. tOD CLKIN DATACLK The DAC output sample rate in one port mode is equal to CLKIN multiplied by the interpolation rate. If zero stuffing is used, another factor of 2 must be included to calculate the DAC sample rate. DATA AT PORTS 1 AND 2 tS t S = 0.0ns t H = 2.5ns (TYP SPECS) tH ONEPORTCLK INVERSION (Control Register 02h, Bit 2) Figure 18. Timing Requirements in Two Port Input Mode with PLL Enabled DATACLK DRIVER STRENGTH (Control Register 02h, Bit 5) The DATACLK output driver strength is capable of driving >10 mA into a 330 Ω load while providing a rise time of 3 ns. Figure 19 shows DATACLK driving a 330 Ω resistive load at a frequency of 50 MHz. By enabling the drive strength option (Control Register 02h, Bit 5), the amplitude of DATACLK under these conditions will be increased by approximately 200 mV. By programming this bit, the ONEPORTCLK signal shown in Figure 20 can be inverted. With inversion enabled, tOD refers to the delay between the rising edge of the external clock and the falling edge of ONEPORTCLK. The setup and hold times, tS and tH, will be with respect to the falling edge of ONEPORTCLK. There will be no other effect on timing. ONEPORTCLK DRIVER STRENGTH The drive capability of ONEPORTCLK is identical to that of DATACLK in the two port mode. Refer to Figure 19 for performance under load conditions. tOD 3.0 tOD = 4.7ns t S = 3.0ns t H = –0.5ns tIQS = 3.5ns tIQH = –1.5ns 2.5 CLKIN FREQUENCY – V 2.0 1.5 ONEPORTCLK 1.0 0.5 0 DELTA APPROX. 2.8ns I AND Q INTERLEAVED INPUT DATA AT PORT 1 –0.5 0 10 20 30 40 50 TIME – ns Figure 19. DATACLK Driver Capability into 330 ⍀ at 50 MHz tS tH PLL ENABLED, ONE PORT MODE (Control Register 02h, Bits 6–1 and 04h, Bits 7–1) IQSEL In one port mode, the I and Q channels receive their data from an interleaved stream at digital input Port 1. The function of Pin 32 is defined as an output (ONEPORTCLK) that generates a clock at the interleaved data rate, which is 2⫻ the internal input data rate of the I and Q channels. The frequency of CLKIN is equal to the internal input data rate of the I and Q channels. The selection of REV. 0 –23– tIQS tIQH Figure 20. Timing Requirements in One Port Input Mode, with the PLL Enabled AD9777 IQ PAIRING (Control Register 02h, Bit 0) tOD In one port mode, the interleaved data is latched into the AD9777 internal I and Q channels in pairs. The order of how the pairs are latched internally is defined by this control register. The following is an example of the effect this has on incoming interleaved data. CLKIN Given the following interleaved data stream, where the data indicates the value with respect to full scale: I 0.5 Q 0.5 I 1 Q 1 I 0.5 Q 0.5 I 0 Q 0 I 0.5 DATACLK Q 0.5 With the control register set to “0” (I first), the data will appear at the internal channel inputs in the following order in time: I channel Q channel 0.5 0.5 1 1 0.5 0.5 0 0 DATA AT PORTS 1 AND 2 0.5 0.5 tS With the control register set to “1” (Q first), the data will appear at the internal channel inputs in the following order in time: I channel Q channel 0.5 y 1 0.5 0.5 1 0 0.5 0.5 0 x 0.5 PLL DISABLED, TWO PORT MODE With the PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal clock dividers in the AD9777 synthesize the DATACLK signal at Pin 8, which runs at the input data rate and can be used to synchronize the input data. Data is latched into input Ports 1 and 2 of the AD9777 on the rising edge of DATACLK. DATACLK speed is defined as the speed of CLKIN divided by the interpolation rate. With zero stuffing enabled, this division increases by a factor of 2. Figure 21 illustrates the delay between the rising edge of CLKIN and the rising edge of DATACLK, as well as tS and tH in this mode. As described earlier in the PLL-Enabled Mode section, tOD can vary depending on CLKIN frequency and interpolation rate. However, with the PLL disabled, the input data latches are closely synchronized to DATACLK so that it is recommended in this mode that the input data be timed from DATACLK, not CLKIN. t S = 5.0ns t H = –3.2ns (TYP SPECS) Figure 21. Timing Requirements in Two Port Input Mode, with PLL Disabled PLL DISABLED, ONE PORT MODE The values x and y represent the next I value and the previous Q value in the series. The programmable modes DATACLK inversion and DATACLK driver strength described in the previous section (PLL Enabled, Two Port Mode) have identical functionality with the PLL disabled. tH In one port mode, data is received into the AD9777 as an interleaved stream on Port 1. A clock signal (ONEPORTCLK), running at the interleaved data rate, which is 2× the input data rate of the internal I and Q channels is available for data synchronization at Pin 32. With PLL disabled, a clock at the DAC output rate must be applied to CLKIN. Internal dividers synthesize the ONEPORTCLK signal at Pin 32. The selection of the data for the I or Q channel is determined by the state of the logic level applied to Pin 31 (IQSEL when the AD9777 is in one port mode) on the rising edge of ONEPORTCLK. IQSEL = 1 under these conditions will latch the data into the I channel on the clock rising edge, while IQSEL = 0 will latch the data into the Q channel. It is possible to invert the I and Q selection by setting Control Register 02h, Bit 1 to the invert state (Logic “1”). Figure 22 illustrates the timing requirements for the data inputs as well as the IQSEL input. Note that the 1× interpolation rate is not available in the one port mode. One port mode is very useful when interfacing with devices such as Analog Devices’ AD6622 or AD6623 transmit signal processors, in which two digital data channels have been interleaved (multiplexed). –24– REV. 0 AD9777 The programmable modes’ ONEPORTCLK inversion, ONEPORTCLK driver strength, and IQ pairing described in the previous section (PLL Enabled, One Port Mode) have identical functionality with the PLL disabled. AMPLITUDE MODULATION Given two sine waves at the same frequency, but with a 90 phase difference, a point of view in time can be taken such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal. Analysis of complex variables states that the cosine waveform can be defined as having real positive and negative frequency components, while the sine waveform consists of imaginary positive and negative frequency images. This is shown graphically in the frequency domain in Figure 23. tOD CLKIN e–jt/2j SINE ONEPORTCLK DC e–jt/2j e–jt /2 e–jt /2 COSINE I AND Q INTERLEAVED INPUT DATA AT PORT 1 DC Figure 23. Real and Imaginary Components of Sinusoidal and Cosinusoidal Waveforms tS tH tOD = 4.7ns t S = 3.0ns t H = –1.0ns tIQS = 3.5ns tIQH = –1.5ns Amplitude modulating a baseband signal with a sine or a cosine convolves the baseband signal with the modulating carrier in the frequency domain. Amplitude scaling of the modulated signal reduces the positive and negative frequency images by a factor of two. This scaling will be very important in the discussion of the various modulation modes. The phase relationship of the modulated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, again with respect to the reference point of the viewer. Examples of sine and cosine modulation are given in Figure 24. IQSEL tIQS tIQH (TYP SPECS) Figure 22. Timing Requirements in One Port Input Mode, with PLL Disabled DIGITAL FILTER MODES The I and Q data paths of the AD9777 have their own independent half-band FIR filters. Each data path consists of three FIR filters, providing up to 8× interpolation for each channel. The rate of interpolation is determined by the state of Control Register 01h, Bits 7 and 6. Figures 1a–1c show the response of the digital filters when the AD9777 is set to 2×, 4×, and 8× modes. The frequency axes of these graphs have been normalized to the input data rate of the DAC. As the graphs show, the digital filters can provide greater than 75 dB of out-of-band rejection. An online tool is available for quick and easy analysis of the AD9777 interpolation filters in the various modes. The link can be accessed at: www.analog.com/techSupport/designTools/ interactiveTools/dac/ad9777image.html. REV. 0 Ae–jt/2j SINUSOIDAL MODULATION DC Ae–jt/2j Ae–jt /2 Ae–jt /2 COSINUSOIDAL MODULATION DC Figure 24. Baseband Signal, Amplitude Modulated with Sine and Cosine Carriers –25– AD9777 MODULATION, NO INTERPOLATION narrow bandwidth. By comparing the digital domain spectrum to the DAC SIN(x)/x roll-off, an estimate can be made for the characteristics required for the DAC reconstruction filter. Note also, per the previous discussion on amplitude modulation, that the spectral components (where modulation is set to fS/4 or fS/8) are scaled by a factor of 2. In the situation where the modulation is fS/2, the modulated spectral components add constructively and there is no scaling effect. 0 0 –20 –20 AMPLITUDE – dBFS AMPLITUDE – dBFS With Control Register 01h, Bits 7 and 6 set to “00,” the interpolation function on the AD9777 is disabled. Figures 25a–25d show the DAC output spectral characteristics of the AD9777 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 01h, Bits 5 and 4. The tall rectangles represent the digital domain spectrum of a baseband signal of –40 –60 –40 –60 –80 –80 –100 –100 0 0.2 0.4 0.6 0.8 1.0 0 0.2 fOUT (fDATA) 0.6 0.8 1.0 fOUT (fDATA) Figure 25a. No Interpolation, Modulation Disabled Figure 25c. No Interpolation, Modulation = fDAC/4 0 0 –20 –20 AMPLITUDE – dBFS AMPLITUDE – dBFS 0.4 –40 –60 –40 –60 –80 –80 –100 –100 0 0.2 0.4 0.6 0.8 1.0 0 fOUT (fDATA) 0.2 0.4 0.6 0.8 1.0 fOUT (fDATA) Figure 25b. No Interpolation, Modulation = fDAC/2 Figure 25d. No Interpolation, Modulation = fDAC/8 Figure 25. Effects of Digital Modulation on DAC Output Spectrum, Interpolation Disabled –26– REV. 0 AD9777 MODULATION, INTERPOLATION = 2× input data rate frequency are suppressed by >70 dB. Another significant point is that the interpolation filtering is done previous to the digital modulator. For this reason, as Figures 26a–26d show, the pass band of the interpolation filters can be frequency shifted, giving the equivalent of a high-pass digital filter. Note that when using the fS/4 modulation mode, there is no true stop band as the band edges coincide with each other. In the fS/8 modulation mode, amplitude scaling occurs over only a portion of the digital filter pass band due to constructive addition over just that section of the band. 0 0 –20 –20 AMPLITUDE – dBFS AMPLITUDE – dBFS With Control Register 01h, Bits 7 and 6 set to “01,” the interpolation rate of the AD9777 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (1, –1). Figures 26a–26d represent the spectral response of the AD9777 DAC output with 2× interpolation in the various modulation modes to a narrow band baseband signal (again, the tall rectangles in the graphic). The advantage of interpolation becomes clear in Figures 26a–26d, where it can be seen that the images that would normally appear in the spectrum around the –40 –60 –40 –60 –80 –80 –100 –100 0 0.5 1.0 1.5 0 2.0 0.5 1.5 0 –20 –20 AMPLITUDE – dBFS 0 –40 –60 –40 –60 –80 –80 –100 –100 0 0.5 1.0 1.5 0 2.0 0.5 1.0 1.5 2.0 fOUT (fDATA) fOUT (fDATA) Figure 26d. 2 × Interpolation, Modulation = fDAC/8 Figure 26b. 2 × Interpolation, Modulation = fDAC/2 Figure 26. Effects of Digital Modulation on DAC Output Spectrum, Interpolation = 2 × REV. 0 2.0 Figure 26c. 2 × Interpolation, Modulation = fDAC/4 Figure 26a. 2 × Interpolation, Modulation = Disabled AMPLITUDE – dBFS 1.0 fOUT (fDATA) fOUT (fDATA) –27– AD9777 MODULATION, INTERPOLATION = 4× by the sequence (0, 1, 0, –1). Figures 27a–27d represent the spectral response of the AD9777 DAC output with 4× interpolation in the various modulation modes to a narrow band baseband signal. 0 0 –20 –20 AMPLITUDE – dBFS AMPLITUDE – dBFS With Control Register 01h, Bits 7 and 6 set to “10,” the interpolation rate of the AD9777 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output –40 –60 –80 –40 –60 –80 –100 –100 0 1 2 3 0 4 1 fOUT (fDATA) Figure 27a. 4 × Interpolation, Modulation Disabled 3 4 Figure 27c. 4 × Interpolation, Modulation = fDAC/4 0 0 –20 –20 AMPLITUDE – dBFS AMPLITUDE – dBFS 2 fOUT (fDATA) –40 –60 –80 –40 –60 –80 –100 –100 0 1 2 3 0 4 fOUT (fDATA) 1 2 3 4 fOUT (fDATA) Figure 27b. 4 × Interpolation, Modulation = fDAC/2 Figure 27d. 4 × Interpolation, Modulation = fDAC/8 Figure 27. Effect of Digital Modulation on DAC Output Spectrum, Interpolation = 4 × –28– REV. 0 AD9777 Looking at Figures 26 through 29, the user can see how higher interpolation rates reduce the complexity of the reconstruction filter needed at the DAC output. It also becomes apparent that the ability to modulate by fS/2, fS/4, or fS/8 adds a degree of flexibility in frequency planning. MODULATION, INTERPOLATION = 8× 0 0 –20 –20 AMPLITUDE – dBFS AMPLITUDE – dBFS With Control Register 01h, Bits 7 and 6, set to “11,” the interpolation rate of the AD9777 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, 0.707, 1, 0.707, 0, –0.707, –1, 0.707). Figures 28a–28d represent the spectral response of the AD9777 DAC output with 8× interpolation in the various modulation modes to a narrow band baseband signal. –40 –60 –40 –60 –80 –80 –100 –100 0 1 2 3 0 4 1 2 3 5 6 7 8 Figure 28c. 8 × Interpolation, Modulation = fDAC/4 Figure 28a. 8 × Interpolation, Modulation Disabled 0 0 –20 –20 AMPLITUDE – dBFS AMPLITUDE – dBFS 4 fOUT (f DATA) fOUT (fDATA) –40 –60 –40 –60 –80 –80 –100 –100 0 1 2 3 0 4 1 2 3 4 5 6 7 8 fOUT (fDATA) fOUT (fDATA) Figure 28d. 8 × Interpolation, Modulation = fDAC/8 Figure 28b. 8 × Interpolation, Modulation = fDAC/2 Figure 28. Effect of Digital Modulation on DAC Output Spectrum, Interpolation = 8 × ZERO STUFFING (Control Register 01h, Bit 3) As shown in Figure 29, a “0” or null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (fDAC). This is due to the inherent SIN(x)/x roll-off response in the digitalto-analog conversion. In applications where the desired frequency content is below fDAC/2, this may not be a problem. Note that at fDAC/2 the loss due to SIN(x)/x is 4 dB. In direct RF applications, this roll-off may be problematic due to the increased pass-band amplitude variation as well as the reduced amplitude of the desired signal. REV. 0 Consider an application where the digital data into the AD9777 represents a baseband signal around fDAC/4 with a pass band of fDAC/10. The reconstructed signal out of the AD9777 would experience only a 0.75 dB amplitude variation over its passband. However, the image of the same signal occurring at 3 × fDAC/4 will suffer from a pass-band flatness variation of 3.93 dB. This image may be the desired signal in an IF application using one of the various modulation modes in the AD9777. This roll-off of image frequencies can be seen in Figures 25 through 28, where the effect of the interpolation and modulation rate is apparent as well. –29– AD9777 If a complex modulation function (e+jt) is desired, the real and imaginary components of the system correspond to the real and imaginary components of e+jt, or cost and sint. As Figure 31 shows, the complex modulation function can be realized by applying these components to the structure of the complex system defined in Figure 30. 10 ZERO STUFFING ENABLED SIN (X)/X ROLL-OFF – dBFS 0 –10 –20 a(t) ZERO STUFFING DISABLED –30 b(t) –50 0.5 OUTPUT c(t) b(t) + d b(t) COMPLEX FILTER = (c + jd) –40 0 INPUT 1.0 1.5 IMAGINARY OUTPUT INPUT b(t) a(t) + c b(t) Figure 30. Realization of a Complex System 2.0 fOUT, NORMALIZED TO fDATA WITH ZERO STUFFING DISABLED – Hz Figure 29. Effect of Zero Stuffing on DAC’s SIN(x)/x Response To improve upon the pass-band flatness of the desired image, the zero stuffing mode can be enabled by setting the control register bit to a Logic “1.” This option increases the ratio of fDAC/fDATA by a factor of 2 by doubling the DAC sample rate and inserting a midscale sample (i.e., 1000 0000 0000 0000) after every data sample originating from the interpolation filter. This is important as it will affect the PLL divider ratio needed to keep the VCO within its optimum speed range. Note that the zero stuffing takes place in the digital signal chain at the output of the digital modulator, before the DAC. INPUT (REAL) INPUT (IMAGINARY) OUTPUT (REAL) 90 OUTPUT (IMAGINARY) e–jt = COSt + jSINt Figure 31. Implementation of a Complex Modulator COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS The net effect is to increase the DAC output sample rate by a factor of 2× with the “0” in the SIN(x)/x DAC transfer function occurring at twice the original frequency. A 6 dB loss in amplitude at low frequencies is also evident, as can be seen in Figure 30. It is important to realize that the zero stuffing option by itself does not change the location of the images but rather their amplitude, pass-band flatness, and relative weighting. For instance, in the previous example, the pass-band amplitude flatness of the image at 3 × fDATA/4 is now improved to 0.59 dB while the signal level has increased slightly from –10.5 dBFS to –8.1 dBFS. INTERPOLATING (COMPLEX MIX MODE) (Control Register 01h, Bit 2) In the complex mix mode, the two digital modulators on the AD9777 are coupled to provide a complex modulation function. In conjunction with an external quadrature modulator, this complex modulation can be used to realize a transmit image rejection architecture. The complex modulation function can be programmed for e+jt or e–jt to give upper or lower image rejection. As in the real modulation mode, the modulation frequency can be programmed via the SPI port for fDAC/2, fDAC/4, and fDAC/8, where fDAC represents the DAC output rate. In traditional transmit applications, a two-step upconversion is done in which a baseband signal is modulated by one carrier to an IF (intermediate frequency) and then modulated a second time to the transmit frequency. Although this approach has several benefits, a major drawback is that two images are created near the transmit frequency. Only one image is needed, the other being an exact duplicate. Unless the unwanted image is filtered, typically with analog components, transmit power is wasted and the usable bandwidth available in the system is reduced. A more efficient method of suppressing the unwanted image can be achieved by using a complex modulator followed by a quadrature modulator. Figure 32 is a block diagram of a quadrature modulator. Note that it is in fact the real output half of a complex modulator. The complete upconversion can actually be referred to as two complex upconversion stages, the real output of which becomes the transmitted signal. INPUT (REAL) INPUT (IMAGINARY) SINt OPERATIONS ON COMPLEX SIGNALS Truly complex signals cannot be realized outside of a computer simulation. However, two data channels, both consisting of real data, can be defined as the real and imaginary components of a complex signal. I (real) and Q (imaginary) data paths are often defined this way. By using the architecture defined in Figure 30, a system that operates on complex signals can be realized, giving a complex (real and imaginary) output. –30– OUTPUT 90 COSt Figure 32. Quadrature Modulator REV. 0 AD9777 The entire upconversion from baseband to transmit frequency is represented graphically in Figure 33. The resulting spectrum shown in Figure 33 represents the complex data consisting of the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit frequency. It is important to remember that in this application (two baseband data channels), the image rejection is not dependent on the data at either of the AD9777 input channels. In fact, image rejection will still occur with either one or both of the AD9777 input channels active. Note that by changing the sign of the sinusoidal multiplying term in the complex modulator, the upper sideband image could have been suppressed while passing the lower one. This is easily done in the AD9777 by selecting the e+jt bit (Register 01h, Bit 1). In purely complex terms, Figure 31 represents the two-stage upconversion from complex baseband to carrier. REAL CHANNEL (OUT) A/2 A/2 –FC* FC –B/2J B/2J –FC FC REAL CHANNEL (IN) A DC COMPLEX MODULATOR TO QUADRATURE MODULATOR IMAGINARY CHANNEL (OUT) –A/2J A/2J –FC –FC B/2 B/2 –FC FC IMAGINARY CHANNEL (IN) B DC *FC = COMPLEX MODULATION FREQUENCY *FQ = QUADRATURE MODULATION FREQUENCY A/4 + B/4J A/4 – B/4J A/4 + B/4J A/4 – B/4J –FQ* –FQ – FC FQ –FQ + FC FQ – FC FQ + FC OUT REAL –A/4 – B/4J A/4 – B/4J A/4 + B/4J –A/4 + B/4J QUADRATURE MODULATOR –FQ IMAGINARY FQ REJECTED IMAGES A/2 + B/2J –FQ A/2 – B/2J FQ Figure 33. Two-Stage Upconversion and Resulting Image Rejection REV. 0 –31– AD9777 complex carriers are then summed and applied to the real and imaginary inputs of the AD9777. A system in which multiple baseband signals are complex modulated and then applied to the AD9777 real and imaginary inputs, followed by a quadrature modulator is shown in Figure 36, which also describes the transfer function of this system and the spectral output. Note the similarity of the transfer functions given in Figure 36 and Figure 34. Figure 36 adds an additional complex modulator stage for the purpose of summing multiple carriers at the AD9777 inputs. Also, as in Figure 33, the image rejection is not dependent on the real or imaginary baseband data on any channel. Image rejection on a channel will occur if either the real or imaginary data, or both, is present on the baseband channel. COMPLEX BASEBAND SIGNAL 1 OUTPUT = REAL ej(1 + 2)t 1/2 = REAL –1 – 2 1/2 1 + 2 FREQUENCY DC Figure 34. Two-Stage Complex Upconversion IMAGE REJECTION AND SIDEBAND SUPPRESSION OF MODULATED CARRIERS As shown in Figure 33, image rejection can be achieved by applying baseband data to the AD9777 and following the AD9777 with a quadrature modulator. To process multiple carriers while still maintaining image reject capability, each carrier must be complex modulated. As Figure 34 shows, single- or multiple-complex modulators can be used to synthesize complex carriers. These BASEBAND CHANNEL 1 REAL INPUT R(1) COMPLEX MODULATOR 1 IMAGINARY INPUT BASEBAND CHANNEL 2 REAL INPUT It is important to remember that the magnitude of a complex signal can be 1.414× the magnitude of its real or imaginary components. Due to this 3 dB increase in signal amplitude, the real and imaginary inputs to the AD9777 must be kept at least 3 dB below full scale when operating with the complex modulator. Overranging in the complex modulator will result in severe distortion at the DAC output. MULTICARRIER REAL OUTPUT = R(1) + R(2) +...R(N) (TO REAL INPUT OF AD9777) R(1) R(2) COMPLEX MODULATOR 2 IMAGINARY INPUT MULTICARRIER IMAGINARY OUTPUT = I(1) + I(2) +...I(N) (TO IMAGINARY INPUT OF AD9777) R(2) BASEBAND CHANNEL N REAL INPUT R(N) = REAL OUTPUT OF N I(N) = IMAGINARY OUTPUT OF N R(N) COMPLEX MODULATOR N R(N) IMAGINARY INPUT Figure 35. Synthesis of Multicarrier Complex Signal MULTIPLE BASEBAND CHANNELS REAL IMAGINARY MULTIPLE COMPLEX MODULATORS FREQUENCY = 1, 2...N REAL AD9777 COMPLEX MODULATOR FREQUENCY = C IMAGINARY REAL IMAGINARY REAL QUADRATURE MODULATOR FREQUENCY = Q COMPLEX BASEBAND SIGNAL ej(N + C + Q)t OUTPUT = REAL –1 – C – Q 1 + C + Q DC REJECTED IMAGES Figure 36. Image Rejection with Multicarrier Signals –32– REV. 0 AD9777 The complex carrier synthesized in the AD9777 digital modulator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running at fDAC/2. As a result, complex modulation only functions with modulation rates of fDAC/4 and fDAC/8. Regions A and B of Figures 37 through 42 are the result of the complex signal described above, when complex modulated in the AD9777 by +ejt. Regions C and D are the result of the complex signal described above, again with positive frequency components only, modulated in the AD9777 by –ejt. The analog quadrature modulator after the AD9777 inherently modulates by +ejt. Region A Region A is a direct result of the upconversion of the complex signal near baseband. If viewed as a complex signal, only the images in Region A will remain. The complex Signal A, consisting of positive frequency components only in the digital domain, has images in the positive odd Nyquist zones (1, 3, 5...) as well as images in the negative even Nyquist zones. The appearance and rejection of images in every other Nyquist zone will become more apparent at the output of the quadrature modulator. The A images will appear on the real and the imaginary outputs of the AD9777, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator LO and the horizontal scale now represents the frequency offset from this LO. Region B Region B is the image (complex conjugate) of Region A. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9777, Region B will appear in the spectrum. However, on the output of the quadrature modulator, Region B will be rejected. REV. 0 Region C Region C is most accurately described as a down conversion, as the modulating carrier is –ejt. If viewed as a complex signal, only the images in Region C will remain. This image will appear on the real and imaginary outputs of the AD9777, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator LO and the horizontal scale will represent the frequency offset from this LO. Region D Region D is the image (complex conjugate) of Region C. If a spectrum analyzer is used to view the real or imaginary DAC outputs of the AD9777, Region D will appear in the spectrum. However, on the output of the quadrature modulator, Region D will be rejected. Figures 43 through 50 show the measured response of the AD9777 and AD8345 given the complex input signal to the AD9777 in Figure 43. The data in these graphs was taken with a data rate of 12.5 MSPS at the AD9777 inputs. The interpolation rate of 4× or 8× gives a DAC output data rate of 50 MSPS or 100 MSPS. As a result, the high end of the DAC output spectrum in these graphs is the first null point for the SIN(x)/x roll-off, and the asymmetry of the DAC output images is representative of the SIN(x)/x roll-off over the spectrum. The internal PLL was enabled for these results. In addition, a 35 MHz third order low-pass filter was used at the AD9777/AD8345 interface to suppress DAC images. An important point can be made by looking at Figures 45 and 47. Figure 45 represents a group of positive frequencies modulated by complex +fDAC/4, while Figure 47 represents a group of negative frequencies modulated by complex –fDAC/4. When looking at the real or imaginary outputs of the AD9777, as shown in Figures 45 and 47, the results look identical. However, the spectrum analyzer cannot show the phase relationship of these signals. The difference in phase between the two signals becomes apparent when they are applied to the AD8345 quadrature modulator, with the results shown in Figures 46 and 48. –33– AD9777 0 0 –20 –20 D A B C D A B C –40 –40 –60 –60 –80 –80 D –100 –2.0 –1.5 –1.0 –0.5 0 0.5 (LO) fOUT (fDATA) 1.0 1.5 –100 –2.0 2.0 Figure 37. 2 × Interpolation, Complex fDAC/4 Modulation A –1.5 B –1.0 A –0.5 0 0.5 (LO) fOUT (fDATA) B 1.0 C 1.5 2.0 Figure 40. 2 × Interpolation, Complex fDAC/8 Modulation 0 0 –20 –20 D A B C D A B C –40 –40 –60 –60 –80 –80 D A –100 –4.0 –3.0 –2.0 –1.0 0 1.0 (LO) fOUT (fDATA) 2.0 3.0 –100 –4.0 4.0 0 0 –20 –20 D A B C D A B –40 –60 –60 –80 –80 –4.0 –2.0 0 2.0 (LO) fOUT (fDATA) 4.0 6.0 –2.0 D A C –40 –6.0 –3.0 B C D A –1.0 0 1.0 (LO) fOUT (fDATA) B 2.0 C 3.0 4.0 Figure 41. 4 × Interpolation, Complex fDAC/8 Modulation Figure 38. 4 × Interpolation, Complex fDAC/4 Modulation –100 –8.0 CD –100 –8.0 8.0 –6.0 B C –4.0 –2.0 D A 0 2.0 (LO) fOUT (fDATA) B C 4.0 6.0 8.0 Figure 42. 8 × Interpolation, Complex fDAC/8 Modulation Figure 39. 8 × Interpolation, Complex fDAC/4 Modulation –34– REV. 0 0 0 –10 –10 –20 –20 –30 –30 AMPLITUDE – dBm AMPLITUDE – dBm AD9777 –40 –50 –60 –60 –70 –80 –80 –90 –90 –100 0 30 20 FREQUENCY – MHz 10 40 50 Figure 43. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 4, No Modulation in AD9777 0 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –70 –70 –90 780 790 800 810 820 FREQUENCY – MHz 830 840 50 –60 –80 770 40 –50 –90 760 20 30 FREQUENCY – MHz 10 –40 –80 –100 750 0 Figure 45. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 4, Complex Modulation in AD9777 = +fDAC/4 AMPLITUDE – dBm AMPLITUDE – dBm –50 –70 –100 –100 750 850 Figure 44. AD9777 Complex Output from Figure 43, Now Quadrature Modulated by AD8345 (LO = 800 MHz) REV. 0 –40 760 770 780 790 800 810 820 FREQUENCY – MHz 830 840 850 Figure 46. AD9777 Complex Output from Figure Figure 45, Now Quadrature Modulated by AD8345 (LO = 800 MHz) –35– 0 0 –10 –10 –20 –20 –30 –30 AMPLITUDE – dBm AMPLITUDE – dBm AD9777 –40 –50 –60 –70 –50 –60 –70 –80 –80 –90 –90 –100 –100 0 20 30 FREQUENCY – MHz 10 40 0 50 0 –10 –10 –20 –20 –30 –30 AMPLITUDE – dBm 0 –40 –50 –60 –70 100 80 –40 –50 –60 –70 –80 –80 –90 –90 –100 750 60 40 FREQUENCY – MHz 20 Figure 49. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 8, Complex Modulation in AD9777 = +fDAC/8 Figure 47. AD9777, Real DAC Output of Complex Input Signal Near Baseband (Negative Frequencies Only), Interpolation = 4, Complex Modulation in AD9777 = –fDAC/4 AMPLITUDE – dBm –40 760 770 780 790 800 810 820 FREQUENCY – MHz 830 840 –100 700 850 720 740 760 780 800 820 840 FREQUENCY – MHz 860 880 900 Figure 50. AD9777 Complex Output from Figure 49, Now Quadrature Modulated by AD8345 (LO = 800 MHz) Figure 48. AD9777 Complex Output from Figure 47, Now Quadrature Modulated by AD8345 (LO = 800 MHz) –36– REV. 0 AD9777 APPLYING THE AD9777 OUTPUT CONFIGURATIONS DIFFERENTIAL COUPLING USING A TRANSFORMER The following sections illustrate typical output configurations for the AD9777. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring optimum dynamic performance, a differential output configuration is suggested. A simple differential output may be achieved by converting IOUTA and IOUTB to a voltage output by terminating them to AGND via equal value resistors. This type of configuration may be useful when driving a differential voltage input device such as a modulator. If a conversion to a single-ended signal is desired and the application allows for ac-coupling, an RF transformer may be useful; if power gain is required, an op amp may be used. The transformer configuration provides optimum high frequency noise and distortion performance. The differential op amp configuration is suitable for applications requiring dccoupling, signal gain, and/or level shifting within the bandwidth of the chosen op amp. An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 52. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s pass band. An RF transformer, such as the Mini-Circuits T1-1T, provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if I OUTA and/or I OUTB is connected to a load resistor, RLOAD, referred to AGND. This configuration is most suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best DAC dc linearity as IOUTA or IOUTB are maintained at ground or virtual ground. UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT CIRCUIT In many applications, it may be necessary to understand the equivalent DAC output circuit. This is especially useful when designing output filters or when driving inputs with finite input impedances. Figure 51 illustrates the output of the AD9777 and the equivalent circuit. A typical application where this informatWn may be useful is when designing an interface filter between the AD9777 and Analog Devices’ AD8345 quadrature modulator. IOUTA VOUT+ IOUTB VOUT– RA + RB VSOURCE = IOUTFS (RA + RB) p-p IOUTA RLOAD DAC IOUTB Figure 52. Transformer-Coupled Output Circuit The center tap on the primary side of the transformer must be connected to AGND to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around AGND and should be maintained within the specified output compliance range of the AD9777. A differential resistor, RDIFF, may be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF. DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential-to-singleended conversion as shown in Figure 53. This has the added benefit of providing signal gain as well. In Figure 53, the AD9777 is configured with two equal load resistors, RLOAD, of 25 Ω. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp’s distortion performance by preventing the DAC’s fast slewing output from overloading the input of the op amp. 500 VOUT (DIFFERENTIAL) IOUTA AD8021 COPT 225 AVDD For the typical situation, where IOUTFS = 20 mA and RA and RB both equal 50 Ω, the equivalent circuit values become: 25 VSOURCE = 2 V p-p ROUT = 100 Ω Note that the output impedance of the AD9777 DAC itself is greater than 100 kΩ and typically has no effect on the impedance of the equivalent output circuit. 225 DAC IOUTB Figure 51. DAC Output Equivalent Circuit REV. 0 MINI-CIRCUITS T1-T2 25 500 ROPT 225 Figure 53. Op Amp-Coupled Output Circuit The common-mode (and second order distortion) rejection of this configuration is typically determined by the resistor matching. The op amp used must operate from a dual supply since its output is approximately ± 1.0 V. A high speed amplifier, such as the AD8021, capable of preserving the differential performance of the –37– AD9777 AD9777 while meeting other system level objectives (i.e., cost, power) is recommended. The op amp’s differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. ROPT is only necessary if level shifting is required on the op amp output. In Figure 53, AVDD, which is the positive analog supply for both the AD9777 and the op amp, is also used to level shift the differential output of the AD9777 to midsupply (i.e., AVDD/2). 0 –10 AMPLITUDE – dBm –20 INTERFACING THE AD9777 WITH THE AD8345 QUADRATURE MODULATOR –30 –40 –50 –60 –70 –80 The AD9777 architecture was defined to operate in a transmit signal chain using an image reject architecture. A quadrature modulator is also required in this application and should be designed to meet the output characteristics of the DAC as much as possible. The AD8345 from Analog Devices meets many of the requirements for interfacing with the AD9777. As with any DAC output interface, there are a number of issues that have to be resolved. Among the major issues are the following. –90 –100 762.5 782.5 802.5 FREQUENCY – MHz 822.5 842.5 Figure 54. AD9777/AD8345 Synthesizing a Three Carrier WCDMA Signal at an LO of 800 MHz EVALUATION BOARD DAC Compliance Voltage/Input Common-Mode Range The AD9777 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from either Win95® or Win98®. The evaluation board also contains an AD8345 quadrature modulator and support circuitry that allows the user to optimally configure the AD9777 in an image reject transmit signal chain. The dynamic range of the AD9777 is optimal when the DAC outputs swing between ± 1.0 V. The input common-mode range of the AD8345, at 0.7 V, allows optimum dynamic range to be achieved in both components. Gain/Offset Adjust The matching of the DAC output to the common-mode input of the AD8345 allows the two components to be dc-coupled, with no level shifting necessary. The combined voltage offset of the two parts can therefore be compensated for via the AD9777 programmable offset adjust. This allows excellent LO cancellation at the AD8345 output. The programmable gain adjust allows for optimal image rejection as well. Figures 55 through 58 describe how to configure the evaluation board in the one and two port input modes with the PLL enabled and disabled. Refer to Figures 59 through 68, the schematics, and the layout for the AD9777 evaluation board for the jumper locations described below. The AD9777 outputs can be configured for various applications by referring to the following instructions. The AD9777 evaluation board includes an AD8345 and recommended interface (Figures 59 and 60). On the output of the AD9777, R9 and R10 convert the DAC output current to a voltage. R16 may be used to do a slight common-mode shift if necessary. The (now voltage) signal is applied to a low pass reconstruction filter to reject DAC images. The components installed on the AD9777 provide a 35 MHz cutoff, but may be changed to fit the application. A balun (Mini-Circuits ADTL1-12) is used to cross the ground plane boundary to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is used to couple the LO input of the AD8345. The interface requires a low ac impedance return path from the AD8345, so a single connection between the AD9777 and AD8345 ground planes is recommended. The performance of the AD9777 and AD8345 in an image reject transmitter, reconstructing three WCDMA carriers, can be seen in Figure 54. The LO of the AD8345 in this application is 800 MHz. Image rejection (50 dB) and LO feedthrough (–78 dBFS) have been optimized with the programmable features of the AD9777. The average output power of the digital waveform for this test was set to –15 dBFS to account for the peak-to-average ratio of the WCDMA signal. DAC Single-Ended Outputs Remove transformers T2 and T3. Solder jumper link JP4 or JP28 to look at the DAC1 outputs. Solder jumper link JP29 or JP30 to look at the DAC2 outputs. Jumpers 8 and 13–17 should remain unsoldered. The jumpers JP35–JP38 may be used to ground one of the DAC outputs while the other is measured single-ended. Optimum single-ended distortion performance is typically achieved in this manner. The outputs are taken from S3 and S4. DAC Differential Outputs Transformers T2 and T3 should be in place. Note that the lower band of operation for these transformers is 300 kHz to 500 kHz. Jumpers 4, 8, 13–17, and 28–30 should remain unsoldered. The outputs are taken from S3 and S4. Using the AD8345 Remove transformers T2 and T3. Jumpers JP4 and 28–30 should remain unsoldered. Jumpers 13–16 should be soldered. The desired components for the low pass interface filters L6, L7, C55, and C81 should be in place. The LO drive is connected to the AD8345 via J10 and the balun T4, and the AD8345 output is taken from J9. Win95 and Win98 are a registered trademarks of Microsoft Corporation. –38– REV. 0 AD9777 LECROY TRIG PULSE INP GENERATOR SIGNAL GENERATOR DATACLK INPUT CLOCK AWG2021 OR DG2020 CLK+/CLK– 40-PIN RIBBON CABLE DAC1, DB11–DB0 DAC2, DB11–DB0 AD9777 JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON JP1 JP2 – JP3 – JP5 – JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – SOLDERED/IN UNSOLDERED/OUT Figure 55. Test Configuration for AD9777 in Two Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate, DAC Output Data Rate = Signal Generator Frequency Interpolation Rate LECROY TRIG PULSE INP GENERATOR SIGNAL GENERATOR ONEPORTCLK INPUT CLOCK CLK+/CLK– AD9777 AWG2021 OR DG2020 DAC1, DB11–DB0 DAC2, DB11–DB0 JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON JP1 – JP2 – JP3 – JP5 – JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – SOLDERED/IN UNSOLDERED/OUT Figure 56. Test Configuration for AD9777 in One Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency Interpolation Rate REV. 0 –39– AD9777 LECROY TRIG PULSE INP GENERATOR SIGNAL GENERATOR DATACLK INPUT CLOCK AWG2021 OR DG2020 CLK+/CLK– 40-PIN RIBBON CABLE DAC1, DB11–DB0 DAC2, DB11–DB0 AD9777 JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF JP1 – JP2 – JP3 – JP5 – JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – SOLDERED/IN UNSOLDERED/OUT Figure 57. Test Configuration for AD9777 in Two Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, DATACLK = Signal Generator Frequency/Interpolation Rate LECROY TRIG PULSE INP GENERATOR SIGNAL GENERATOR ONEPORTCLK INPUT CLOCK CLK+/CLK– AD9777 AWG2021 OR DG2020 DAC1, DB11–DB0 DAC2, DB11–DB0 JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON JP1 – JP2 – JP3 – JP5 – JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – SOLDERED/IN UNSOLDERED/OUT Figure 58. Test Configuration for AD9777 in One Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, ONEPORTCLK = Interleaved Input Data Rate = 2 Signal Generator Frequency/Interpolation Rate –40– REV. 0 AD9777 O1N O1P C54 DNP L4 DNP C73 DNP 3 4 S P 1 R37 DNP 6 R35 51 J20 C80 DNP C77 100pF 1 C78 0.1F 3 S 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 4 3 S P 6 1 R33 51 J19 R34 DNP VDDMIN P 5 4 R30 DNP J7 JP18 R26 1k C74 100pF R28 LOCAL OSC INPUT 0 J10 DGND; 3, 4, 5 R23 0 MODULATED OUTPUT J10 DGND; 3, 4, 5 POWER INPUT FILTERS W11 VDDMIN L8 FERRITE VDDM C28 22F 16V C32 0.1F W12 TP2 RED J8 J5 DVDD_IN L3 FERRITE J9 DVDD AGND C65 22F 16V C66 22F 16V C67 0.1F TP3 BLK TP4 RED J4 J6 AVDD_IN J10 L2 FERRITE AVDD AGND C64 22F 16V C61 22F 16V C68 0.1F TP5 BLK TP6 RED J3 J7 CLKVDD_IN J11 L1 FERRITE CLKVDD AGND C63 22F 16V C69 0.1F C62 22F 16V TP7 BLK Figure 59. AD8345 Circuitry on AD9777 Evaluation Board REV. 0 –41– L6 DNP C81 DNP T5 ADTL1-12 T4 ETC1-1-13 J21 L7 DNP C75 0.1F C78 0.1F T6 ADTL1-12 O2N C55 DNP C35 10F L5 DNP R36 51 O2P C72 10F VDDM 10V R32 51 C79 DNP –42– CX2 CX1 12 13 J34 OPCLK J40 J27 J5 C29 0.1F J3 C45 IQ 0.01F AGND;3,4,5 S5 OPCLK IQ S6 AGND;3,4,5 OPCLK_3 BD15 2 3 5 4 J24 11 12 13 BD14 J31 J26 R39 1k J32 R5 49.9 DVDD; 14 AGND; 7 74VCX86 TP14 WHT C1 10F 6.3V DVDD DVDD DVDD DVDD R1 200 R38, 10k J23 R3 1k 74VCX86 CX3 J25 11 AGND;3,4,5 S1 J12 R40 DVDD 200 AGND;3,4,5 DATACLK S2 R4 49.9 1 6 J22 T1 T1-1T J33 ADCLK C13 0.1F CLKIN J2 J1 TP15 WHT R2 1k C7 10F 6.3V C8 10F 6.3V C9 10F 6.3V C10 10F 6.3V C12 0.1F C42 0.1F BD11 C23 0.001F BD10 BD09 BD08 BD13 BD12 AD03 C24 0.001F AD02 AD01 AD00 AD09 C25 0.001F AD08 AD07 AD06 AD05 AD04 AD10 AD15 C26 0.001F AD14 AD13 AD12 AD11 C11 0.1F 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AD9777 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 C36 0.1F VDDA6 VSSA10 VDDA5 VSSA9 VDDA4 VSSA8 VSSA7 IOUT1P IOUT1N VSSA6 VSSA5 IOUT2P IOUT2N VSSA4 VSSA3 VDDA3 VSSA2 VDDA2 VSSA1 VDDA1 FSADJ1 FSADJ2 REFOUT RESET SP-CSB SP-CLK SP-SDI SP-SDO VSSD6 VDDD6 P2D0 P2D1 P2D2 P2D3 P2D4 P2D5 VSSD5 VDDD5 P2D6 P2D7 DVDD VDDC1 LF VDDC2 VSSC1 CLKP CLKN VSSC2 DCLK-PLLL VSSD1 VDDD1 P1D15 P1D14 P1D13 P1D12 P1D11 P1D10 VSSD2 VDDD2 U1 P1D9 P1D8 P1D7 P1D6 P1D5 P1D4 VSSD3 VDDD3 P1D3 P1D2 P1D1 P1D0 P2D15-IQSEL P2D14-OPCLK P2D13 P2D12 VSSD4 VDDD4 P2D11 P2D10 P2D9 P2D8 CLKVDD C20 0.1F C38 0.1F BD06 BD07 BD00 BD01 BD02 BD03 BD04 BD05 SPCSP SPCLK SPSDI SPSDO TP11 WHT C22 0.001F C40 0.1F C15 0.1F DVDD C4 10F 6.3V TP8 WHT DVDD C6 10F 6.3V C2 10F 6.3V AVDD C41 0.1F R7 2k C3 10F 6.3V AVDD C14 0.1F C5 10F 6.3V C16 0.1F TP9 WHT C17 0.1F C58, DNP C58, DNP C19 0.1F C39 0.1F C21 0.001F R6 1k TP10 WHT C18 0.1F C59, DNP C57, DNP C37 0.1F R8 2k J38 J36 J35 J37 R11, 51 R12, 51 4 5 6 4 5 6 J14 J15 T1-1T T3 J30 J29 J16 3 2 1 T2 T1-1T J13 3 2 1 J28 J4 R9, 51 R10, 51 O1N O1P O2N O2P R17, 10 C70, 0.1F R43 49.9 J17 AGND;3,4,5 OUT2 S4 R42 49.9 AGND;3,4,5 OUT1 S3 R16, 10 C70, 0.1F J8 AD9777 Figure 60. AD9777 Clock, Power Supplies, and Output Circuitry REV. 0 REV. 0 –43– 37 39 38 40 R15 220 35 36 RIBBON J1 33 22 34 21 20 31 19 18 32 17 16 29 15 14 30 13 12 27 11 10 28 9 8 25 7 6 26 5 4 23 3 24 1 2 DATA-A R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 R8 9 ADCLK 9 1 2 3 4 5 6 7 8 RCON R1 R2 R3 R4 R5 R6 R7 R8 RCON 1 RP6 50 Figure 61. AD9777 Evaluation Board Input (A Channel) and Clock Buffer Circuitry PRE 4 K R1 3 Q 6 5 DVDD Q_ 15 CLR CLK J R1 2 R1 4 R1 5 R1 6 R1 7 R1 8 R1 9 2 1 U4 3 10 R9 R1 10 OPCLK_3 DVDD; 14 AGND; 7 74VCX86 OPCLK_2 9 1 2 3 4 5 6 7 8 RCON R1 R2 R3 R4 R5 R6 R7 R8 RCON 1 74LCX112 U7 2 1 3 1 16 RP1, 22 2 15 RP1, 22 3 14 RP1, 22 4 13 RP1, 22 5 12 RP1, 22 6 11 RP1, 22 7 10 RP1, 22 8 9 RP2, 22 1 16 RP2, 22 2 15 RP2, 22 3 14 RP2, 22 4 13 RP2, 22 5 12 RP2, 22 6 11 RP2, 22 7 10 RP2, 22 8 9 RP2, 22 RP5 50 OPCLK 10 R9 R9 10 RP8 DNP AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 RP7 DNP CX1 CX1 10 U4 8 DVDD; 14 AGND; 7 6 DVDD; 14 AGND; 7 74VCX86 U4 8 DVDD; 14 AGND; 7 74VCX86 U4 6 DVDD; 14 AGND; 7 74VCX86 U4 3 DVDD; 14 AGND; 7 74VCX86 U4 74VCX86 74LCX112 U7 DVDD DVDD CX3 DVDD 14 AGND; 8 DVDD; 16 9 Q J PRE 12 CLK 13 7 Q_ K CLR 11 4 5 10 9 10 9 5 4 2 1 C52 4.7F 6.3V C31 4.7F 6.3V C30 4.7F 6.3V C53 0.1F C34 0.1F C33 0.1F AD9777 AD9777 DATA-B RCON 1 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 R1 2 R2 3 R3 4 R4 R5 R6 5 6 7 R7 8 R8 9 RP12 50 R9 10 RCON 1 R1 2 R1 3 R1 R1 4 5 R1 6 R1 7 R1 8 R1 R1 9 10 1 16 RP3, 22 2 15 RP3, 22 3 14 RP3, 22 4 13 RP3, 22 5 12 RP3, 22 6 11 RP3, 22 7 10 RP3, 22 8 9 RP4, 22 1 16 RP4, 22 2 15 RP4, 22 3 14 RP4, 22 4 13 RP4, 22 5 12 RP4, 22 6 11 RP4, 22 7 10 RP4, 22 8 9 RP4, 22 1 2 3 4 RCON R1 R2 R3 9 5 6 7 8 R4 R5 R6 R7 R8 10 R9 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 BD05 BD04 BD03 BD02 BD01 BD00 DVDD C43 4.7F 6.3V 1 U5 74AC14 4 U5 74AC14 SPCLK 10 R9 RP10 DNP DVDD RIBBON J2 SPCSB 9 7 8 R6 R7 R8 1 2 3 4 5 6 RCON R1 R2 R3 R4 R5 RP11 50 RP9 DNP 6 U5 74AC14 C44 4.7F 6.3V C50 0.1F 2 AGND; 7 DVDD; 14 3 AGND; 7 DVDD; 14 5 AGND; 7 DVDD; 14 12 U5 74AC14 10 U5 74AC14 8 U5 74AC14 13 C51 0.1F R50 9k AGND; 7 DVDD; 14 11 P1 1 AGND; 7 DVDD; 14 9 SPI PORT R48 9k 2 R45 9k AGND; 7 DVDD; 14 3 4 5 6 SPSDI SPSDO 1 U6 2 AGND; 7 74AC14 DVDD; 14 3 U6 4 AGND; 7 74AC14 DVDD; 14 5 U6 74AC14 6 AGND; 7 DVDD; 14 13 U6 12 AGND; 7 74AC14 DVDD; 14 11 U6 10 AGND; 7 74AC14 DVDD; 14 9 U6 8 AGND; 7 74AC14 DVDD; 14 Figure 62. AD9777 Evaluation Board Input (B Channel) and SPI Port Circuitry –44– REV. 0 AD9777 Figure 63. AD9777 Evaluation Board Components, Top Side Figure 64. AD9777 Evaluation Board Components, Bottom Side REV. 0 –45– AD9777 Figure 65. AD9777 Evaluation Board Layout, Layer One (Top) Figure 66. AD9777 Evaluation Board Layout, Layer Two (Ground Plane) –46– REV. 0 AD9777 Figure 67. AD9777 Evaluation Board Layout, Layer Three (Power Plane) Figure 68. AD9777 Evaluation Board Layout, Layer Four (Bottom) REV. 0 –47– AD9777 OUTLINE DIMENSIONS 80-Lead, Thermally Enhanced, Thin Plastic Quad Flatpack [TQFP] (SV-80) Dimensions shown in millimeters and (inches) 14.00 (0.5512) SQ 12.00 (0.4724) SQ 80 61 80 61 60 1 SEATING PLANE 60 1 PIN 1 TOP VIEW BOTTOM VIEW (PINS DOWN) 20 COPLANARITY 0.15 (0.0059) 0.05 (0.0020) C02706–0–5/02(0) 1.20 (0.0472) MAX 0.75 (0.0295) 0.60 (0.0236) 0.45 (0.0177) 41 21 6.00 (0.2362) SQ 20 41 40 40 21 1.05 (0.0413) 1.00 (0.0394) 0.95 (0.0374) 0.20 (0.0079) 0.09 (0.0035) GAGE PLANE 0.25 (0.0098) 0.50 (0.0197) BSC 0.27 (0.0106) 0.22 (0.0087) 0.17 (0.0067) 7 3.5 0 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-026-ADD PRINTED IN U.S.A. AN APPLICATION NOTE DETAILING THE THERMALLY ENHANCED TQFP CAN BE FOUND AT; www.amkor.com/products/notes_papers/MLF_Appnote_0301.pdf –48– REV. 0