Data Sheet Low Power, Five Electrode Electrocardiogram (ECG) Analog Front End ADAS1000/ADAS1000-1/ADAS1000-2 FEATURES Biopotential signals in; digitized signals out 5 acquisition (ECG) channels and one driven lead Parallel ICs for up to 10+ electrode measurements Master ADAS1000 or ADAS1000-1 used with Slave ADAS1000-2 AC and DC lead-off detection Internal pace detection algorithm on 3 leads Support for user’s own pace Thoracic impedance measurement (internal/external path) Selectable reference lead Scalable noise vs. power control, power-down modes Low power operation from 11 mW (1 lead), 15 mW (3 leads), 21 mW (all electrodes) Lead or electrode data available Supports AAMI EC11:1991/(R)2001/(R)2007, AAMI EC38 R2007, EC13:2002/(R)2007, IEC60601-1 ed. 3.0 b:2005, IEC60601-2-25 ed. 2.0 :2011, IEC60601-2-27 ed. 2.0 b:2005, IEC60601-2-51 ed. 1.0 b: 2005 Fast overload recovery Low or high speed data output rates Serial interface SPI-/QSPI™-/DSP-compatible 56-lead LFCSP package (9 mm × 9 mm) 64-lead LQFP package (10 mm × 10 mm body size) APPLICATIONS ECG: monitor and diagnostic Bedside patient monitoring, portable telemetry, Holter, AED, cardiac defibrillators, ambulatory monitors, pace maker programmer, patient transport, stress testing GENERAL DESCRIPTION The ADAS1000/ADAS1000-1/ADAS1000-2 measure electro cardiac (ECG) signals, thoracic impedance, pacing artifacts, and lead-on/off status and output this information in the form of a data frame supplying either lead/vector or electrode data at programmable data rates. Its low power and small size make it suitable for portable, battery-powered applications. The high performance also makes it suitable for higher end diagnostic machines. Rev. A The ADAS1000 is a full-featured, 5-channel ECG including respiration and pace detection, while the ADAS1000-1 offers only ECG channels with no respiration or pace features. Similarly, the ADAS1000-2 is a subset of the main device and is configured for gang purposes with only the ECG channels enabled (no respiration, pace, or right leg drive). The ADAS1000/ADAS1000-1/ADAS1000-2 are designed to simplify the task of acquiring and ensuring quality ECG signals. They provide a low power, small data acquisition system for biopotential applications. Auxiliary features that aid in better quality ECG signal acquisition include: multichannel averaged driven lead, selectable reference drive, fast overload recovery, flexible respiration circuitry returning magnitude and phase information, internal pace detection algorithm operating on three leads, and the option of ac or dc lead-off detection. Several digital output options ensure flexibility when monitoring and analyzing signals. Value-added cardiac post processing is executed externally on a DSP, microprocessor, or FPGA. Because ECG systems span different applications, the ADAS1000/ADAS1000-1/ADAS1000-2 feature a power/ noise scaling architecture where the noise can be reduced at the expense of increasing power consumption. Signal acquisition channels may be shut down to save power. Data rates can be reduced to save power. To ease manufacturing tests and development as well as offer holistic power-up testing, the ADAS1000/ADAS1000-1/ ADAS1000-2 offer a suite of features, such as dc and ac test excitation via the calibration DAC and CRC redundancy testing in addition to readback of all relevant register address space. The input structure is a differential amplifier input thereby allowing users a variety of configuration options to best suit their application. The ADAS1000/ADAS1000-1/ADAS1000-2 are available in two package options: either a 56-lead LFCSP or a 64-lead LQFP package; they are specified over −40°C to +85°C temperature range. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Extend Switch On Respiration Paths ....................................... 39 Applications ....................................................................................... 1 Pacing Artifact Detection Function (ADAS1000 Only) ....... 40 General Description ......................................................................... 1 Biventricular Pacers ................................................................... 42 Revision History ............................................................................... 2 Pace Detection Measurements ................................................. 42 Functional Block Diagram .............................................................. 3 Evaluating Pace Detection Performance ................................. 43 Specifications..................................................................................... 4 Pace Latency ................................................................................ 43 Noise Performance ....................................................................... 9 Timing Characteristics .............................................................. 10 Pace Detection via Secondary Serial Interface (ADAS1000 and ADAS1000-1 Only) ............................................................ 43 Absolute Maximum Ratings .......................................................... 13 Filtering ....................................................................................... 43 Thermal Resistance .................................................................... 13 Voltage Reference ....................................................................... 45 ESD Caution ................................................................................ 13 Gang Mode Operation ............................................................... 45 Pin Configurations and Function Descriptions ......................... 14 Interfacing in Gang Mode ......................................................... 47 Typical Performance Characteristics ........................................... 18 Serial Interfaces............................................................................... 48 Applications Information .............................................................. 25 Standard Serial Interface ........................................................... 48 Overview...................................................................................... 25 Secondary Serial Interface......................................................... 52 ECG Inputs—Electrodes/Leads ................................................ 28 RESET .......................................................................................... 52 ECG Channel .............................................................................. 29 PD Function ................................................................................ 52 Electrode/Lead Formation and Input Stage Configuration .. 30 SPI Output Frame Structure (ECG and Status Data) ................ 53 Defibrillator Protection ............................................................. 33 SPI Register Definitions and Memory Map ................................ 54 ESIS Filtering............................................................................... 33 Control Registers Details ............................................................... 55 ECG Path Input Multiplexing ................................................... 33 Examples of Interfacing to the ADAS1000 ............................. 72 Common-Mode Selection and Averaging .............................. 34 Software Flowchart .................................................................... 75 Wilson Central Terminal (WCT) ............................................. 35 Power Supply, Grounding, and Decoupling Strategy ............ 76 Right Leg Drive/Reference Drive ............................................. 35 AVDD .......................................................................................... 76 Calibration DAC ......................................................................... 36 ADCVDD and DVDD Supplies ............................................... 76 Gain Calibration ......................................................................... 36 Unused Pins/Paths ..................................................................... 76 Lead-Off Detection .................................................................... 36 Layout Recommendations ........................................................ 76 Shield Driver ............................................................................... 36 Outline Dimensions ....................................................................... 77 Respiration (ADAS1000 Model Only)..................................... 37 Ordering Guide .......................................................................... 78 Evaluating Respiration Performance ....................................... 39 REVISION HISTORY 1/13—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Table 1 ............................................................................ 3 Changes to Excitation Current, Test Conditions/Comments, Table 2 ................................................................................................ 5 Added Table 3; Renumbered Sequentially .................................... 9 Changes to Respiration (ADAS1000 Model Only) Section, Figure 66, and Internal Respiration Capacitors Section............ 37 Changes to Figure 67 ...................................................................... 38 Changes to Figure 68...................................................................... 39 Added Evaluating Pace Detection Performance Section .......... 43 Added Table 15 ............................................................................... 47 Changes to Clocks Section ............................................................ 51 Changes to RESPAMP Name, Function, Table 28 ..................... 57 Changes to Bits[14:9], Function, Table 30 .................................. 59 Changes to Ordering Guide .......................................................... 78 8/12—Revision 0: Initial Version Rev. A | Page 2 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 FUNCTIONAL BLOCK DIAGRAM REFIN REFOUT CAL_DAC_IO RLD_OUT CM_IN RLD_SJ CM_OUT/WCT DRIVEN LEAD AMP – VREF CALIBRATION DAC SHIELD SHIELD DRIVE AMP + AVDD IOVDD ADCVDD ADCVDD, DVDD 1.8V REGULATORS DVDD VCM_REF (1.3V) RESPIRATION DAC COMMONMODE AMP AC LEAD-OFF DAC AC LEAD-OFF DETECTION 10kΩ BUFFER PACE DETECTION MUXES CS SCLK 5× ECG PATH AMP EXT_RESP_LA EXT_RESP_LL AMP ADC SDO DRDY GPIO0/MCS GPIO1/MSCLK GPIO2/MSDO GPIO3 ADC EXT_RESP_RA RESPIRATION PATH ADAS1000 SDI FILTERS, CONTROL, AND INTERFACE LOGIC CLOCK GEN/OSC/ EXTERNAL CLK SOURCE XTAL1 CLK_IO 09660-001 ELECTRODES ×5 XTAL2 Figure 1. ADAS1000 Full Featured Model Table 1. Overview of Features Available from ADAS1000 Generics Generic ADAS1000 ADAS1000-1 ADAS1000-2 2 ADAS1000-3 ADAS1000-4 1 2 ECG 5 ECG channels 5 ECG channels 5 ECG channels 3 ECG channels 3 ECG channels Operation Master/slave Master/slave Slave Master/slave Master/slave Right Leg Drive Yes Yes Yes Yes Respiration Yes Pace Detection Yes Yes Yes Shield Driver Yes Yes Master Interface 1 Yes Yes Yes Yes Yes Yes Package Option LFCSP, LQFP LFCSP LFCSP, LQFP LFCSP, LQFP LFCSP, LQFP Master interface is provided for users wishing to utilize their own digital pace algorithm; see the Secondary Serial Interface section. This is a companion device for increased channel count purposes. It has a subset of features and is not intended for standalone use. It may be used in conjunction with any master device. Rev. A | Page 3 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet SPECIFICATIONS AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. Decoupling for reference and supplies as noted in the Power Supply, Grounding, and Decoupling Strategy section. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. For specified performance, internal ADCVDD and DVDD linear regulators have been used. They may be supplied from external regulators. ADCVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%. Front-end gain settings: GAIN 0 = ×1.4, GAIN 1 = ×2.1, GAIN 2 = ×2.8, GAIN 3 = ×4.2. Table 2. Parameter ECG CHANNEL Min Typ Max Unit 0.3 0.63 0.8 0.97 −40 1.3 1.3 1.3 1.3 ±1 2.3 1.97 1.8 1.63 +40 V V V V nA +200 −7 nA mV −7 −15 −22 ±2 1||10 mV mV mV μV/°C GΩ||pF 110 dB 80 19 18 dB Bits Bits 16 Bits 30 5 ppm ppm 4.9 9.81 39.24 3.27 6.54 26.15 2.45 4.9 19.62 1.63 µV/LSB μV/LSB μV/LSB μV/LSB μV/LSB μV/LSB μV/LSB μV/LSB μV/LSB μV/LSB 3.27 13.08 μV/LSB μV/LSB Electrode Input Range Input Bias Current −200 Input Offset Input Offset Tempco 1 Input Amplifier Input Impedance 2 CMRR2 Crosstalk1 Resolution2 Integral Nonlinearity Error Differential Nonlinearity Error Gain2 GAIN 0 (×1.4) GAIN 1 (×2.1) GAIN 2 (×2.8) GAIN 3 (×4.2) 105 Rev. A | Page 4 of 80 Test Conditions/Comments These specifications apply to the following pins: ECG1_LA, ECG2_LL, ECG3_RA, ECG4_V1, ECG5_V2, CM_IN (CE mode), EXT_RESP_xx pins when used in extend switch mode Independent of supply GAIN 0 (gain setting ×1.4) GAIN 1 (gain setting ×2.1) GAIN 2 (gain setting ×2.8) GAIN 3 (gain setting ×4.2) Relates to each electrode input; over operating range; dc and ac lead-off are disabled AGND to AVDD Electrode/vector mode with VCM = VCM_REF GAIN 3 GAIN 2 GAIN 1 GAIN 0 At 10 Hz 51 kΩ imbalance, 60 Hz with ±300 mV differential dc offset; per AAMI/IEC standards; with driven leg loop closed Between channels Electrode/vector mode, 2 kHz data rate, 24-bit data-word Electrode/vector mode, 16 kHz data rate, 24-bit dataword Electrode/analog lead mode, 128 kHz data rate, 16-bit data-word GAIN 0; all data rates GAIN 0 Referred to input. (2 × VREF)/Gain/(2N − 1). Applies after factory calibration. User calibration adjusts this number. At 19-bit level in 2 kHz data rate At 18-bit level in 16 kHz data rate At 16-bit level in 128 kHz data rate At 19-bit level in 2 kHz data rate At 18-bit level in 16 kHz data rate At 16-bit level in 128 kHz data rate At 19-bit level in 2 kHz data rate At 18-bit level in 16 kHz data rate At 16-bit level in 128 kHz data rate No factory calibration for this gain setting At 19-bit level in 2 kHz data rate At 18-bit level in 16 kHz data rate At 16-bit level in 128 kHz data rate Data Sheet Parameter Gain Error Gain Matching ADAS1000/ADAS1000-1/ADAS1000-2 Min −1 Typ +0.01 Max +1 Unit % −2 −0.1 −0.5 +0.1 +0.02 +0.1 25 +2 +0.1 +0.5 % % % ppm/°C Gain Tempco1 Input Referred Noise1 Analog Lead Mode 6 10 12 11 12 14 16 100 65 104 100 Electrode Mode Digital Lead Mode Power Supply Sensitivity2 Analog Channel Bandwidth1 Dynamic Range1 Signal-to-Noise Ratio1 COMMON-MODE INPUT Input Voltage Range Input Impedance2 Input Bias Current COMMON-MODE OUTPUT VCM_REF Output Voltage, VCM Output Impedance1 Short Circuit Current1 Electrode Summation Weighting Error2 RESPIRATION FUNCTION (ADAS1000 ONLY) Input Voltage Range Input Voltage Range (Linear Operation) Input Bias Current Input Referred Noise1 Frequency2 Excitation Current Resolution2 Measurement Resolution1 In-Amp Gain1 Gain Error Gain Tempco1 0.3 −40 −200 1.28 0.3 μV p-p μV p-p μV p-p μV p-p μV p-p μV p-p μV p-p dB kHz dB dB 2.3 1||10 ±1 1.3 1.3 0.75 4 1 0.3 +40 +200 1.32 2.3 ±1 0.85 46.5 to 64 V V kΩ mA % 2.3 V V p-p +10 nA μV rms kHz 1.8/gain −10 V GΩ||pF nA nA 64 32 16 8 24 0.2 μA p-p μA p-p μA p-p μA p-p bits Ω 0.02 1 to 10 Ω 1 25 % ppm/C Rev. A | Page 5 of 80 Test Conditions/Comments GAIN 0 to GAIN 2, factory calibrated. Programmable user or factory calibration option enables. Factory gain calibration applies only to standard ECG interface. GAIN 3 setting, no factory calibration for this gain GAIN 0 to GAIN 2 GAIN 3 GAIN 2, 2 kHz data rate, see Table 4 0.5 Hz to 40 Hz; high performance mode 0.05 Hz to 150 Hz; high performance mode 0.05 Hz to 150 Hz; low power mode 0.05 Hz to 150 Hz; high performance mode 0.05 Hz to 150 Hz; low power mode 0.05 Hz to 150 Hz; high performance mode 0.05 Hz to 150 Hz; low power mode At 120 Hz GAIN 0, 2 kHz data rate, −0.5 dBFS input signal, 10 Hz −0.5 dB FS input signal CM_IN pin Over operating range; dc and ac lead-off disabled AGND to AVDD CM_OUT pin Internal voltage; independent of supply No dc load Not intended to drive current Resistor matching error These specifications apply to the following pins: EXT_RESP_LA, EXT_RESP_LL, EXT_RESP_RA and selected internal respiration paths (Lead I, Lead II, Lead III) AC-coupled, independent of supply Programmable gain (10 states) Applies to EXT_RESP_xx pins over AGND to AVDD Programmable frequency, see Table 28 Respiration drive current corresponding to differential voltage programmed by RESPAMP bits in RESPCTL register. Internal respiration mode, cable 5 kΩ/200 pF, 1.2 kΩ chest impedance Drive Range A Drive Range B2 Drive Range C2 Drive Range D2 Update rate 125 Hz Cable <5 kΩ/200 pF per electrode, body resistance modeled as 1.2 kΩ No cable impedance, body resistance modeled as 1.2 kΩ Digitally programmable in steps of 1 LSB weight for GAIN 0 setting ADAS1000/ADAS1000-1/ADAS1000-2 Parameter RIGHT LEG DRIVE/DRIVEN LEAD (ADAS1000/ADAS1000-1 ONLY) Output Voltage Range RLD_OUT Short Circuit Current Closed-Loop Gain Range2 Slew Rate2 Input Referred Noise1 Amplifier GBP2 DC LEAD-OFF Data Sheet Min Typ Max Unit 0.2 −5 ±2 AVDD − 0.2 +5 V mA 25 V/V mV/ms μV p-p MHz 200 8 1.5 Lead-Off Current Accuracy High Threshold Level1 ±10 2.4 % V Low Threshold Level1 Threshold Accuracy AC LEAD-OFF 0.2 25 V mV Frequency Range Lead-Off Current Accuracy REFIN Input Range2 Input Current 2.031 ±10 1.76 450 1.8 113 675 kHz % 1.84 950 V μA μA REFOUT Output Voltage, VREF Reference Tempco1 Output Impedance2 Short Circuit Current1 Voltage Noise1 1.785 1.8 ±10 0.1 4.5 33 17 1.815 V ppm/°C Ω mA μV p-p μV p-p CALIBRATION DAC DAC Resolution Full-Scale Output Voltage Zero-Scale Output Voltage DNL Output Series Resistance2 Input Current CALIBRATION DAC TEST TONE Output Voltage Square Wave Low Frequency Sine Wave High Frequency Sine Wave SHIELD DRIVER (ADAS1000/ ADAS1000-1 ONLY) Output Voltage Range Gain Offset Voltage Short Circuit Current Stable Capacitive Load2 CRYSTAL OSCILLATOR Frequency2 Start-Up Time2 2.64 0.24 −1 0.9 10 2.7 0.3 10 Bits V V LSB kΩ ±5 nA 1 1 10 150 0.3 2.76 0.36 +1 15 External protection resistor required to meet regulatory patient current limits; output shorted to AVDD/AGND 0.05 Hz to 150 Hz Internal current source, pulls up open ECG pins; programmable in 10 nA steps: 10 nA to 70 nA Of programmed value Inputs are compared to threshold levels; if inputs exceed levels, lead-off flag is raised Programmable in 4 steps: 12.5 nA rms, 25 nA rms, 50 nA rms, 100 nA rms Fixed frequency Of programmed value, measured into low impedance Channel gain scales directly with REFIN Per active ADC 5 ECG channels and respiration enabled On-chip reference voltage for ADC; not intended to drive other components reference inputs directly, must be buffered externally Short circuit to ground 0.05 Hz to 150 Hz (ECG band) 0.05 Hz to 5 Hz (respiration) Available on CAL_DAC_IO (output for master, input for slave) No load, nominal FS output is 1.5 × REFOUT No load Not intended to drive low impedance load, used for slave CAL_DAC_IO configured as an input When used as input 1.1 mV p-p Hz Hz Hz Rides on common-mode voltage, VCM_REF = 1.3 V 2.3 V V/V mV μA nF Rides on common-mode voltage, VCM 1 −20 Test Conditions/Comments +20 25 10 Output current limited by internal series resistance Applied to XTAL1 and XTAL2 8.192 15 MHz ms Rev. A | Page 6 of 80 Internal startup Data Sheet Parameter CLOCK_IO Operating Frequency2 Input Duty Cycle2 Output Duty Cycle2 DIGITAL INPUTS Input Low Voltage, VIL Input High Voltage, VIH Input Current, IIH, IIL Pin Capacitance2 DIGITAL OUTPUTS Output Low Voltage, VOL Output High Voltage, VOH Output Rise/Fall Time DVDD REGULATOR Output Voltage Available Current1 Short Circuit Current limit ADCVDD REGULATOR Output Voltage Short Circuit Current Limit POWER SUPPLY RANGES2 AVDD IOVDD ADCVDD DVDD POWER SUPPLY CURRENTS AVDD Standby Current IOVDD Standby Current EXTERNALLY SUPPLIED ADCVDD AND DVDD AVDD Current ADCVDD Current DVDD Current INTERNALLY SUPPLIED ADCVDD AND DVDD AVDD Current POWER DISSIPATION Externally Supplied ADCVDD and DVDD 3 All 5 Input Channels and RLD Internally Supplied ADCVDD and DVDD All 5 Input Channels and RLD ADAS1000/ADAS1000-1/ADAS1000-2 Min Typ Max Unit 80 MHz % % 8.192 20 50 Test Conditions/Comments External clock source supplied to CLK_IO; this pin is configured as an input when the device is programmed as a slave Applies to all digital inputs 0.3 × IOVDD 0.7 × IOVDD −1 −20 +1 +20 3 0.4 V V ns 1.85 V mA mA IOVDD − 0.4 4 1.75 1.8 1 40 V V μA μA pF RESET has an internal pull-up ISINK = 1 mA ISOURCE = −1 mA Capacitive load = 15 pF, 20% to 80% Internal 1.8 V regulator for DVDD Droop < 10 mV; for external device loading purposes Internal 1.8 V regulator for ADCVDD; not recommended as a supply for other circuitry 1.75 1.8 40 1.85 V mA 3.15 1.65 1.71 1.71 3.3 1.8 1.8 5.5 3.6 1.89 1.89 V V V V 785 1 975 60 μA μA If applied by external 1.8 V regulator If applied by external 1.8 V regulator All 5 channels enabled, RLD enabled, pace enabled 3.4 3.1 4.25 6.2 4.7 7 2.7 1.4 3.4 6.25 5.3 6.3 9 6.5 9 5 3.5 5.5 mA mA mA mA mA mA mA mA mA High performance mode Low performance mode High performance mode, respiration enabled High performance mode Low performance mode High performance mode, respiration enabled High performance mode Low performance mode High performance mode, respiration enabled All 5 channels enabled, RLD enabled, pace enabled 12.5 9.4 14.8 15.3 12.4 17.3 mA mA mA High performance mode Low performance mode High performance mode, respiration enabled All 5 channels enabled, RLD enabled, pace enabled 27 21 mW mW High performance (low noise) Low power mode All 5 channels enabled, RLD enabled, pace enabled 41 31 mW mW High performance (low noise) Low power mode Rev. A | Page 7 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Parameter OTHER FUNCTIONS 4 Power Dissipation Respiration Shield Driver Min Typ 7.6 150 Data Sheet Max Unit Test Conditions/Comments mW μW Guaranteed by characterization, not production tested. Guaranteed by design, not production tested. 3 ADCVDD and DVDD can be powered from an internal LDO or, alternatively, can be powered from external 1.8 V rail, which may result in a lower power solution. 4 Pace is a digital function and incurs no power penalty. 1 2 Rev. A | Page 8 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 NOISE PERFORMANCE Table 3. Typical Input Referred Noise over 0.5 Second Window (µV p-p) 1 Mode Analog Lead Mode 3 High Performance Mode Data Rate 2 GAIN 0 (×1.4) ±1 VCM GAIN 1 (×2.1) ±0.67 VCM GAIN 2 (×2.8) ±0.5 VCM GAIN 3 (×4.2) ±0.3 VCM 2 kHz (0.5 Hz to 40 Hz) 2 kHz (0.05 Hz to 150 Hz) 8 14 6 11 5 9 4 7.5 Typical values measured at 25°C, not subject to production test. Data gathered using the 2 kHz packet/frame rate is measured over 0.5 seconds. The ADAS1000 internal programmable low-pass filter is configured for either 40 Hz or 150 Hz bandwidth. The data is gathered and post processed using a digital filter of either 0.05 Hz or 0.5 Hz to provide data over noted frequency bands. 3 Analog lead mode as shown in Figure 58 and Figure 57. 1 2 Table 4. Typical Input Referred Noise (μV p-p) 1 Mode Analog Lead Mode 3 High Performance Mode Low Power Mode Electrode Mode 4 High Performance Mode Low Power Mode Digital Lead Mode 5, 6 High Performance Mode Low Power Mode Data Rate 2 GAIN 0 (×1.4) ±1 VCM GAIN 1 (×2.1) ±0.67 VCM GAIN 2 (×2.8) ±0.5 VCM GAIN 3 (×4.2) ±0.3 VCM 2 kHz (0.5 Hz to 40 Hz) 2 kHz (0.05 Hz to 150 Hz) 16 kHz 128 kHz 2 kHz (0.5 Hz to 40 Hz) 2 kHz (0.05 Hz to 150 Hz) 16 kHz 128 kHz 12 20 95 180 13 22 110 215 8.5 14.5 65 130 9.5 15.5 75 145 6 10 50 105 7.5 12 59 116 5 8.5 39 80 5.5 9 45 85 2 kHz (0.5 Hz to 40 Hz) 2 kHz (0.05 Hz to 150 Hz) 16 kHz 128 kHz 2 kHz (0.5 Hz to 40 Hz) 2 kHz (0.05 Hz to 150 Hz) 16 kHz 128 kHz 13 21 100 190 14 22 110 218 9.5 15 70 139 9.5 15.5 75 145 8 11 57 110 7.5 12 60 120 5.5 9 41 85 5.5 9.5 45 88 2 kHz (0.5 Hz to 40 Hz) 2 kHz (0.05 Hz to 150 Hz) 16 kHz 2 kHz (0.5 Hz to 40 Hz) 2 kHz (0.05 Hz to 150 Hz) 16 kHz 16 25 130 18 30 145 11 19 90 12.5 21 100 9 15 70 10 16 80 6.5 10 50 7 11 58 Typical values measured at 25°C, not subject to production test. Data gathered using the 2 kHz packet/frame rate is measured over 20 seconds. The ADAS1000 internal programmable low-pass filter is configured for either 40 Hz or 150 Hz bandwidth. The data is gathered and post processed using a digital filter of either 0.05 Hz or 0.5 Hz to provide data over noted frequency bands. 3 Analog lead mode as shown in Figure 58 and Figure 57. 4 Single-ended input electrode mode as shown in Figure 59 and Figure 57. 5 Digital lead mode as shown in Figure 59 and Figure 57. 6 Digital lead mode is available in 2 kHz and 16 kHz data rates. 1 2 Rev. A | Page 9 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet TIMING CHARACTERISTICS Standard Serial Interface AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. Table 5. Parameter 1 Output Rate 2 3.3 V 2 SCLK Cycle Time tCSSA tCSHA tCH tCL tDO tDS tDH tCSSD tCSHD tCSW 25 8.5 3 8 8 8.5 11 2 2 2 2 25 tDRDY_CS2 tCSO RESET Low Time2 0 6 20 2 1.8 V 128 Unit kHz 40 9.5 3 8 8 11.5 19 2 2 2 2 40 50 12 3 8 8 20 24 2 2 2 2 50 ns min ns min ns min ns min ns min ns typ ns max ns min ns min ns min ns min ns min 0 7 20 0 9 20 ns min ns typ ns min Description Across specified IOVDD supply range; three programmable output data rates available as configured in FRMCTL register (see Table 35) 2 kHz, 16 kHz, 128 kHz; use skip mode for slower rates See Table 19 for details on SCLK vs. packet data rates CS valid setup time to rising SCLK CS valid hold time to rising SCLK SCLK high time SCLK low time SCLK falling edge to SDO valid delay; SDO capacitance of 15 pF SDI valid setup time from SCLK rising edge SDI valid hold time from SCLK rising edge CS valid setup time from SCLK rising edge CS valid hold time from SCLK rising edge CS high time between writes (if used). Note that CS is an optional input, it may be tied permanently low. See a full description in the Serial Interfaces section. DRDY to CS setup time Delay from CS assert to SDO active Minimum pulse width; RESET is edge triggered Guaranteed by characterization, not production tested. Guaranteed by design, not production tested. SCLK tCSSA tCH tCSSD tCL tCSHA tCSHD CS tCSW tDS tDH MSB LSB DB[31] SDI DB[30] R/W DB[29] DB[25] DB[24] ADDRESS tCSO DB[23] DB[1] DATA LSB MSB SDO DRDV DB[0] DO_31LAST DO_30LAST DO_29LAST DO_25LAST DO_1LAST tDO Figure 2. Data Read and Write Timing Diagram (CPHA = 1, CPOL = 1) Rev. A | Page 10 of 80 DO_0LAST 09660-002 1 IOVDD 2.5 V Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 tDRDY_CS DRDY tCH SCLK tCL tCSSA tCSSD tCSHD tCSHA CS tDS tCSW tDH MSB SDI LSB DB[29] N DB[25] N DB[24] N DB[31] N DB[30] N R/W ADDRESS = 0x40 (FRAMES) DB[23] DB[1] LSB MSB DB[0] N DB[1] N+1 DB[30] N+1 DB[31] N+1 DB[0] N+1 DATA = NOP or 0x40 DATA MSB SDO DRDY DB[30] N–1 DB[24] DB[23] N–1 N–1 DB[25] N–1 DB[1] N–1 LSB MSB LSB DB[31] N–1 DB[0] N–1 DB[31] N tDO PREVIOUS DATA DB[30] N DB[1] N DB[0] N HEADER (FIRST WORD OF FRAME) 09660-003 tCSO Figure 3. Starting Read Frame Data (CPHA = 1, CPOL = 1) tCH SCLK tCSSD tCL tCSSA tCSHA tCSHD CS tCSW tDH DB[31] SDI tDO SDO tDS LSB DB[30] R/W DB[29] DB[28] DB[24] ADDRESS DB[2] DB[1] DATA MSB DO_31LAST DB[0] LSB DO_30LAST DO_29LAST DO_28LAST DO_1LAST tDO Figure 4. Data Read and Write Timing Diagram (CPHA = 0, CPOL = 0) Rev. A | Page 11 of 80 DO_0LAST 09660-004 MSB ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000/ ADAS1000-1 Only AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock = 8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. The following timing specifications apply for the master interface when ECGCTL register is configured for high performance mode (ECGCTL[3] = 1), see Table 26. Table 6. Parameter 1 Output Frame Rate 2 fSCLK2 Min tMCSSA tMDO tMCSHD tMCSW Typ 128 2.5 × crystal frequency 24.4 0 48.8 2173 Max 2026 1 2 Unit kHz MHz Description All five 16-bit ECG data-words are available at frame rate of 128 kHz only Crystal frequency = 8.192 MHz ns ns ns ns MCS valid setup time MSCLK rising edge to MSDO valid delay MCS valid hold time from MSCLK falling edge MCS high time, SPIFW = 0, MCS asserted for entire frame as shown in Figure 5, and configured in Table 31 MCS high time, SPIFW = 1, MCS asserted for each word in frame as shown in Figure 6 and configured in Table 31 ns Guaranteed by characterization, not production tested. Guaranteed by design, not production tested. tMSCLK 2 tMSCLK MSCLK tMCSSA tMCSHD MCS SPIFW = 0* tMCSW MSB MSDO D0_15 D0_14 D0_1 LSB MSB D0_0 D1_15 D1_14 LSB MSB D5_0 D6_15 LSB D6_14 D6_0 tMDO 16-BIT CRC WORD 5 × 16-BIT ECG DATA 09660-105 HEADER: 0xF AND 12-BIT COUNTER *SPIFW = 0 PROVIDES MCS FOR EACH FRAME, SCLK STAYS HIGH FOR 1/2 MSCLK CYCLE BETWEEN EACH WORD. Figure 5. Data Read and Write Timing Diagram for SPIFW = 0, Showing Entire Packet Of Data (Header, 5 ECG Words, and CRC Word) tMSCLK MSCLK tMCSSA tMSCLK tMCSHD MCS SPIFW = 1* tMCSW LSB MSB MSDO D0_15 D0_14 D0_1 D0_0 MSB D1_15 LSB D1_14 D5_0 MSB D6_15 LSB D6_14 D6_0 HEADER: 0xF AND 12-BIT COUNTER 5 × 16-BIT ECG DATA 16-BIT CRC WORD *SPIFW = 1 PROVIDES MCS FOR EACH FRAME, SCLK STAYS HIGH FOR 1 MSCLK CYCLE BETWEEN EACH WORD. Figure 6. Data Read and Write Timing Diagram for SPIFW = 1, Showing Entire Packet Of Data (Header, 5 ECG Words, and CRC Word) Rev. A | Page 12 of 80 09660-005 tMDO Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter AVDD to AGND IOVDD to DGND ADCVDD to AGND DVDD to DGND REFIN/REFOUT to REFGND ECG and Analog Inputs to AGND Digital Inputs to DGND REFIN to ADCVDD AGND to DGND REFGND to AGND ECG Input Continuous Current Storage Temperature Range Operating Junction Temperature Range Reflow Profile Junction Temperature ESD HBM FICDM Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +2.5 V −0.3 V to +2.5 V −0.3 V to +2.1 V −0.3 V to AVDD + 0.3 V −0.3 V to IOVDD + 0.3 V ADCVDD + 0.3 V −0.3 V to + 0.3 V −0.3 V to + 0.3 V ±10 mA −65°C to +125°C −40°C to +85°C J-STD 20 (JEDEC) 150°C max θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 8. Thermal Resistance1 Package Type 56-Lead LFCSP 64-Lead LQFP 1 θJA 35 42.5 Unit °C/W °C/W Based on JEDEC standard 4-layer (2S2P) high effective thermal conductivity test board (JESD51-7) and natural convection. ESD CAUTION 2500 V 1000 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 13 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet AVDD CM_IN RLD_OUT RLD_SJ CM_OUT/WCT AVDD AGND AGND ADCVDD XTAL1 XTAL2 CLK_IO DVDD DGND 56 55 54 53 52 51 50 49 48 47 46 45 44 43 NC AGND 1 ECG5_V2 2 ECG4_V1 3 ECG3_RA 4 ECG2_LL 5 ECG1_LA 6 REFIN 7 REFOUT 8 REFGND 9 EXT_RESP_LA 10 EXT_RESP_LL 11 EXT_RESP_RA 12 RESPDAC_RA 13 AGND 14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC 47 DGND RESPDAC_RA 3 46 IOVDD EXT_RESP_RA 4 45 SDO EXT_RESP_LL 5 44 SCLK EXT_RESP_LA 6 43 SDI NC 1 PIN 1 2 7 ADAS1000 42 DRDY REFOUT 8 64-LEAD LQFP 41 CS TOP VIEW (Not to Scale) 40 DGND 39 GPIO3 ECG2_LL 11 38 GPIO2/MSDO ECG3_RA 12 37 GPIO1/MSCLK ECG4_V1 13 36 GPIO0/MCS ECG5_V2 14 35 IOVDD AGND 15 34 DGND NC 16 33 NC REFIN 9 ECG1_LA 10 NC DGND IOVDD GPIO0/MCS GPIO1/MSCLK GPIO2/MSDO GPIO3 DGND CS DRDY SDI SCLK SDO IOVDD DGND NOTES 1. THE EXPOSED PADDLE IS ON THE TOP OF THE PACKAGE; IT IS CONNECTED TO THE MOST NEGATIVE POTENTIAL, AGND. 09660-007 DGND DVDD CLK_IO XTAL2 XTAL1 ADCVDD AGND AGND AVDD CM_OUT/WCT RLD_SJ RLD_OUT CM_IN NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD TOP VIEW (Not to Scale) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 REFGND ADAS1000 56-LEAD LFCSP NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 8. ADAS1000 56-Lead LFCSP Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 AVDD CM_IN RLD_OUT RLD_SJ CM_OUT/WCT AVDD AGND AGND ADCVDD XTAL1 XTAL2 CLK_IO DVDD DGND Figure 7. ADAS1000 64-Lead LQFP Pin Configuration PIN 1 INDICATOR ADAS1000-1 56-LEAD LFCSP TOP VIEW (Not to Scale) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 DGND IOVDD GPIO0/MCS GPIO1/MSCLK GPIO2/MSDO GPIO3 DGND CS DRDY SDI SCLK SDO IOVDD DGND AVDD NC CAL_DAC_IO SHIELD VREG_EN AVDD AGND AGND ADCVDD RESET PD SYNC_GANG DVDD DGND 15 16 17 18 19 20 21 22 23 24 25 26 27 28 AGND 1 ECG5_V2 2 ECG4_V1 3 ECG3_RA 4 ECG2_LL 5 ECG1_LA 6 REFIN 7 REFOUT 8 REFGND 9 NC 10 NC 11 NC 12 NC 13 AGND 14 NOTES 1. THE EXPOSED PADDLE IS ON THE TOP OF THE PACKAGE; IT IS CONNECTED TO THE MOST NEGATIVE POTENTIAL, AGND. Figure 9. ADAS1000-1 56-Lead LFCSP Pin Configuration Rev. A | Page 14 of 80 09660-008 AGND PIN 1 INDICATOR AVDD RESPDAC_LL CAL_DAC_IO SHIELD/RESPDAC_LA VREG_EN AVDD AGND AGND ADCVDD RESET PD SYNC_GANG DVDD DGND 48 09660-006 DGND DVDD SYNC_GANG PD RESET ADCVDD AGND AGND AVDD VREG_EN SHIELD/RESPDAC_LA CAL_DAC_IO RESPDAC_LL AVDD NC PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AVDD CM_IN NC RLD_SJ NC AVDD AGND AGND ADCVDD NC NC CLK_IN DVDD DGND NC DGND DVDD SYNC_GANG PD RESET ADCVDD AGND AGND AVDD VREG_EN NC CAL_DAC_IN ADAS1000/ADAS1000-1/ADAS1000-2 NC AVDD NC Data Sheet 56 55 54 53 52 51 50 49 48 47 46 45 44 43 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 NC PIN 1 2 NC 3 NC 4 45 SDO NC 5 44 SCLK 47 DGND AGND 1 ECG5 2 ECG4 3 ECG3 4 ECG2 5 ECG1 6 REFIN 7 REFOUT 8 REFGND 9 NC 10 NC 11 NC 12 NC 13 AGND 14 46 IOVDD 43 SDI NC 6 REFGND 7 ADAS1000-2 REFOUT 8 64-LEAD LQFP REFIN 9 42 DRDY 41 CS 40 DGND TOP VIEW (Not to Scale) ECG1 10 39 GPIO3 ECG2 11 37 GPIO1 ECG4 13 36 GPIO0 ECG5 14 35 IOVDD AGND 15 34 DGND NC 16 33 NC NC TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PADDLE IS ON THE TOP OF THE PACKAGE; IT IS CONNECTED TO THE MOST NEGATIVE POTENTIAL, AGND. 2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 09660-010 DGND DVDD CLK_IN NC NC ADCVDD AGND AGND AVDD NC RLD_SJ NC CM_IN NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD 56-LEAD LFCSP DGND IOVDD GPIO0 GPIO1 GPIO2 GPIO3 DGND CS DRDY SDI SCLK SDO IOVDD DGND AVDD NC CAL_DAC_IN NC VREG_EN AVDD AGND AGND ADCVDD RESET PD SYNC_GANG DVDD DGND ECG3 12 ADAS1000-2 42 41 40 39 38 37 36 35 34 33 32 31 30 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 38 GPIO2 PIN 1 INDICATOR NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 10. ADAS1000-2 Companion 64-Lead LQFP Pin Configuration 09660-009 NC 1 AGND Figure 11. ADAS1000-2 Companion 56-Lead LFCSP Pin Configuration Table 9. Pin Function Descriptions ADAS1000 LQFP LFCSP 18, 23, 15, 20, 58, 63 51, 56 35, 46 30, 41 ADAS1000-1 LFCSP 15, 20, 51, 56 30, 41 ADAS1000-2 LQFP LFCSP 18, 23, 15, 20, 58, 63 51, 56 35, 46 30, 41 26, 55 23, 48 23, 48 26, 55 23, 48 ADCVDD 30, 51 27, 44 27, 44 30, 51 27, 44 DVDD 2, 15, 24, 25, 56, 57 31, 34, 40, 47, 50 59 1, 14, 21, 22, 49, 50 28, 29, 36, 42, 43 19 1, 14, 21, 22, 49, 50 2, 15, 24, 25, 56, 57 31, 34, 40, 47, 50 59 1, 14, 21, 22, 49, 50 28, 29, 36, 42, 43 19 AGND Description Analog Supply. See recommendations for bypass capacitors in the Power Supply, Grounding, and Decoupling Strategy section. Digital Supply for Digital Input/Output Voltage Levels. See recommendations for bypass capacitors in the Power Supply, Grounding, and Decoupling Strategy section. Analog Supply for ADC. There is an on-chip linear regulator providing the supply voltage for the ADCs. This pin is primarily provided for decoupling purposes; however, the pin may also be supplied by an external 1.8 V supply should the user wish to use a more efficient supply to minimize power dissipation. In this case, use the VREG_EN pin tied to ground to disable the ADCVDD and DVDD regulators. The ADCVDD pin should not be used to supply other functions. See recommendations for bypass capacitors in the Power Supply, Grounding, and Decoupling Strategy section. Digital Supply. There is an on-chip linear regulator providing the supply voltage for the digital core. This pin is primarily provided for decoupling purposes; however, the pin may also be overdriven supplied by an external 1.8 V supply should the user wish to use a more efficient supply to minimize power dissipation. In this case, use the VREG_EN pin tied to ground to disable the ADCVDD and DVDD regulators. See recommendations for bypass capacitors in the Power Supply, Grounding, and Decoupling Strategy section. Analog Ground. DGND Digital Ground. VREG_EN 10 11 12 13 6 5 4 3 Enables or disables the internal voltage regulators used for ADCVDD and DVDD. Tie this pin to AVDD to enable or tie this pin to ground to disable the internal voltage regulators. Analog Input, Left Arm (LA). Analog Input, Left Leg (LL). Analog Input, Right Arm (RA). Analog Input, Chest Electrode 1 or Auxiliary Biopotential Input (V1). 28, 29, 36, 42, 43 19 6 5 4 3 Mnemonic AVDD IOVDD ECG1_LA ECG2_LL ECG3_RA ECG4_V1 Rev. A | Page 15 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 ADAS1000 LQFP LFCSP 14 2 ADAS1000-1 LFCSP 2 ADAS1000-2 LQFP LFCSP 10 11 12 13 14 6 5 4 3 2 Data Sheet Mnemonic ECG5_V2 ECG1 ECG2 ECG3 ECG4 ECG5 EXT_RESP_RA EXT_RESP_LL EXT_RESP_LA RESPDAC_LL Description Analog Input, Chest Electrode 2 or Auxiliary Biopotential Input (V2). Analog Input 1. Analog Input 2. Analog Input 3. Analog Input 4. Analog Input 5. Optional External Respiration Input. Optional External Respiration Input. Optional External Respiration Input. Optional path for higher performance respiration resolution, respiration DAC drive, Negative Side 0. Shared Pin (User-Configured). Output of Shield Driver (SHIELD). Optional Path for Higher Performance Respiration Resolution, Respiration DAC Drive, Negative Side 1 (RESPDAC_LA). Optional Path for Higher Performance Respiration Resolution, Respiration DAC Drive, Positive Side. Common-Mode Output Voltage (Average of Selected Electrodes). Not intended to drive current. Common-Mode Input. Summing Junction for Right Leg Drive Amplifier. Output and Feedback Junction for Right Leg Drive Amplifier. Calibration DAC Input/Output. Output for a master device, input for a slave. Not intended to drive current. Reference Input. For standalone mode, use REFOUT connected to REFIN. External 10 μF with ESR < 0.2 Ω in parallel with 0.1 μF bypass capacitors to GND are required and should be placed as close to the pin as possible. An external reference can be connected to REFIN. Reference Output. Reference Ground. Connect to a clean ground. External crystal connects between these two pins; external clock drive should be applied to CLK_IO. Each XTAL pin requires 15 pF to ground. Buffered Clock Input/Output. Output for a master device; input for a slave. Powers up in high impedance. Chip Select and Frame Sync, Active Low. CS can be used to frame each word or to frame the entire suite of data in framing mode. Clock Input. Data is clocked into the shift register on a rising edge and clocked out on a falling edge. Serial Data Input. Power-Down, Active Low. 4 5 6 62 12 11 10 16 60 18 SHIELD/ RESPDAC_LA 3 13 RESPDAC_RA 22 52 52 19 21 20 61 55 53 54 17 55 53 54 17 19 21 55 53 CM_IN RLD_SJ RLD_OUT CAL_DAC_IO 9 7 7 9 7 REFIN 8 7 27, 28 8 9 47, 46 8 9 47, 46 8 7 8 9 REFOUT REFGND XTAL1, XTAL2 29 45 45 41 35 35 41 35 CS 44 32 32 44 32 SCLK 43 53 33 25 33 25 43 53 33 25 SDI PD 45 31 31 45 31 SDO 42 34 34 42 34 DRDY 54 24 24 54 24 RESET 52 26 26 52 26 SYNC_GANG 36 40 40 GPIO0/MCS Digital Input. This pin has an internal pull-up. This pin resets all internal nodes to their power-on reset values. Digital Input/Output (Output on Master, Input on Slave). Used for synchronization control where multiple devices are connected together. Powers up in high impedance. General-Purpose I/O or Master 128 kHz SPI CS. 37 38 39 39 38 37 39 38 37 GPIO1/MSCLK GPIO2/MSDO GPIO3 General-Purpose I/O or Master 128 kHz SPI SCLK. General-Purpose I/O or Master 128 kHz SPI SDO. General-Purpose I/O. CM_OUT/WCT CLK_IO Serial Data Output. This pin is used for reading back register configuration data and for the data frames. Digital Output. This pin indicates that conversion data is ready to be read back when low, busy when high. When reading packet data, the entire packet must be read to allow DRDY to return high. Rev. A | Page 16 of 80 Data Sheet ADAS1000 LQFP LFCSP 1, 16, 17, 32, 33, 48, 49, 64 ADAS1000/ADAS1000-1/ADAS1000-2 ADAS1000-1 LFCSP 10, 11, 12, 13, 16 ADAS1000-2 LQFP LFCSP 10, 11, 1, 3, 4, 12, 13, 5, 6, 16, 18, 16, 17, 46, 47, 20, 22, 52, 54 27, 28, 32, 33, 48, 49, 60, 62, 64 36 40 37 39 38 38 39 37 57 Description No connect. Do not connect to these pins. (see Figure 7, Figure 9, Figure 10, Figure 11). General-Purpose I/O. General-Purpose I/O. General-Purpose I/O. General-Purpose I/O. Output of Shield Driver. Calibration DAC Input. Input for companion device. Calibration signal should come from the master. Buffered Clock Input. This pin should be driven from the master CLK_IO pin. Exposed Pad. The exposed paddle is on the top of the package; it is connected to the most negative potential, AGND. 61 17 GPIO0 GPIO1 GPIO2 GPIO3 SHIELD CAL_DAC_IN 29 45 57 CLK_IN EPAD 18 57 Mnemonic NC Rev. A | Page 17 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 8 15 10 INPUT REFERRED NOISE (µV) 4 2 0 –2 1 2 3 4 5 6 7 8 9 10 –5 Figure 12. Input Referred Noise for 0.5 Hz to 40 Hz Bandwidth, 2 kHz Data Rate, GAIN 0 (1.4) 8 –15 09660-039 0 TIME (Seconds) 0.5Hz TO 150Hz GAIN SETTING 3 = 4.2 DATA RATE = 2kHz 10 SECONDS OF DATA 0 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) Figure 15. Input Referred Noise for 0.5 Hz to 150 Hz Bandwidth, 2 kHz Data Rate, GAIN 3 (4.2) 25 0.5Hz TO 40Hz GAIN SETTING 3 = 4.2 DATA RATE = 2kHz 10 SECONDS OF DATA LA 150Hz LA 40Hz INPUT REFERRED NOISE (µV) 6 INPUT REFERRED NOISE (µV) 0 –10 –4 –6 5 09660-042 INPUT REFERRED NOISE (µV) 0.5Hz TO 40Hz GAIN SETTING 0 = 1.4 DATA RATE = 2kHz 6 10 SECONDS OF DATA 4 2 0 –2 20 15 10 5 0 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) 0 09660-040 –6 Figure 13. Input Referred noise for 0.5 Hz to 40 Hz Bandwidth, 2 kHz Data Rate, GAIN 3 (4.2) GAIN 0 GAIN 1 GAIN 2 GAIN 3 GAIN SETTING 09660-043 –4 Figure 16. ECG Channel Noise Performance over a 0.5 Hz to 40 Hz or 0.5 Hz to 150 Hz Bandwidth vs. Gain Setting 15 0.0020 AVDD = 3.3V GAIN SETTING 0 = 1.4 0.0018 GAIN ERROR (%) 5 0 –5 0.0016 0.0014 –15 0.5Hz TO 150Hz GAIN SETTING 0 = 1.4 DATA RATE = 2kHz 10 SECONDS OF DATA 0 1 2 3 4 5 6 TIME (Seconds) 7 8 9 10 Figure 14. Input Referred Noise for 0.5 Hz to 150 Hz Bandwidth, 2 kHz Data Rate, GAIN 0 (1.4) Rev. A | Page 18 of 80 0.0010 LA LL RA V1 ELECTRODE INPUT Figure 17. Typical Gain Error Across Channels V2 09660-044 0.0012 –10 09660-041 INPUT REFERRED NOISE (µV) 10 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 0.121 0.215 AVDD = 3.3V AVDD = 3.3V 0.210 0.101 THRESHOLD (V) GAIN ERROR (%) 0.205 0.081 0.061 0.041 0.200 0.195 0.190 0.021 GAIN 0 GAIN 1 GAIN 2 GAIN 3 0.180 –40 ECG DC LEAD-OFF THRESHOLD RLD DC LEAD-OFF THRESHOLD –20 0 GAIN SETTING 2.420 0 = 1.4 1 = 2.1 2 = 2.8 3 = 4.2 HIGH THRESHOLD (V) –0.15 –0.20 2.405 2.400 2.395 2.390 2.385 GAIN ERROR G0 GAIN ERROR G1 GAIN ERROR G2 GAIN ERROR G3 –0.35 –40 –20 0 20 40 60 2.380 80 TEMPERATURE (°C) Figure 19. Typical Gain Error for All Gain Settings Across Temperature –20 0 20 40 60 80 Figure 22. DC Lead-Off Comparator High Threshold vs. Temperature 0 AVDD = 3.3V GAIN SETTING 0 = 1.4 +85°C +55°C +25°C –5°C –40°C ECG DC LEAD-OFF THRESHOLD RLD DC LEAD-OFF THRESHOLD TEMPERATURE (°C) AVDD = 3.3V –1 –2 2 –3 1 –4 GAIN (dB) LEAKAGE (nA) 2.375 –40 09660-046 –0.30 09660-049 –0.25 0 –1 –5 –6 –2 –7 –3 –8 –4 –9 1.3 VOLTAGE (V) 1.8 2.3 09660-047 0.8 –10 Figure 20. Typical ECG Channel Leakage Current over Input Voltage Range vs. Temperature 1 10 100 FREQUENCY (Hz) 1k 09660-050 GAIN ERROR (%) –0.10 –5 0.3 AVDD = 3.3V 2.410 –0.05 3 80 2.415 0 4 60 Figure 21. DC Lead-Off Comparator Low Threshold vs. Temperature 0.15 5 40 TEMPERATURE (°C) Figure 18. Typical Gain Error vs. Gain AVDD = 3.3V GAIN SETTING 0.10 GAIN SETTING GAIN SETTING 0.05 GAIN SETTING 20 09660-048 0.001 09660-045 0.185 Figure 23. Filter Response with 40 Hz Filter Enabled, 2 kHz Data Rate; See Figure 72 for Digital Filter Overview Rev. A | Page 19 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet 0 0 AVDD = 3.3V –1 –1 –2 –2 –4 GAIN (dB) GAIN (dB) –3 –5 –6 –3 –4 –7 –8 –5 –9 10 100 1k FREQUENCY (Hz) AVDD = 3.3V –6 1 0 0 –1 –2 –2 10k 100k AVDD = 3.3V –3 –4 GAIN (dB) –5 –6 –4 –5 –6 –7 –7 –8 10 100 1k FREQUENCY (Hz) Figure 25. Filter Response with 250 Hz Filter Enabled, 2 kHz Data Rate; See Figure 72 for Digital Filter Overview 0 –9 09660-052 1 1 10 100 1k 10k 100k FREQUENCY (Hz) 09660-055 –8 –9 Figure 28. Filter Response Running at 128 kHz Data Rate; See Figure 72 for Digital Filter Overview 1.8010 AVDD = 3.3V –1 1.8005 –2 1.8000 –3 VOLTAGE (V) 1.7995 –4 –5 –6 1.7990 1.7985 1.7980 –7 1.7975 –8 1.7970 1 10 100 FREQUENCY (Hz) 1k 09660-053 –9 Figure 26. Filter Response with 450 Hz Filter Enabled, 2 kHz Data Rate; See Figure 72 for Digital Filter Overview Rev. A | Page 20 of 80 1.7965 –40 –20 0 20 40 60 TEMPERATURE (°C) Figure 29. Typical Internal VREF vs. Temperature 80 09660-056 GAIN (dB) –3 GAIN (dB) 1k Figure 27. Analog Channel Bandwidth –1 –10 100 FREQUENCY (Hz) Figure 24. Filter Response with 150 Hz Filter Enabled, 2 kHz Data Rate; See Figure 72 for Digital Filter Overview –10 10 09660-054 1 09660-051 –10 Data Sheet 805 AVDD = 3.3V AVDD = 3.3V 800 AVDD SUPPLY CURRENT (µA) 1.3005 1.2995 1.2990 1.2985 1.2980 785 780 775 0 20 40 60 80 TEMPERATURE (°C) 765 –40 0 20 40 60 80 TEMPERATURE (°C) Figure 33. Typical AVDD Supply Current vs. Temperature in Standby Mode Figure 30. VCM_REF vs. Temperature 12.65 AVDD = 3.3V 5 ECG CHANNELS ENABLED INTERNAL LDO UTILIZED 12.45 HIGH PERFORMANCE/LOW NOISE MODE 12.60 12.40 12.55 CURRENT (mA) 12.50 12.35 12.30 LOW NOISE/HIGH PERFORMANCE MODE 12.50 12.45 12.40 12.25 –20 0 20 40 60 80 TEMPERATURE (°C) 12.35 3.0 09660-060 12.20 –40 3.5 4.0 4.5 5.0 5.5 6.0 VOLTAGE (V) Figure 34. Typical AVDD Supply Current vs. AVDD Supply Voltage Figure 31. Typical AVDD Supply Current vs. Temperature, Using Internal ADVCDD/DVDD Supplies 3.430 0.142955 AVDD = 3.3V 5 ECG CHANNELS ENABLED ADCVDD AND DVDD SUPPLIED EXTERNALLY HIGH PERFORMANCE/LOW NOISE MODE RESPIRATION MAGNITUDE (V) 3.425 –20 09660-069 –20 09660-057 1.2970 –40 AVDD SUPPLY CURRENT (mA) 790 770 1.2975 AVDD SUPPLY CURRENT (mA) 795 09660-059 VOLTAGE (V) 1.3000 3.420 3.415 3.410 3.405 0.142945 0.142940 0.142935 0.142930 3.400 –20 0 20 40 TEMPERATURE (°C) 60 80 0.142925 09660-058 3.395 –40 AVDD = 3.3V ECG PATH/DEFIB/CABLE IMPEDANCE = 0 Ω PATIENT IMPEDANCE = 1k Ω RESPIRATION RATE = 10RESPPM 0.142950 RESPAMP = 11 = 60µA p-p RESPGAIN = 0011 = 4 Figure 32. Typical AVDD Supply Current vs. Temperature, Using Externally Supplied ADVCDD/DVDD 0 5 10 15 TIME (Seconds) 20 25 30 09660-062 1.3010 ADAS1000/ADAS1000-1/ADAS1000-2 Figure 35. Respiration with 200 mΩ Impedance Variation, Using Internal Respiration Paths and Measured with a 0 Ω Patient Cable Rev. A | Page 21 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet 0.517390 AVDD = 3.3V ECG PATH/DEFIB/CABLE IMPEDANCE = 0Ω PATIENT IMPEDANCE = 1kΩ 0.121140 RESPIRATION RATE = 10RESPPM RESPAMP = 11 = 60µA p-p RESPGAIN = 0011 = 4 0.121135 0.121130 0.121125 0.517375 0.517370 0.121120 0.517365 0.121115 0.517360 0 5 10 15 20 25 30 TIME (Seconds) Figure 36. Respiration with 100 mΩ Impedance Variation, Using Internal Respiration Paths and Measured with a 0 Ω Patient Cable 0.663160 0.663155 0.159770 0.663150 0.663145 0.663140 15 20 25 30 AVDD = 3.3V TIME (seconds) ECG PATH/DEFIB/CABLE IMPEDANCE = 1.5k Ω/600pF PATIENT IMPEDANCE = 1k Ω EXTCAP = 1nF RESPIRATION RATE = 10RESPPM RESPAMP = 11 = 60µA p-p RESPGAIN = 0011 = 4 0.159765 0.159760 0.159755 15 20 25 30 0.159745 0.159125 RESPIRATION MAGNITUDE (V) 0.062350 0.062345 AVDD = 3.3V ECG PATH/DEFIB/CABLE IMPEDANCE = 0Ω PATIENT IMPEDANCE = 1kΩ EXTCAP = 100pF RESPIRATION RATE = 10RESPPM RESPAMP = 11 = 60µA p-p RESPGAIN = 0011 = 4 0 5 10 15 TIME (ms) 15 20 25 30 AVDD = 3.3V ECG PATH/DEFIB/CABLE IMPEDANCE = 1.5kΩ/600pF PATIENT IMPEDANCE = 1k Ω 0.159124 0.159123 0.159122 0.159121 0.159120 0.159119 EXTCAP= 1nF 20 25 30 0.159118 09660-065 0.062340 10 Figure 40. Respiration with 200 mΩ Impedance Variation, Using External Respiration DAC Driving 1 nF External Capacitor and Measured with a 1.5 kΩ Patient Cable 0.159126 0.062355 5 TIME (ms) 0.062365 0.062360 0 09660-066 10 Figure 37. Respiration with 200 mΩ Impedance Variation, Using Internal Respiration Paths and Measured with a 5 kΩ Patient Cable RESPIRATION MAGNITUDE (V) 10 Figure 38. Respiration with 200 mΩ Impedance Variation, Using External Respiration DAC Driving 100 pF External Capacitor and Measured with a 0 Ω Patient Cable RESPIRATION RATE = 10RESPPM RESPAMP = 11 = 60µA p-p RESPGAIN = 0011 = 4 0 5 10 15 TIME (Seconds) 20 25 30 09660-068 5 09660-064 0 TIME (ms) 0.062335 5 0.159750 0.663135 0.663130 0 Figure 39. Respiration with 200 mΩ Impedance Variation, Using External Respiration DAC Driving 100 pF External Capacitor and Measured with a 5 kΩ Patient Cable 0.159775 AVDD = 3.3V ECG PATH/DEFIB/CABLE IMPEDANCE = 5k Ω PATIENT IMPEDANCE = 1k Ω RESPIRATION RATE = 10RESPPM RESPAMP = 11 = 60µA p-p RESPGAIN = 0011 = 4 RESPAMP = 11 = 60µA p-p RESPGAIN = 0011 = 4 TIME (Seconds) RESPIRATION MAGNITUDE (V) RESPIRATION MAGNITUDE (V) 0.517380 09660-067 RESPIRATION MAGNITUDE (V) AVDD = 3.3V ECG PATH/DEFIB/CABLE IMPEDANCE = 5k Ω/250pF PATIENTIMPEDANCE = 1k Ω EXTCAP = 100pF 0.517385 RESPIRATION RATE = 10RESPPM 09660-063 RESPIRATION MAGNITUDE (V) 0.121145 Figure 41. Respiration with 100 mΩ Impedance Variation, Using External Respiration DAC Driving 1 nF External Capacitor and Measured with a 1.5 kΩ Patient Cable Rev. A | Page 22 of 80 Data Sheet 50 ADAS1000/ADAS1000-1/ADAS1000-2 40 30 LA LL RA V1 V2 AVDD = 3.3V 100 20 50 10 INL (µV/RTI) DNL ERROR (µV RTI) 150 LA LL RA V1 V2 AVDD = 3.3V 0 –10 0 –50 –20 –30 –100 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 INPUT VOLTAGE (V) Figure 42. DNL vs. Input Voltage Range Across Electrodes at 25°C 50 30 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 INPUT VOLTAGE (V) Figure 45. INL vs. Input Voltage Across Electrode Channel for 2 kHz Data Rate 150 –40°C –5°C +25°C +55°C +85°C AVDD = 3.3V 40 AVDD = 3.3V GAIN0 GAIN1 GAIN2 GAIN3 100 20 INL (µV/RTI) DNL ERROR (µV RTI) –150 0.3 09660-070 –50 0.3 09660-074 –40 10 0 –10 50 0 –20 –50 –30 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 INPUT VOLTAGE (V) Figure 43. DNL vs. Input Voltage Range Across Temperature AVDD = 3.3V 150 1.1 1.3 1.5 1.7 1.9 AVDD = 3.3V 2.1 2.3 GAIN0 GAIN1 GAIN2 GAIN3 100 50 INL (µV/RTI) 0 0 –50 –50 –100 –100 0.5 0.7 0.9 1.1 1.3 1.5 INPUT VOLTAGE (V) 1.7 1.9 2.1 2.3 –150 0.3 09660-073 INL (µV/RTI) 0.9 Figure 46. INL vs. Input Voltage Across Gain Setting for 16 kHz Data Rate 50 –150 0.3 0.7 INPUT VOLTAGE (V) GAIN0 GAIN1 GAIN2 GAIN3 100 0.5 Figure 44. INL vs. Input Voltage Across Gain Setting for 2 kHz Data Rate 0.5 0.7 0.9 1.1 1.3 1.5 INPUT VOLTAGE (V) 1.7 1.9 2.1 2.3 09660-076 150 –100 0.3 09660-071 –50 0.3 09660-075 –40 Figure 47. INL vs. Input Voltage Across Gain Setting for 128 kHz Data Rate Rev. A | Page 23 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet 0 120 AVDD = 3.3V GAIN 0 DATA RATE = 2kHz FILTER SETTING = 150Hz –20 80 60 LOOP GAIN (dB) –60 –80 –100 –120 40 20 0 –140 –40 –160 –60 –180 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (Hz) 1 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 51. Open-Loop Gain Response of ADAS1000 Right Leg Drive Amplifier Without Loading Figure 48. FFT with 60 Hz Input Signal 150 –80 100m 09660-080 –20 09660-077 AMPLITUDE (dBFS) –40 100 0 AVDD = 3.3V –0.5dBFS 10Hz INPUT SIGNAL –50 100 LOOP GAIN (Phase) AMPLITUDE (dB) SNR 50 0 –100 –150 –200 –250 –50 –300 GAIN 0 GAIN 1 GAIN 2 –350 100m 09660-078 –100 GAIN 3 GAIN SETTING DRDY 2 AVDD 2.48V 09660-079 1 A CH1 100 1k 10k 100k FREQUENCY (Hz) AVDD = 3.3V M1.00ms T 22.1% 10 1M 10M 100M 1G Figure 52. Open-Loop Phase Response of ADAS1000 Right Leg Drive Amplifier Without Loading Figure 49. SNR and THD Across Gain Settings CH1 2.00V CH2 1.00V 1 09660-081 THD Figure 50. Power Up AVDD Line to DRDY Going Low (Ready) Rev. A | Page 24 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 APPLICATIONS INFORMATION OVERVIEW The ADAS1000/ADAS1000-1/ADAS1000-2 are electro cardiac (ECG) front-end solutions targeted at a variety of medical applications. In addition to ECG measurements, the ADAS1000 version also measures thoracic impedance (respiration) and detects pacing artifacts, providing all the measured information to the host controller in the form of a data frame supplying either lead/vector or electrode data at programmable data rates. The ADAS1000/ADAS1000-1/ADAS1000-2 are designed to simplify the task of acquiring ECG signals for use in both REFIN REFOUT CAL_DAC_IO RLD_SJ RLD_OUT CM_IN monitor and diagnostic applications. Value-added cardiac post processing may be executed externally on a DSP, microprocessor, or FPGA. The ADAS1000/ADAS1000-1/ ADAS1000-2 are designed for operation in both low power, portable telemetry applications and line powered systems; therefore, the parts offer power/noise scaling to ensure suitability to these varying requirements. The devices also offer a suite of dc and ac test excitation via a calibration DAC feature and CRC redundancy checks in addition to read-back of all relevant register address space. DRIVEN LEAD AMP – VREF CALIBRATION DAC SHIELD CM_OUT/WCT SHIELD DRIVE AMP + VCM_REF (1.3V) ADCVDD, DVDD 1.8V REGULATORS ADCVDD DVDD ADAS1000 10kΩ COMMONMODE AMP 10kΩ IOVDD + – RESPIRATION DAC AC LEAD-OFF DAC AVDD VCM AC LEAD-OFF DETECTION VREF PACE DETECTION DC LEADOFF/MUXES ECG PATH ECG1_LA AMP ADC CS ECG2_LL AMP SCLK ADC SDI ECG3_RA AMP ECG4_V1 ADC AMP ADC AMP ADC ECG5_V2 FILTERS, CONTROL, AND INTERFACE LOGIC PD RESET SYNC_GANG GPIO0/MCS GPIO1/MSCLK GPIO2/MSDO GPIO3 EXT_RESP_LA EXT_RESP_LL EXT_RESP_RA SDO DRDY AMP ADC MUX RESPDAC_LA RESPIRATION PATH RESPDAC_LL CLOCK GEN/OSC/ EXTERNAL CLK SOURCE CLK_IO REFGND AGND DGND Figure 53. ADAS1000 Simplified Block Diagram Rev. A | Page 25 of 80 XTAL1 XTAL2 09660-011 RESPDAC_RA ADAS1000/ADAS1000-1/ADAS1000-2 CAL_DAC_IO RLD_SJ VREF CALIBRATION DAC CM_IN CM_OUT/WCT SHIELD SHIELD DRIVE AMP AVDD IOVDD ADCVDD, DVDD 1.8V REGULATORS VCM_REF (1.3V) ADCVDD DVDD ADAS1000-1 COMMONMODE AMP 10kΩ AC LEAD-OFF DAC RLD_OUT DRIVEN LEAD AMP VCM 10kΩ REFIN REFOUT Data Sheet VREF AC LEAD-OFF DETECTION ECG PATH ECG1_LA AMP ADC CS ECG2_LL AMP SCLK ADC SDI ECG3_RA DC LEADOFF/MUXES AMP ADC FILTERS, CONTROL, AND INTERFACE LOGIC DRDY PD RESET SYNC_GANG ECG4_V1 AMP SDO ADC GPIO0/MCS GPIO1/MSCLK ECG5_V2 GPIO2/MSDO GPIO3 ADC CLOCK GEN/OSC/ EXTERNAL CLK SOURCE REFGND AGND DGND Figure 54. ADAS1000-1 Simplified Block Diagram Rev. A | Page 26 of 80 XTAL1 XTAL2 CLK_IO 09660-012 AMP Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 REFIN REFOUT CAL_DAC_IN RLD_SJ AVDD CM_IN VREF 10kΩ COMMONMODE AMP 10kΩ AC LEAD-OFF DAC ADCVDD, DVDD 1.8V REGULATORS IOVDD ADCVDD DVDD ADAS1000-2 VREF AC LEAD-OFF DETECTION ECG PATH ECG1 AMP ADC CS ECG2 AMP SCLK ADC SDI ECG3 DC LEADOFF/MUXES AMP ADC FILTERS, CONTROL, AND INTERFACE LOGIC SDO DRDY PD AMP ADC RESET SYNC_GANG AMP ADC GPIO0 GPIO1 ECG4 ECG5 REFGND AGND 09660-013 GPIO2 GPIO3 DGND Figure 55. ADAS1000-2 Slave Device Simplified Block Diagram Rev. A | Page 27 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet ECG INPUTS—ELECTRODES/LEADS The ADAS1000/ADAS1000-1/ADAS1000-2 ECG product consists of 5 ECG inputs and a reference drive, RLD (right leg drive). In a typical 5-lead/vector application, four of the ECG inputs (ECG3_RA, ECG1_LA, ECG2_LL, ECG4_V1) would be used in addition to the RLD path. This leaves one spare ECG path (which could be used for other purposes, such as calibration or temperature measurement). Both V1 and V2 input channels can be used for alternative measurements if desired. When used in this way, the negative terminal of the input stage can be switched to the fixed internal VCM_REF = 1.3 V; see details in Table 48. In a 5-lead system, the ADAS1000/ADAS1000-1/ADAS1000-2 can provide Lead I, Lead II, and Lead III data or electrode data directly via the serial interface at all frame rates. The other ECG leads can be calculated by the user’s software from either the lead data or the electrode data provided by the ADAS1000/ ADAS1000-1/ADAS1000-2. Note that in 128 kHz data rate, lead data is only available when configured in analog lead mode as shown in Figure 57. Digital lead mode is not available for this data rate. A 12-lead (10-electrode) system can be achieved using one ADAS1000 or ADAS1000-1 device ganged together with one ADAS1000-2 slave device as described in the Gang Mode Operation section. Here, 9 ECG electrodes and one RLD electrode achieve the 10 electrode system, again leaving one spare ECG channel that could be used for alternate purposes as suggested previously. In such a system, having nine dedicated electrodes benefits the user by delivering lead information based on electrode measurements and calculations rather than deriving leads from other lead measurements. Table 10 outlines the calculation of the leads (vector) from the individual electrode measurements. Table 10. Lead Composition 1 ADAS1000 or ADAS1000-1 12 Leads Achieved by Adding ADAS1000-2 Slave Lead Name I II III aVR 2 aVL2 aVF2 V1’ V2’ V3’ V4’ V5’ V6’ Composition LA – RA LL – RA LL – LA RA – 0.5 × (LA + LL) LA – 0.5 × (LL + RA) LL – 0.5 × (LA + RA) V1 – 0.333 × (LA + RA + LL) V2 – 0.333 × (LA + RA + LL) V3 – 0.333 × (LA + RA + LL) V4 – 0.333 × (LA + RA + LL) V5 – 0.333 × (LA + RA + LL) V6 – 0.333 × (LA + RA + LL) Equivalent −0.5 × (I + II) 0.5 × (I − III) 0.5 × (II + III) These lead compositions apply when the master ADAS1000 device is configured into lead mode (analog lead mode or digital lead mode) with VCM = WCT = (RA + LA + LL)/3. When configured for 12-lead operation with a master and slave device, the VCM signal derived on the master device (CM_OUT) is applied to the CM_IN of the slave device. For correct operation of the slave device, the device must be configured in electrode mode (see the FRMCTL register in Table 35). 2 These augmented leads are not calculated within the ADAS1000, but can be derived in the host DSP/microcontroller/FPGA. 1 Rev. A | Page 28 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 The ADAS1000/ADAS1000-1/ADAS1000-2 implementation uses a dc-coupled approach, which requires that the front end be biased to operate within the limited dynamic range imposed by the relatively low supply voltage. The right leg drive loop performs this function by forcing the electrical average of all selected electrodes to the internal 1.3 V level, VCM_REF, maximizing each channel’s available signal range. ECG CHANNEL The ECG channel consists of a programmable gain, low noise, differential preamplifier; a fixed gain anti-aliasing filter; buffers; and an ADC (see Figure 56). Each electrode input is routed to its PGA noninverting input. Internal switches allow the PGA’s inverting inputs to be connected to other electrodes and/or the Wilson central terminal to provide differential analog processing (analog lead mode), to a computed average of some or all electrodes, or the internal 1.3 V common-mode reference (VCM_REF). The latter two modes support digital lead mode (leads computed on-chip) and electrode mode (leads calculated off-chip). In all cases, the internal reference level is removed from the final lead data. All ECG channel amplifiers use chopping to minimize 1/f noise contributions in the ECG band. The chopping frequency of ~250 kHz is well above the bandwidth of any signals of interest. The 2-pole anti-aliasing filter has ~65 kHz bandwidth to support digital pace detection while still providing greater than 80 dB of attenuation at the ADC’s sample rate. The ADC itself is a 14-bit, 2 MHz SAR converter; 1024 × oversampling helps achieve the required system performance. The ADC’s full-scale input range is 2 × VREF, or 3.6 V, although the analog portion of the ECG channel limits the useful signal swing to about 2.8 V. ADAS1000 AVDD ELECTRODE ELECTRODE EXTERNAL RFI AND DEFIB PROTECTION EXTERNAL RFI AND DEFIB PROTECTION PREAMP G = 1, 1.5, 2, 3 + DIFF AMP BUFFER FILTER G = 1.4 – fS VREF ADC 14 ELECTRODE VCM SHIELD DRIVER Figure 56. Simplified Schematic of a Single ECG Channel Rev. A | Page 29 of 80 09660-014 PATIENT CABLE TO COMMON-MODE AMPLIFIER FOR DRIVEN LEG AND SHIELD DRIVER ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Digital Lead Configuration and Calculation ELECTRODE/LEAD FORMATION AND INPUT STAGE CONFIGURATION When the ADAS1000/ADAS1000-1/ADAS1000-2 are configured for digital lead mode (see the FRMCTL register, 0x0A[4], Table 35), the digital core will calculate each lead from the electrode signals. This is straightforward for Lead I/ Lead II/Lead III. Calculating V1’ and V2’ requires WCT, which is also computed internally for this purpose. This mode ignores the common-mode configuration specified in the CMREFCTL register (0x05). Digital lead calculation is only available in 2 kHz and 16k Hz data rates. The input stage of the ADAS1000/ADAS1000-1/ADAS1000-2 can be arranged in several different manners. The input amplifiers are differential amplifiers and can be configured to generate the leads in the analog domain, before the ADCs. In addition to this, the digital data can be configured to provide either electrode or lead format under user control as described in Table 35. This allows maximum flexibility of the input stage for a variety of applications. Single-Ended Input Electrode Analog Lead Configuration and Calculation In this mode, the electrode data are digitized relative to the common-mode signal, VCM, which can be arranged to be any combination of the contributing ECG electrodes. Commonmode generation is controlled by the CMREFCTL register as described in Table 30. Leads are configured in the analog input stage when CHCONFIG = 1, as shown in Figure 58. This uses a traditional in-amp structure where lead formation is performed prior to digitization, with WCT created using the common-mode amplifier. While this results in the inversion of Lead II in the analog domain, this is digitally corrected so output data have the proper polarity. 0 0 1 2 3 4 5 6 7 0 0 0 1 MODE WORD1 WORD2 In this mode, all electrodes are digitized relative to a common electrode, for example, RA. Standard leads must be calculated by post processing the output data of the ADAS1000/ADAS1000-1/ ADAS1000-2. See Figure 60. WORD3 WORD5 LEAD I SINGLE-ENDED INPUT, DIGITALLY CALCULATED LEADS (LA − RA) LEAD II V1’ V2’ (LL − RA) (LL − LA) (V1 − WCT4) (V2 − WCT4) LEAD I COMMON ELECTRODE (CE) (LA − RA) LEADS (HERE RA ELECTRODE IS CONNECTED TO THE CE ELECTRODE (CM_IN) AND V3 IS ON ECG3 INPUT)5 LEAD II V1’ V2’ 0 1 0 ANALOG LEADS6 LEAD I (LA − RA) 1 0 0 SINGLE-ENDED INPUT ELECTRODE RELATIVE TO VCM7 1 0 1 LEADS FORMED RELATIVE TO A COMMON ELECTRODE (CE) 5 LEAD III WORD4 V3’ (LL − RA) (V3 – RA) − (LA − RA) − (LL − RA) (V1 − RA) − (LA − RA) + (LL − RA) (V2 − RA) − (LA − RA) + (LL − RA) 3 3 3 LEAD II LEAD III (LL − RA) (LL − LA) V1’ (V1 − VCM) V2’ (V2 − VCM) LA − VCM LL − VCM RA − VCM V1 − VCM V2 − VCM LA − CE V2 − CE V3 − CE LL − CE V1 − CE REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE. REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL INPUT (ANALOG LEAD MODE). REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED. WILSON CENTRAL TERMINAL (WCT) = (RA + LA + LL)/3, THIS IS A DIGITALLY CALCULATED WCT BASED ON THE RA, LA, LL MEASUREMENTS. COMMON ELECTRODE MODE AS SHOWN IN FIGURE 60. ANALOG LEAD MODE AS SHOWN IN FIGURE 58. SINGLE-ENDED INPUT ELECTRODE MODE AS SHOWN IN FIGURE 59. Figure 57. Electrode and Lead Configurations Rev. A | Page 30 of 80 09660-061 0x0A 0x01 0x05 [4]1 [10]2 [8]3 Common Electrode Configuration Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 CM_OUT/WCT VCM = WCT = (LA + LL + RA)/3 COMMONMODE AMP ECGCTL 0x01[10] CHCONFIG = 1 FRMCTL 0x0A[4] DATAFMT = 0 DIFFERENTIAL INPUT – LEAD FORMAT LEAD I + (LA – RA) ADC AMP ECG1_LA – LEAD III (LL – LA) + AMP ECG2_LL ADC – LEAD II (LL – RA)* + AMP ECG3_RA ADC – *GETS MULITPLED BY –1 IN DIGITAL + AMP ECG4_V1 ADC V1’ = V1 – WCT – WCT = (LA + LL + RA)/3 + AMP ECG5_V2 ADC V2’ = V2 – WCT – WCT = (LA + LL + RA)/3 09660-015 CM_IN for example RA COMMON ELECTRODE CE IN Figure 58. Flexible Front-End Configuration—Showing Analog Lead Mode Configuration Relative to Wilson Central Terminal (WCT) VCM CM_OUT/WCT COMMONMODE AMP COMMON MODE CAN BE ANY COMBINATION OF ELECTRODES ECGCTL 0x01[10] CHCONFIG = 0 FRMCTL 0x0A[4] DATAFMT = 1 SINGLE ENDED ELECTRODE FORMAT ECG1_LA + AMP ADC + AMP ADC + AMP ADC + AMP ADC + AMP ADC LA – VCM – ECG 2_LL LL – VCM – ECG3_RA RA – VCM – ECG4_V1 V1 – VCM – ECG5_V2 V2 – VCM CM_IN for example, RA COMMON ELECTRODE CE IN FRMCTL 0x0A[4] = 0 CONFIGURES SINGLE-ENDED LEAD FORMAT WHERE LEADS ARE CALCULATED DIGITALLY AFTER ADC PROCESSING. Figure 59. Flexible Front-End Configuration—Showing Single-Ended Electrode Configuration Rev. A | Page 31 of 80 09660-016 – ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet VCM = RA CM_OUT/WCT COMMONMODE AMP ECG1_LA ECGCTL 0x01[10] CHCONFIG = 0 FRMCTL 0x0A[4] DATAFMT = 1 CMREFCTL 0x05[8] CEREFEN = 1 SINGLE ENDED ELECTRODE FORMAT + AMP ADC + AMP ADC + AMP ADC + AMP ADC + AMP ADC LA – RA – ECG2_LL – ECG3_RA = V3 – ECG4_V1 LL – RA V3 – RA V1 – RA – – CM_IN = RA COMMON ELECTRODE CE IN V2 – RA FRMCTL 0x0A[4] = 0 CONFIGURES SINGLE-ENDED ELECTRODE FORMAT WHERE LEADS ARE CALCULATED DIGITALLY AFTER ADC PROCESSING. Figure 60. Flexible Front-End Configuration—Showing Common Electrode Configuration Rev. A | Page 32 of 80 09660-017 ECG5_V2 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 DEFIBRILLATOR PROTECTION ESIS FILTERING The ADAS1000/ADAS1000-1/ADAS1000-2 do not include defibrillation protection on chip. Any defibrillation protection required by the application requires external components. Figure 61 and Figure 62 show examples of external defibrillator protection, which is required on each ECG channel, in the RLD path and in the CM_IN path if using the CE input mode. Note that, in both cases, the total ECG path resistance is assumed to be 5 kΩ. The 22 MΩ resistors shown connected to RLD are optional and used to provide a safe termination voltage for an open ECG electrode; they may be larger in value. Note that, if using these resistors, the dc lead-off feature works best with the highest current setting. The ADAS1000/ADAS1000-1/ADAS1000-2 do not include electrosurgical interference suppression (ESIS) protection on chip. Any ESIS protection required by the application requires external components. As shown in Figure 63, signal paths for numerous functions are provided on each ECG channel (except respiration, which only connect to the ECG1_LA, ECG2_LL, and ECG3_RA pins). Note that the channel enable switch occurs after the RLD amplifier connection, thus allowing the RLD to be connected (re-directed into any one of the ECG paths). The CM_IN path is treated the same as the ECG signals. 500Ω 4kΩ ELECTRODE ARGON/NEON BULB PATIENT CABLE RLD ECG1 ADAS1000/ ADAS1000-1/ ADAS1000-2 SP724 22MΩ1 500Ω 4kΩ ELECTRODE 500Ω AVDD 22MΩ1 500Ω ECG2 AVDD ARGON/NEON BULB 09660-018 PATIENT CABLE ECG PATH INPUT MULTIPLEXING SP724 1OPTIONAL. Figure 61. Possible Defibrillation Protection on ECG Paths Using Neon Bulbs PATIENT CABLE ELECTRODE 500Ω 4.5kΩ AVDD ECG1 22MΩ1 SP7242 ADAS1000/ ADAS1000-1/ ADAS1000-2 RLD PATIENT CABLE 22MΩ1 4.5kΩ 500Ω ELECTRODE ECG2 AVDD 09660-019 SP7242 1OPTIONAL. 2TWO SP724 CHANNELS PER ELECTRODE MAY PROVIDE BEST PROTECTION. Figure 62. Possible Defibrillation Protection on ECG Paths Using Diode Protection RLD AMP RESPIRATION INPUT DCLO CURRENT ACLO CURRENT CALDAC INPUT AMPLIFIER ECG PIN + – CHANNEL ENABLE TO FILTERING MUX FOR LEAD CONFIG, COMMON ELECTRODE + – TO CM AVERAGING ADAS1000 Figure 63. Typical ECG Channel Input Multiplexing Rev. A | Page 33 of 80 VCM FROM CM AVERAGING 09660-020 1.3V VCM_REF ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet common-mode block. If the physical connection to each electrode is buffered, these buffers are omitted for clarity. COMMON-MODE SELECTION AND AVERAGING The common-mode signal can be derived from any combination of one or more electrode channel inputs, the fixed internal common-mode voltage reference, VCM_REF, or an external source connected to the CM_IN pin. One use of the latter arrangement is in gang mode where the master device creates the Wilson central terminal for the slave device(s). The fixed reference option is useful when measuring the calibration DAC test tone signals or while attaching electrodes to the patient, where it allows a usable signal to be obtained from just two electrodes. There are several restrictions on the use of the switches: • • • If SW1 is closed, SW7 must be open. If SW1 is open, at least one electrode switch (SW2 to SW7) must be closed. SW7 can be closed only when SW2 to SW6 are open, so that the 1.3 V VCM_REF gets summed in only when all ECG channels are disconnected. The CM_OUT output is not intended to supply current or drive resistive loads, and its accuracy is degraded if it is used to drive anything other than the slave ADAS1000-2 devices. An external buffer is required if there is any loading on the CM_OUT pin. The flexible common-mode generation allows complete user control over the contributing channels. It is similar to, but independent of, circuitry that creates the right leg drive (RLD) signal. Figure 64 shows a simplified version of the ADAS1000 CM_IN SW1 SW2 + – ECG1_LA VCM CM_OUT SW3 ECG2_LL SW4 ECG3_RA SW5 ECG4_V1 SW6 ECG5_V2 (WHEN SELECTED, IT GETS SUMMED IN ON EACH ECG CHANNEL) 09660-021 SW7 VCM_REF = 1.3V Figure 64. Common-Mode Generation Block Table 11. Truth Table for Common-Mode Selection ECGCTL Address 0x01 1 PWREN 0 1 1 1 1 DRVCM X X 0 0 0 EXTCM X 0 0 0 0 LACM X 0 1 1 1 LLCM X 0 0 1 1 RACM X 0 0 0 1 . 1 . X . 1 . X . X . X 1 2 CMREFCTL Address 0x05 2 V1CM V2CM On Switch X X 0 0 SW7 0 0 SW2 0 0 SW2, SW3 0 0 SW2, SW3, SW4 . . . X X SW1 See Table 26. See Table 30. Rev. A | Page 34 of 80 Description Powered down, paths disconnected Internal VCM_REF = 1.3 V is selected Internal CM selection: LA contributes to VCM Internal CM selection: LA and LL contribute to VCM Internal CM selection: LA, LL, and RA contribute to VCM (WCT) . External VCM selected Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 In some cases, adding lead compensation will prove necessary, while in others lag compensation may be more appropriate. The RLD amplifier’s summing junction is brought out to a package pin (RLD_SJ) to facilitate compensation. WILSON CENTRAL TERMINAL (WCT) The flexibility of the common-mode selection averaging allows the user to achieve a Wilson central terminal voltage from the ECG1_LA, ECG2_LL, ECG3_RA electrodes. The RLD amplifier’s short circuit current capability exceeds regulatory limits. A patient protection resistor is required to achieve compliance. RIGHT LEG DRIVE/REFERENCE DRIVE The right leg drive amplifier or reference amplifier is used as part of a feedback loop to force the patient’s common-mode voltage close to the internal 1.3 V reference level (VCM_REF) of the ADAS1000/ADAS1000-1/ADAS1000-2. This centers all the electrode inputs relative to the input span, providing maximum input dynamic range. It also helps to reject noise and interference from external sources such as fluorescent lights or other patient-connected instruments, and absorbs the dc or ac lead-off currents injected on the ECG electrodes. Within the RLD block, there is lead-off comparator circuitry that monitors the RLD amplifier output to determine whether the patient feedback loop is closed. An open-loop condition, typically the result of the right leg electrode (RLD_OUT) becoming detached, tends to drive the amplifier’s output low. This type of fault is flagged in the header word (see Table 52), allowing the system software to take action by notifying the user, redirecting the reference drive to another electrode via the internal switches of the ADAS1000/ ADAS1000-1/ADAS1000-2, or both. The detection circuitry is local to the RLD amplifier and remains functional with a redirected reference drive. Table 30 provides details on reference drive redirection. The RLD amplifier can be used in a variety of ways as shown in Figure 65. Its input can be taken from the CM_OUT signal using an external resistor. Alternatively, some or all of the electrode signals can be combined using the internal switches. The DC gain of the RLD amplifier is set by the ratio of the external feedback resistor (RFB) to the effective input resistor, which can be set by an external resistor, or alternatively, a function of the number of selected electrodes as configured in the CMREFCTL register (see Table 30). In a typical case, using the internal resistors for RIN, all active electrodes would be used to derive the right leg drive, resutling in a 2 kΩ effective input resistor. Achieving a typical dc gain of 40 dB would thus require a 200 kΩ feedback resistor. While reference drive redirection may be useful in the event that the right leg electrode cannot be reattached, some precautions must be observed. Most important is the need for a patient protection resistor. Because this is an external resistor, it does not follow the redirected reference drive; some provision for continued patient protection is needed external to the ADAS1000/ADAS1000-1/ADAS1000-2. Any additional resistance in the ECG paths will certainly interfere with respiration measurement and may also result in an increase in noise and decrease in CMRR. The dynamics and stability of the RLD loop depend on the chosen dc gain and the resistance and capacitance of the patient cabling. In general, loop compensation using external components is required, and must be determined experimentally for any given instrument design and cable set. The RLD amplifier is designed to stably drive a maximum capacitance of 5 nF based on the gain configuration (see Figure 65) and assuming a 330 kΩ patient protection resistor. EXTERNALLY SUPPLIED COMPONENTS CZ TO SET RLD LOOP GAIN 2nF 40kΩ RIN* RLD_SJ 100kΩ RZ 4MΩ RFB* RLD_OUT CM_OUT/WCT 10kΩ SW2 10kΩ SW3 10kΩ SW4 10kΩ SW5 10kΩ ELECTRODE LL ELECTRODE RA ELECTRODE V1 ELECTRODE V2 SW6 CM_IN OR CM BUFFER OUT VCM_REF (1.3V) – SW1 ELECTRODE LA + 10kΩ RLD_INT_REDIRECT *EXTERNAL RESISTOR RIN IS OPTIONAL. IF DRIVING RLD FROM THE ELECTRODE PATHS, THEN THE SERIES RESISTANCE WILL CONTRIBUTE TO THE RIN IMPEDANCE. WHERE SW1 TO SW5 ARE CLOSED, RIN = 2kΩ. RFB SHOULD BE CHOSEN ACCORDINGLY FOR DESIRED RLD LOOP GAIN. 09660-022 ADAS1000 Figure 65. Right Leg Drive—Possible External Component Configuration Rev. A | Page 35 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet either case, all active channels use the same detection thresholds. CALIBRATION DAC Within the ADAS1000/ADAS1000-1, there are a number of calibration features. The 10-bit calibration DAC can be used to correct channel gain errors (to ensure channel matching) or to provide several test tones. The options are as follows: • • • DC voltage output (range: 0.3 V to 2.7 V). The DAC transfer function for dc voltage output is code 0.3 V + 2.4 V× 10 (2 − 1) 1 mV p-p sine wave of 10 Hz or 150 Hz 1 mV 1 Hz square wave A lead-off event sets a flag in the frame header word (see Table 52). Identification of which electrode is off is available as part of the data frame or as a register read from the leadoff status register (Register LOFF, see Table 45). In the case of ac lead-off, information about the amplitude of the lead-off signal(s) can be read back through the serial interface (see Table 50). DC Lead-Off Detection Internal switching allows the calibration DAC signals to be routed to the input of each ECG channel (see Figure 63). Alternatively, it can be driven out from the CAL_DAC_IO pin, enabling measurement and correction for external error sources in the entire ECG signal chain and/or for use as an input to the ADAS1000-2 companion chip calibration input. To ensure a successful update of the calibration DAC (see Table 34), the host controller must issue four additional SCLK cycles after writing the new calibration DAC register word. GAIN CALIBRATION The gain for each ECG channel can be adjusted to correct for gain mismatches between channels. Factory trimmed gain correction coefficients are stored in nonvolatile memory on-chip for GAIN 0, GAIN 1, and GAIN 2; there is no factory calibration for GAIN 3. The default gain values can be overwritten by user gain correction coefficients, which are stored in volatile memory and available by addressing the appropriate gain control registers (see Table 49). The gain calibration applies to the ECG data available on the standard interface and applies to all data rates. LEAD-OFF DETECTION This method injects a small programmable dc current into each input electrode. When an electrode is properly connected, the current flows into the right leg (RLD_OUT) and produces a minimal voltage shift. If an electrode is off, the current charges that pin’s capacitance, causing the voltage at the pin to float positive and create a large voltage change that is detected by the comparators in each channel. The dc lead-off detection current can be programmed via the serial interface. Typical currents range from 10 nA to 70 nA in 10 nA steps. The propagation delay for detecting a dc lead-off event depends on the cable capacitance and the programmed current. It is approximately Delay = Voltage × Cable Capacitance/Programmed Current For example: Delay = 1.2 V × (200 pF/70 nA) = 3.43 ms AC Lead-Off Detection The alternative method of sensing if the electrodes are connected to the patient is based on injecting ac currents into each channel and measuring the amplitudes of the resulting voltages. The system uses a fixed carrier frequency slightly above 2 kHz, high enough to be removed by the ADAS1000/ ADAS1000-1/ ADAS1000-2 on-chip digital filters without introducing phase or amplitude artifacts into the ECG signal. An ECG system must be able to detect if an electrode is no longer connected to the patient. The ADAS1000/ADAS1000-1/ ADAS1000-2 support two methods of lead-off detection: either ac or dc lead-off detection. The two systems are independent and can be used singly or together under the control of the serial interface (see Table 27). The polarity of the ac lead-off signal can be configured on a per-electrode basis. All electrodes can be driven in phase, or some can be driven with reversed polarity to minimize the total injected ac current. Drive amplitude is also programmable. The propagation delay for detecting an ac lead-off event is <10 ms. For both ac and dc lead-off detection, the upper and lower threshold voltages are programmable via Table 37 and Table 38. Note that these programmed thresholds voltage vary with the ECG channel gain. The threshold voltages are not affected by the current level that is programmed. SHIELD DRIVER DC lead-off detection uses fixed gain-independent upper and lower threshold voltages. AC lead-off detection offers user-programmable thresholds; because the detection is performed digitally, it may be necessary to adjust the thresholds, depending on the selected ECG channel gain. In Note that the ac lead-off function is disabled when the calibration DAC is enabled. The shield drive amplifier is a unity gain amplifier. Its purpose is to drive the shield of the ECG cables. For power consumption purposes, it can be disabled if not in use. Note that, the SHIELD pin is shared with the respiration pin function, where it can be muxed to be one of the pins for external capacitor connection. If the pin is being used for the respiration feature, the shield function is not available. In this case, if the application requires Rev. A | Page 36 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Only one lead measurement can be made at one time. The respiration measurement path is not suited for use as additional ECG measurements because the internal configuration and demodulation do not align with an ECG measurement; however, the EXT_RESP_LA, EXT_RESP_RA, or EXT_RESP_LL paths can be multiplexed into one of the ECG ADC paths, if required, as discussed in the Extend Switch On Respiration Paths section. a shield drive, an external amplifier connected to the CM_OUT pin can be used. RESPIRATION (ADAS1000 MODEL ONLY) The respiration measurement is performed by driving a high frequency (programmable from 46.5 kHz to 64 kHz) differential current into two electrodes; the resulting impedance variation caused by breathing causes the differential voltage to vary at the respiration rate. The signal is ac-coupled onto the patient. The acquired signal is AM, with a carrier at the driving frequency and a shallow modulation envelope at the respiration frequency. The modulation depth is greatly reduced by the resistance of the customer-supplied RFI and ESIS protection filters, in addition to the impedance of the cable and the electrode to skin interface (see Table 12). The goal is to measure small ohm variation to sub ohm resolution in the presence of large series resistance. The circuit itself consists of a respiration DAC that drives the accoupled current at a programmable frequency onto the chosen pair of electrodes. The resulting variation in voltage is amplified, filtered, and synchronously demodulated in the digital domain; what results is a digital signal that represents the total thoracic or respiration impedance, including cable and electrode contributions. While it is heavily low-pass filtered on-chip, the user is required to further process it to extract the envelope and perform the peak detection needed to establish breathing (or lack thereof). Internal Respiration Capacitors The internal respiration function uses an internal RC network (5 kΩ/100 pF), and this circuit is capable of 200 mΩ resolution (with up to 5 kΩ total path and cable impedance). The current is ac-coupled onto the same pins that the measurement is sensed back on. Figure 66 shows the measurement on Lead I, but, similarly, the measurement can be configured to measure on either Lead II or Lead III. The internal capacitor mode requires no external capacitors and produces currents of ~64 µA p-p amplitude when configured for maximum amplitude setting (±1V) through the RESPCTRL register (see Table 28). Table 12. Maximum Allowable Cable and Thoracic Loading Cable Resistance R < 1 kΩ 1 kΩ < R < 2.5 kΩ 2.5 kΩ < R < 5 kΩ Cable Capacitance C < 1200 pF C < 400 pF C < 200 pF Rthoracic < 2 kΩ Respiration measurement is available on one of the leads (Lead I, Lead II, or Lead III) or on an external path via a pair of dedicated pins (EXT_RESP_LA, EXT_RESP_RA, or EXT_RESP_LL). ±1V RESPIRATION DAC DRIVE + 46.5kHz TO 64kHz ADAS1000 5kΩ 100pF CABLE AND ELECTRODE IMPEDANCE < 5kΩ FILTER IN-AMP AND ANTI-ALIASING EXT_RESP_LA LL CABLE ECG2_LL OVERSAMPLED HPF FILTER EXT_RESP_LL RA CABLE SAR ADC LPF MAGNITUDE AND PHASE ECG3_RA FILTER EXT_RESP_RA 100pF 5kΩ RESPIRATION DAC DRIVE– 46.5kHz TO 64kHz ±1V Figure 66. Simplified Respiration Block Diagram Rev. A | Page 37 of 80 09660-023 LA CABLE RESPIRATION MEASURE ECG1_LA ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet External Respiration Path External Respiration Capacitors The EXT_RESP_xx pins are provided for use either with the ECG electrode cables or, alternatively, with a dedicated external sensor independent of the ECG electrode path. Additionally, the EXT_RESP_xx pins are provided such that the user can measure the respiration signal at the patient side of the RFI/ ESIS protection filters. In this case, the user must take precautions to protect the EXT_RESP_xx pins from any signals applied that are in excess of the operating voltage range. If necessary, the ADAS1000 allows the user to connect external capacitors into the respiration circuit to achieve higher resolution (<200 mΩ). This level of resolution requires that the cable impedance be ≤1 kΩ. The diagram in Figure 67 shows the connections at RESPDAC_xx paths for the extended respiration configuration. Again, the EXT_RESP_xx paths can be connected at the patient side of any filtering circuit; however, the user must provide protection for these pins. While this external capacitor mode requires external components, it can deliver a larger signal-to-noise ratio. Note again that respiration can be measured on only one lead (at one time); therefore, only one pair of external respiration paths (and external capacitors) may be required. ±1V 46.5kHz TO 64kHz 1nF TO 10nF RESPDAC_LA RESPIRATION DAC DRIVE + ADAS1000 1kΩ RESPDAC_LL 1kΩ 5kΩ 100pF MUTUALLY EXCLUSIVE CABLE AND ELECTRODE IMPEDANCE < 1kΩ RESPIRATION MEASURE ECG1_LA FILTER IN-AMP AND ANTI-ALIASING EXT_RESP_LA LL CABLE RA CABLE ECG2_LL FILTER OVERSAMPLED HPF EXT_RESP_LL SAR ADC LPF MAGNITUDE AND PHASE ECG3_RA FILTER EXT_RESP_RA MUTUALLY EXCLUSIVE 100pF 5kΩ 1nF TO 10nF RESPDAC_RA 1kΩ 46.5kHz TO 64kHz RESPIRATION DAC DRIVE – ±1V Figure 67. Respiration Measurement Using External Capacitor Rev. A | Page 38 of 80 09660-024 LA CABLE Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 1nF TO 10nF RESPDAC_LA 50kHz TO 56kHz 1kΩ 100Ω RESPIRATION DAC DRIVE + ve CABLE AND ELECTRODE IMPEDANCE < 1kΩ RESPIRATION MEASURE LA CABLE EXT_RESP_LA IN-AMP AND ANTI-ALIASING 10kΩ RA CABLE ADAS1000 ±1V OVERSAMPLED HPF SAR ADC GAIN 10kΩ LPF MAGNITUDE AND PHASE EXT_RESP_RA 1/2 OF AD8606 10kΩ 0.9V 1nF TO 10nF RESPDAC_RA 1kΩ 100Ω 46.5kHz TO 64kHz ±1V 09660-025 REFOUT = 1.8V 10kΩ RESPIRATION DAC DRIVE – ve 1/2 OF AD8606 Figure 68. Respiration Using External Capacitor and External Amplifiers If required, further improvements in respiration performance may be possible with the use of an instrumentation amplifier and op amp external to the ADAS1000. The instrumentation amplifier must have sufficiently low noise performance to meet the target performance levels. This mode uses the external capacitor mode configuration and is shown in Figure 68. Bit 14 of the RESPCTL register (Table 28) allows the user to bypass the on-chip amplifier when using an external instrumentation amplifier. Respiration Carrier In applications where an external signal generator is used to develop a respiration carrier signal, that external signal source can be synchronized to the internal carrier using the signal available on GPIO3 when Bit 7, RESPEXTSEL, is enabled in the respiration control register (see Table 28). EXTEND SWITCH ON RESPIRATION PATHS There is additional multiplexing on the external respiration inputs to allow them to serve as additional electrode inputs to the existing five ECG ADC channels. This approach allows a user to configure eight electrode inputs; however, it is not intended as a true 8-channel/12-lead solution. Time overheads will be required to reconfigure the multiplexer arrangement using the serial interface in addition to filter the latency as described in Table 14. The user has full control over the SW1/SW2/SW3 configuration as outlined in Table 48. SW1a SW2a SW3a SW1b SW2b SW3b EVALUATING RESPIRATION PERFORMANCE ECG simulators offer a convenient means of studying the ADAS1000’s performance. While many simulators offer a variable-resistance respiration capability, care must be taken when using this feature. SW1c SW2c TO ECG1_LA CHANNEL TO ECG2_LL CHANNEL TO ECG3_RA CHANNEL SW3c TO ECG4_V1 CHANNEL SW1e SW2e TO ECG5_V2 CHANNEL SW3e TO RESPIRATION CIRCUITRY EXT_RESP_LA EXT_RESP_RA EXT_RESP_LL Rev. A | Page 39 of 80 Figure 69. Alternative Use of the Respiration Paths 09660-032 Some simulators use electrically programmable resistors, often referred to as digiPOTs, to create the time-varying resistance to be measured by the respiration function. The capacitances at the digitPOT's terminals are often unequal and code-dependent, and these unbalanced capacitances can give rise to unexpectedly large or small results on different leads for the same programmed resistance variation. Best results are obtained with a purposebuilt fixture that carefully balances the capacitance presented to each ECG electrode. SW1d SW2d SW3d ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet PACING ARTIFACT DETECTION FUNCTION (ADAS1000 ONLY) The pacing artifact validation function qualifies potential pacing artifacts and measures the width and amplitude of valid pulses. These parameters are stored in and available from any of the pace dataregisters (Address 0x1A, Address 0x3A to Address 0x3C). This function runs in parallel with the ECG channels. Digital detection is performed using a state machine operating on the 128 kHz 16-bit data from the ECG decimation chain. The main ECG signals are further decimated before appearing in the 2 kHz output stream so that detected pace signals are not perfectly time-aligned with fully-filtered ECG data. This time difference is deterministic and may be compensated for. The pacing artifact validation function can detect and measure pacing artifacts with widths from 100 μs to 2 ms and with amplitudes of <400 μV to >1000 mV. Its filters are designed to reject heartbeat, noise, and minute ventilation pulses. The flowchart for the pace detection algorithm is shown in Figure 70. The ADAS1000 pace algorithm can operate with the ac lead-off and respiration impedance measurement circuitry enabled. Once a valid pace has been detected in the assigned leads, the pace-detected flags appear in the header word (see Table 52) at the start of the packet of ECG words. These bits indicate that a pace was qualified. Further information on height and width of pace is available by reading the contents of Address 0x1A (Register PACEDATA, see Table 42). This word can be included in the ECG data packet/frame as dictated by the frame control register (see Table 35). The data available in the PACEDATA register is limited to seven bits total for width and height information; therefore, if more resolution is required on the pace height and width, this is available by issuing read commands of the PACExDATA registers (Address 0x3A to Address 0x3C) as shown in Table 51. Some users may not wish to use three pace leads for detection. In this case, Lead II would be the vector of choice because this lead is likely to display the best pacing artifact. The other two pace instances can be disabled if not in use. The on-chip filtering contributes some delay to the pace signal (see the Pace Latency section). Choice of Leads Three identical state machines are available and can be configured to run on up to three of four possible leads (Lead I, Lead II, Lead III, and aVF) for pacing artifact detection. All necessary lead calculations are performed internally and are independent of EGG channel settings for output data rate, lowpass filter cutoff, and mode (electrode, analog lead, common electrode). These calculations take into account the available front-end configurations as detailed in Table 13. The pace detection algorithm searches for pulses by analyzing samples in the 128 kHz ECG data stream. The algorithm searches for an edge, a peak, and a falling edge as defined by values in the PACEEDGETH, PACEAMPTH, and PACELVLTH registers, along with fixed width qualifiers. The post-reset default register values can be overwritten via the SPI bus, and different values can be used for each of the three pace detection state machines. The first step in pace detection is to search the data stream for a valid leading edge. Once a candidate edge has been detected, the algorithm begins searching for a second, opposite-polarity edge that meets with pulse width criteria and passes the (optional) noise filters. Only those pulses meeting all the criteria are flagged as valid pace pulses. Detection of a valid pace pulse sets the flag(s) in the frame header register and stores amplitude and width information in the PACEDATA register (Address 0x1A; see Table 42). The pace algorithm looks for a negative or positive pulse. Table 13. Pace Lead Calculation 0x01 [10] 1 0 0x05 [8] 2 0 Configuration Digital leads 0 1 Common electrode leads 1 X Analog leads 00 Lead I (LA − RA) LA − RA CH1 − CH3 Lead I CH1 Lead I CH1 01 Lead II (LL − RA) LL − RA CH2 − CH3 Lead II CH2 Lead II −CH3 0x04 [8:3] 3 10 11 Lead III aVF (LL − LA) (Lead II + Lead III)/2 LL − LA LL − (LA + RA)/2 CH2 − CH1 CH2 − (CH1 + CH3)/2 lead II − 0.5 × Lead I Lead II – Lead I CH2 − 0.5 × CH1 CH2 − CH1 Lead III Lead II − 0.5 × Lead I − CH3 − 0.5 × CH1 CH2 Register ECGCTL, Bit CHCONFIG, see Table 26. Register CMREFCTL, Bit CEREFEN, see Table 30. 3 Register PACECTL, Bit PACExSEL [1:0], see Table 29. 1 2 Rev. A | Page 40 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 START ENABLE PACE DETECTION SELECT LEADS START PACE DETECTION ALGORITHM START PULSE WIDTH TIMER LOOK FOR TRAILING EDGE START NOISE FILTERS (if enabled) TRAILING EDGE DETECTED? NO YES NOISE FILTER PASSED? NO YES 2ms > PULSE WIDTH > 100µs NO YES 09660-026 FLAG PACE DETECTED UPDATE REGISTERS WITH WIDTH AND HEIGHT Figure 70. Overview of Pace Algorithm PACE PULSE PACELVLTH LEADING EDGE LEADING EDGE STOP PACEAMPTH PACEEDGETH RECHARGE PULSE Figure 71. Typical Pace Signal Rev. A | Page 41 of 80 09660-027 PACE WIDTH ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Pace Amplitude Threshold Pace Validation Filter 2 This register (Address 0x07, see Table 32) can be used to set the minimum valid pace pulse amplitude: This filter is also used to reject sub threshold pulses such as MV pulses and inductive implantable telemetry systems. It is normally enabled and is controlled via the PACECTL register, Bit 10 (see Table 29). Filter 2 applies to all leads enabled for pace detection. N × VREF , (corresponds to a GAIN × 216 range of 20 µV to 5 mV in the ×1.4 gain setting (GAIN 0)) PACEAMPTH setting = where: N = 0 to 255 (8 bits), register default N = 0x24, (PACEAMPTH = 706 μV in the ×1.4 gain setting) GAIN = 1.4, 2.1, 2.8, or 4.2 (programmable). VREF = 1.8 V. This level would typically be set to be the minimum expected pace amplitude. For best results under most operating conditions for both biventricular and unipolar pacing, it is suggested to set the pace amplitude threshold to a value of approximately 700 μV to 1 mV. It is not recommended to set the threshold below 250 μV to avoid ambient noise from the patient. The amplitude may need to be adjusted much higher than 1 mV when other medical devices are connected to the patient. Pace Edge Threshold This programmable level (Address 0x0E, see Table 39) is used to find a leading edge, signifying the start of a pace pulse: N × VREF (corresponds to a GAIN × 216 range of 20 µV to 5 mV in the ×1.4 gain setting) PACEEDGETH setting = where: If N = 0, PACEEDGETH = PACEAMPTH/2, then N = 0 to 255 (8 bits). GAIN = 1.4, 2.1, 2.8 or 4.2 (programmable). VREF = 1.8 V. Pace Level Threshold This programmable level (Address 0x0F, see Table 40) is used to find the leading edge peak: N × VREF PACELVLTH setting = , signed (FF = −1, GAIN × 216 01 = +1), default = 0 Pace Width Filter When enabled, this filter searches for an edge of opposite polarity to the leading edge with a magnitude of at least half the original trigger. The second edge must be between 100 µs to 2 ms from the original edge. When a valid pace width is detected, the width is stored. When disabled only the minimum pulse width of 100 μs is disabled. This filter is controlled by the PACECTL register, Bit 11 (see Table 29). BIVENTRICULAR PACERS As described previously, the pace algorithm expects the pace pulse to be less than 2 ms wide. In a pacer where both ventricles are paced, they can be paced simultaneously. Where they fall within the width and height limits programmed into the algorithm, a valid pace will be flagged, but only one pace pulse may be visible. With the pace width filter enabled, the pace algorithm seeks pace pulse widths within a 100 μs to 2 ms window. Assuming that this filter is enabled and in a scenario where two ventricle pacer pulses fire at slightly different times, resulting in the pulse showing in the lead as one large, wider pulse, a valid pace is flagged so long as the total width does not exceed 2 ms. PACE DETECTION MEASUREMENTS Design verification of the ADAS1000 digital pace algorithm includes detection of a range of simulated pace signals in addition to using the ADAS1000 and evaluation board with one pacemaker device connected to various simulated loads (approximately 200 Ω to over 2 kΩ) and covering the following 4 waveform corners. • • Minimum pulse width (100 μs), minimum height (to <300 μV) Minimum pulse width (100 μs), maximum height (up to 1.0 V) Maximum pulse width (2 ms), minimum height (to <300 μV) Maximum pulse width (2 ms), maximum height (up to 1.0 V) where: N = 0 to 255 (8 bits). GAIN = 1.4, 2.1, 2.8 or 4.2 (programmable). VREF = 1.8 V. • Pace Validation Filter 1 These scenarios passed with acceptable results. The use of the ac lead-off function had no obvious impact on the recorded pace height, width, or the ability of the pace detection algorithm to identify a pace pulse. The pace algorithm was also evaluated with the respiration carrier enabled; again, no differences in the threshold or pacer detect were noted from the carrier. • This filter is used to reject sub threshold pulses such as minute ventilation (MV) pulses and inductive coupled implantable telemetry systems. It is typically enabled and is controlled via the PACECTL register, Bit 9 (see Table 29) register. Filter 1 applies to all leads enabled for pace detection. Rev. A | Page 42 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 delays are summarized in Table 14 and must be taken into account to enable correct positioning of the pace event relative to the ECG data. While these experiments validate the pace algorithm over a confined set of circumstances and conditions, they do not replace end system verification of the pacer algorithm. This can be performed in only the end system, using the system manufacturer’s specified cables and validation data set. EVALUATING PACE DETECTION PERFORMANCE ECG simulators offer a convenient means of studying the performance and ability of the ADAS1000 to capture pace signals over the range of widths and heights defined by the various regulatory standards. While the pace detection algorithm of the ADAS1000 is designed to conform to medical instrument standards, some simulators put out signals wider (or narrower) than called for in the standards, and these will be rejected as invalid by the algorithm of the ADAS1000. The pace width acceptance window of the ADAS1000 is the tightest at the 2 ms limit. If this proves problematic, margin can be obtained by reducing the master clock frequency. As an example, using an 8.000 MHz crystal in place of the recommended 8.192 MHz crystal increases the high limit of the pace acceptance window from 2.000 ms to 2.048 ms. The low limit also increases; however, this does not impair the ability of the algorithm to detect 100 µs pace pulses. Changing the clock frequency affects all of the other ADAS1000 frequency-related functions. Continuing with the 8.000 MHz example, the −3 dB frequencies for ECG scales by a factor of 8000/8192, with 40 Hz becoming 39.06 Hz and 150 Hz becoming 146.5 Hz, which are both still well within regulatory requirements. The respiration and ac leads-off frequencies, as well as the output data rates, also scale by the same 8000/8192 fraction. PACE LATENCY The pace algorithm always examines 128 kHz, 16-bit ECG data, regardless of the selected frame rate and ECG filter setting. A pace pulse is qualified when a valid trailing edge is detected and is flagged in the next available frame header. Pace and ECG data is always correctly time-aligned at the 128 kHz frame rate, but the additional filtering inherent in the slower frame rates delays the frame's ECG data relative to the pace pulse flag. These There is an inherent one-frame-period uncertainty in the exact location of the pace trailing edge. PACE DETECTION VIA SECONDARY SERIAL INTERFACE (ADAS1000 AND ADAS1000-1 ONLY) The ADAS1000/ADAS1000-1 provide a second serial interface for users who wish to implement their own pace detection schemes. This interface is configured as a master interface. It provides ECG data at the 128 kHz data rate only. The purpose of this interface is to allow the user to access the ECG data at a rate sufficient to allow them to run their own pace algorithm, while maintaining all the filtering and decimation of the ECG data that the ADAS1000/ADAS1000-1 offer on the standard serial interface (2 kHz and 16 kHz data rates). This dedicated pace interface uses three of the four GPIO pins, leaving one GPIO pin available even when the secondary serial interface is enabled. Note that the on-chip digital calibration to ensure channel gain matching does not apply to data that is available on this interface. This interface is discussed in more detail in the Secondary Serial Interface section. FILTERING Figure 72 shows the ECG digital signal processing. The ADC sample rate is programmable. In high performance mode, it is 2.048 MHz; in low power mode, the sampling rate is reduced to 1.024 MHz. The user can tap off framing data at one of three data rates, 128 kHz, 16 kHz, or 2 kHz. Note that although the data-word width is 24 bits for the 2 kHz and 16 kHz data rate, the usable bits are 19 and 18, respectively. The amount of decimation depends on the selected data rate, with more decimation for the lower data rates. Four selectable low-pass filter corners are available at the 2 kHz data rate. Filters are cleared by a reset. Table 14 shows the filter latencies at the different data rates. AC LEAD-OFF DETECTION 2.048MHz PACE DETECTION 128kHz –3dB AT 13kHz ACLO CARRIER NOTCH 2kHz AVAILABLE DATA RATE CHOICE OF 1: 128kHz DATA RATE 16-BITS WIDE 128kHz 16kHz DATA RATE 24-BITS WIDE 18 USABLE BITS 16kHz –3dB AT 3.5kHz 16kHz 2kHz DATA RATE 24-BITS WIDE 19 USABLE BITS 2kHz –3dB AT 450Hz 40Hz 150Hz 250Hz (PROGRAMMABLE BESSEL ) ~7Hz Figure 72. ECG Channel Filter Signal Flow Rev. A | Page 43 of 80 CALIBRATION 31.25Hz DATA RATE 24-BITS WIDE ~22 USABLE BITS 09660-028 ADC DATA 14-BITS 2.048MHz ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 14. Relationship of ECG Waveform to Pace Indication 1, 2, 3 Data Rate 2 kHz 16 kHz 128 kHz Conditions 450 Hz ECG bandwidth 250 Hz ECG bandwidth 150 Hz ECG bandwidth 40 Hz ECG bandwidth Apparent Delay of ECG Data Relative to Pace Event 4 0.984 ms 1.915 ms 2.695 ms 7.641 ms 109 μs 0 ECG waveform delay is the time required to reach 50% of final value following a step input. Guaranteed by design, not subject to production test. There is an unavoidable residual uncertainty of 8 μs in determining the pace pulse trailing edge. 4 Add 38 μs to obtain the absolute delay for any setting. 1 2 3 Rev. A | Page 44 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 The ADAS1000/ADAS1000-1/ADAS1000-2 have a high performance, low noise, on-chip 1.8 V reference for use in the ADC and DAC circuits. The REFOUT of one device is intended to drive the REFIN of the same device. The internal reference is not intended to drive significant external current; for optimum performance in gang operation with multiple devices, each device should use its own internal reference. An external 1.8 V reference can be used to provide the required VREF. In such cases, there is an internal buffer provided for use with external reference. The REFIN pin is a dynamic load with an average input current of approximately 100 μA per enabled channel, including respiration. When the internal reference is used, the REFOUT pin requires decoupling with a10 μF capacitor with low ESR (0.2 Ω maximum) in parallel with 0.01 μF capacitor to REFGND, these capacitors should be placed as close to the device pins as possible and on the same side of the PCB as the device. GANG MODE OPERATION While a single ADAS1000 or ADAS1000-1 provides the ECG channels to support a five-electrode and one-RLD electrode (or up to 8-lead) system, the device has also been designed so that it can easily extend to larger systems by paralleling up multiple devices. In this mode of operation, an ADAS1000 or ADAS1000-1 master device can easily be operated with one or more ADAS1000-2 slave devices. In such a configuration, one of the devices (ADAS1000 or ADAS1000-1) is designated as master, and any others are designated as slaves. It is important that the multiple devices operate well together; with this in mind, the pertinent inputs/outputs to interface between master and slave devices have been made available. Note that when using multiple devices, the user must collect the ECG data directly from each device. If using a traditional 12-lead arrangement where the Vx leads are measured relative to WCT, the user should configure the ADAS1000 or ADAS1000-1 master device in lead mode with the slave ADAS1000-2 device configured for electrode mode. The LSB size for electrode and lead data differs (see Table 41 for details). In gang mode, all devices must be operated in the same power mode (either high performance or low power) and the same data rate. Master/Slave When a device is configured as a slave (ADAS1000-2), the SYNC_GANG and CLK_IO pins are set as inputs. Synchronizing Devices The ganged devices need to share a common clock to ensure that conversions are synchronized. One approach is to drive the slave CLK_IO pins from the master CLK_IO pin. Alternatively, an external 8.192 MHz clock can be used to drive the CLK_IO pins of all devices. The CLK_IO powers up high impedance until configured in gang mode. In addition, the SYNC_GANG pin is used to synchronize the start of the ADC conversion across multiple devices. The SYNC_GANG pin is automatically driven by the master and is an input to all the slaves. SYNC_GANG is in high impedance until enabled via gang mode. When connecting devices in gang mode, the SYNC_GANG output is triggered once when the master device starts to convert. Therefore, to ensure that the slave device(s) receive this synchronization signal, configure the slave device first for operation and enable conversions, followed by issuing the conversion signal to the ECGCTL register in the master device. MASTER SLAVE 0 CLK_OI SYNC_GANG CM_OUT CAL_DAC_IO CLK_IO SYNC_GANG CM_IN CAL_DAC_IO SLAVE 1 CLK_IO SYNC_GANG CM_IN CAL_DAC_IO 09660-029 VOLTAGE REFERENCE Figure 73. Master/Slave Connections in Gang Mode, Using Multiple ADAS1000/ADAS1000-1/ADAS1000-2 Devices Calibration The calibration DAC signal from one device (master) can be output on the CAL_DAC_IO pin and used as the calibration input for other devices (slaves) when used in the gang mode of operation. This ensures that they are all being calibrated using the same signal which results in better matching across channels. This does not happen automatically in gang mode but, rather, must be configured via Table 34. The ADAS1000 or ADAS1000-1 can be configured as a master or slave, while the ADAS1000-2 can only be configured as a slave. A device is selected as a master or slave using Bit 5, master, in the ECGCTL register (see Table 26). Gang mode is enabled by setting Bit 4, gang, in the same register. When a device is configured as a master, the SYNC_GANG pin is automatically set as an output. Rev. A | Page 45 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Right Leg Drive The ADAS1000/ADAS1000-1 have a dedicated CM_OUT pin serving as an output and a CM_IN pin as an input. In gang mode, the master device determines the common-mode voltage based on the selected input electrodes. This commonmode signal (on CM_OUT) can then be used by subsequent slave devices (applied to CM_IN) as the common-mode reference. All electrodes within the slave device are then measured with respect to the CM_IN signal from the master device. See the CMREFCTL register in Table 30 for more details on the control via the serial interface. Figure 74 shows the connections between a master and slave device using multiple ADAS1000/ADAS1000-2 devices. The right leg drive comes from the master device. If the internal RLD resistors of the slave device are to contribute to the RLD loop, tie the RLD_SJ pins of master and slave together. REFOUT CAL_DAC_IO REFIN RLD_SJ Common Mode Sequencing Devices into Gang Mode When entering gang mode with multiple devices, both devices can be configured for operation, but the conversion enable bit (ECGCTL register, Bit 2, Table 26) of the master device should be set after the conversion enable bit of the slave device. When the master device conversion signal is set, the master device generates one edge on its SYNC_GANG pin. This applies to any slave SYNC_GANG inputs, allowing the devices to synchronize ADC conversions. CM_IN CM_OUT/ RLD_OUT WCT SHIELD AVDD IOVDD DRIVEN LEAD AMP VREF CALIBRATION DAC SHIELD DRIVE AMP VCM_REF (1.3V) RESPIRATION DAC ADCVDD, DVDD 1.8V REGULATORS ADAS1000 LEAD-OFF DETECTION 10kΩ PACE DETECTION MUXES CS SCLK SDI SDO DRDY SYNC_GANG 5 × ECG PATH ELECTRODES ×5 AMP ADC EXT RESP_LA AMP ADC EXT RESP LL EXT RESP_RA RESPIRATION PATH FILTERS, CONTROL, AND INTERFACE LOGIC CLOCK GEN/OSC/ EXTERNAL CLK SOURCE XTAL1 REFOUT CAL_DAC_IN RLD_SJ ADCVDD, DVDD 1.8V REGULATORS VCM_REF (1.3V) TAKE LEAD DATA CLK_IO XTAL2 AVDD CM_IN VREF AC LEAD-OFF DAC DVDD (optional) COMMONMODE AMP AC LEAD-OFF DAC REFIN ADCVDD (optional) IOVDD ADCVDD (optional) DVDD (optional) ADAS1000-2 SLAVE COMMONMODE AMP LEAD-OFF DETECTION 5 × ECG PATH ELECTRODES ×5 AMP ADC FILTERS, CONTROL, AND INTERFACE LOGIC CLOCK GEN/OSC/ EXTERNAL CLK SOURCE CS SCLK SDI SDO DRDY SYNC_GANG TAKE ELECTRODE DATA CLK_IO Figure 74. Configuring Multiple Devices to Extend Number of Electrodes/Leads (This Example Uses ADAS1000 as Master and ADAS1000-2 as Slave. Similarly the ADAS1000-1 Could be Use as Master.) Rev. A | Page 46 of 80 09660-030 PACE DETECTION MUXES Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 15. Some Possible Arrangements for Gang Operation Slave 1 ADAS1000-2 ADAS1000-2 ADAS1000-3 ADAS1000-2 ADAS1000-2 ADAS1000-2 Slave 2 ADAS1000-2 Features ECG, respiration, pace ECG, respiration, pace ECG, respiration, pace ECG ECG ECG, respiration, pace INTERFACING IN GANG MODE Number of Leads 12-lead + spare ADC channel 15-lead + 3 spare ADC channels 12-lead (derived leads) 12-lead + spare ADC channel 12-lead (derived leads) 12-lead (derived leads) have the relevant synchronized data. Alternative methods might use individual controllers for each device or separate SDO paths. As shown in Figure 74, when using multiple devices, the user must collect the ECG data directly from each device. The example shown in Figure 75 illustrates one possibility of how to approach interfacing to a master and slave device. For some applications, digital isolation is required between the host and the ADAS1000. The example shown illustrates a means to ensure that the number of lines requiring isolation is minimized. Note that SCLK, SDO, and SDI are shared here with individual CS lines. This requires the user to read the data on both devices twice as fast to ensure that they can capture all the data to maintain the chosen data rate and ensure they MICROCRONTROLLER/ DSP Number of Electrodes 10 ECG, CM_IN, RLD 15 ECG, CM_IN, RLD 8 ECG, CM_IN, RLD 10 ECG, CM_IN, RLD 8 ECG, CM_IN, RLD 8 ECG, CM_IN, RLD SCLK SDI CS1 CS2 SDO MASTER SLAVE SCLK SCLK SDI SDI CS CS DRDY (OPTIONAL) DRDY (OPTIONAL) SDO SDO Figure 75. One Method of Interfacing to Multiple Devices Rev. A | Page 47 of 80 09660-031 Master ADAS1000 ADAS1000 ADAS1000 ADAS1000-1 ADAS1000-3 ADAS1000-4 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet SERIAL INTERFACES The ADAS1000/ADAS1000-1 also provide an optional secondary serial interface that is capable of providing ECG data at the 128 kHz data rate for users wishing to apply their own digital pace detection algorithm. This is a master interface that operates with an SCLK of 20.48 MHz. STANDARD SERIAL INTERFACE The standard serial interface is LVTTL-compatible when operating from a 2.3 V to 3.6 V IOVDD supply. This is the primary interface for controlling the ADAS1000/ADAS1000-1/ ADAS1000-2, reading and writing registers, and reading frame data containing all the ECG data-words and other status functions within the device. The SPI is controlled by the following five pins: • • • • • CS (frame synchronization input). Asserting CS low selects the device. When CS is high, data on the SDI pin is ignored. If CS is inactive, the SDO output driver is disabled, so that multiple SPI devices can share a common SDO pin. The CS pin can be tied low to reduce the number of isolated paths required. When CS is tied low, there is no frame around the data-words; therefore, the user must be aware of where they are within the frame. All data-words with 2 kHz and 16 kHz data rates contain register addresses at the start of each word within the frame. Users can resynchronize the interface by holding SDI high for 64 SCLK cycles, followed by a read of any register so that SDI is brought low for the first bit of the following word. SDI (serial data input pin): Data on SDI is clocked into the device on the rising edges of SCLK. SCLK (clocks data in and out of the device). SCLK should idle high when CS is high. SDO (serial data output pin for data readback). Data is shifted out on SDO on the falling edges of SCLK. The SDO output driver is high-Z when CS is high. DRDY (data ready, optional). Data ready when low, busy when high. Indicates the internal status of the ADAS1000/ADAS1000-1/ADAS1000-2 digital logic. It is driven high/busy during reset. If data frames are enabled and the frame buffer is empty, this pin is driven busy/high. If the frame buffer is full, this pin is driven low/ready. If data frames are not enabled, this pin is driven low to indicate that the device is ready to accept register read/write commands. When reading packet data, the entire packet must be read to allow the DRDY return back high. MICROCONTROLLER/ DSP ADAS1000 SCLK CS SDI SDO DRDY SCLK CS MOSI MISO GPIO 09660-033 The ADAS1000/ADAS1000-1/ADAS1000-2 are controlled via a standard serial interface allowing configuration of registers and readback of ECG data. This is an SPI-compatible interface that can operate at SCLK frequencies up to 40 MHz. Figure 76. Serial Interface Write Mode The serial word for a write is 32 bits long, MSB first. The serial interface works with both a continuous and a burst (gated) serial clock. The falling edge of CS starts the write cycle. Serial data applied to SDI is clocked into the ADAS1000/ ADAS1000-1/ADAS1000-2 on rising SCLK edges. At least 32 rising clock edges must be applied to SCLK to clock in 32 bits of data before CS is taken high again. The addressed input register is updated on the rising edge of CS. For another serial transfer to take place, CS must be taken low again. Register writes are used to configure the device. Once the device is configured and enabled for conversions, frame data can be initiated to start clocking out ECG data on SDO at the programmed data rate. Normal operation for the device is to send out frames of ECG data. Typically, register reads and writes should be needed only during start-up configuration. However, it is possible to write new configuration data to the device while in framing mode. A new write command is accepted within the frame and, depending on the nature of the command, there may be a need to flush out the internal filters (wait periods) before seeing usable framing data again. Write/Read Data Format Address, data, and the read/write bits are all in the same word. Data is updated on the rising edge of CS or the first cycle of the following word. For all write commands to the ADAS1000/ ADAS1000-1/ADAS1000-2, the data-word is 32 bits, as shown in Table 16. Similarly, when using data rates of 2 kHz and 16 kHz, each word is 32 bits (address bits and data bits). Table 16. Serial Bit Assignment (Applies to All Register Writes, 2 kHz and 16 kHz Reads) B31 R/W [B30:B24] Address bits[6:0] [B23:B0] Data bits [23:0] (MSB first) For register reads, data is shifted out during the next word, as shown in Table 17. Table 17. Read/Write Data Stream Digital Pin SDI SDO Rev. A | Page 48 of 80 Command 1 Read Address 1 Command 2 Read Address 2 Address 1 Read Data 1 Command 2 Write Address 3 Address 2 Read Data 2 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Read Mode In the 128 kHz data rate, all write words are still 32-bit writes but the read words in the data packet are now 16 bits (upper 16 bits of register). There are no address bits, only data bits. Register space that is larger than 16 bits spans across 2 × 16-bit words (for example, pace and respiration). Although the primary reading function within the ADAS1000/ ADAS1000-1/ADAS1000-2 is the output of the ECG frame data, the devices also allow reading of all configuration registers. To read a register, the user must first address the device with a read command containing the particular register address. If the device is already in data framing mode, the read register command can be interleaved between the frames by issuing a read register command during the last word of frame data. Data shifted out during the next word is the register read data. To return to framing mode, the user must re-enable framing by issuing a read of the frame header register (Address 0x40) (see Table 52). This register write can be used to flush out the register contents from the previous read command. Data Frames/Packets The general data packet structure is shown in Table 18. Data can be received in two different frame formats. For the 2 kHz and 16 kHz data rates, a 32-bit data format is used (where the register address is encapsulated in the upper byte, identifying the word within the frame) (see Table 20). For the 128 kHz data rate, words are provided in 16-bit data format (see Table 21). When the configuration is complete, the user can begin reading frames by issuing a read command to the frame header register (see Table 52). The ADAS1000/ADAS1000-1/ADAS1000-2 continue to make frames available until another register address is written (read or write command). To continue reading frame data, continue to write all zeros on SDI, which is a write of the NOP register (Address 0x00). A frame is interrupted only when another read or write command is issued. Table 18. Example of Reading Registers and Frames SDI ….. NOP SDO ….. Frame data Read Address N Frame CRC Read frames NOP NOP ….. Register Data N Frame header Frame data ….. Regular register reads are always 32 bits long and MSB first. Each frame can be a large amount of data plus status words. CS can toggle between each word of data within a frame, or it can be held constantly low during the entire frame. Serial Clock Rate The SCLK can be up to 40 MHz, depending on the IOVDD voltage level as shown in Table 5. The minimum SCLK frequency is set by the requirement that all frame data be clocked out before the next frame becomes available. By default, a frame contains 11 × 32 bit words when reading at 2 kHz or 16 kHz data rates; similarly, a frame contains 13 × 16bit words when reading at 128 kHz. The default frame configuration does not include the optional respiration phase word; however, this word can be included as needed. Additionally any words not required can be excluded from the frame. To arrange the frame with the words of interest, configure the appropriate bits in the frame control register (see Table 35). The complete set of words per frame are 12 × 32-bit words for the 2 kHz or 16 kHz data rates, or 15 × 16-bit words at 128 kHz. SCLK (min) = frame_rate × words_per_frame × bits_per_word The minimum SCLK for the various frame rates is shown in Table 19. Table 19. SCLK Clock Frequency vs. Packet Data/Frame Rates Frame Rate 128 kHz 16 kHz 2 kHz Any data not available within the frame can be read between frames. Reading a register interrupts the frame and requires the user to issue a new read command of Address 0x40 (see Table 52) to start framing again. 1 Word Size 16 bits 32 bits 32 bits Maximum Words/Frame 1 15 words 12 words 12 words Minimum SCLK 30.72 MHz 6.14 MHz 768 kHz This is the full set of words that a frame contains. It is programmable and can be configured to provide only the words of interest. See Table 35. Table 20. Default 2 kHz and 16 kHz Data Rate: 32-Bit Frame Word Format Register Address Header 0x40 Lead I/LA 0x11 Lead II/LL 0x12 Lead III/RA 0x13 V1’/V1 0x14 V2’/V2 0x15 PACE 0x1A RESPM 0x1B RESPPH 0x1C LOFF 0x1D GPIO 0x06 CRC 0x41 Table 21. Default 128 kHz Data Rate: 16-Bit Frame Word Format 1 Register Address 1 Header 0x40 Lead I/LA 0x11 Lead II/LL 0x12 Lead III/RA 0x13 V1’/V1 0x14 V2’/V2 0x15 PACE1 PACE2 0x1A Respiration phase words (2x 16-bit words) are not shown in this frame, but could be included. Rev. A | Page 49 of 80 RESPM1 RESPM2 0x1B LOFF 0x1D GPIO 0x06 CRC 0x41 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Internal operations are synchronized to the internal master clock at either 2.048 MHz or 1.024 MHz (ECGCTL[3]: HP = 1 and HP = 0, respectively, see Table 26). Because there is no guaranteed relationship between the internal clock and the SPI's SCLK signal, an internal handshaking scheme is used to ensure safe data transfer between the two clock domains. A full handshake requires three internal clock cycles and imposes an upper speed limit on the SCLK frequency when reading frames with small word counts. This is true for all data frame rates. SCLK (max) = (1.024 MHz × (1 + HP) × words_per_frame × bits_per_word)/3; or 40 MHz, whichever is lower. Exceeding the maximum SCLK frequency for a particular operating mode causes erratic behavior in the DRDY signal and results in the loss of data. Data Rate and Skip Mode When reading packets of data, the entire data packet must be read; otherwise, DRDY stays low. There are three methods of detecting DRDY status. • • • Although the standard frame rates available are 2 kHz, 16 kHz, and 128 kHz, there is also a provision to skip frames to further reduce the data rate. This can be configured in the frame control register (see Table 35). Data Ready (DRDY) The DRDY pin is used to indicate that a frame composed of decimated data at the selected data rate is available to read. It is high when busy and low when ready. Send commands only when the status of DRDY is low or ready. During power-on, the status of DRDY is high (busy) while the device initializes itself. When initialization is complete, DRDY goes low and the user can start configuring the device for operation. When the device is configured and enabled for conversions by writing to the conversion bit (CNVEN) in the ECGCTL register, the ADCs start to convert and the digital interface starts to make data available, loading them into the buffer when ready. If conversions are enabled and the buffer is empty, the device is not ready and DRDY goes high. Once the buffer is full, DRDY goes low to indicate that data is ready to be read out of the device. If the device is not enabled for conversions, the DRDY ignores the state of the buffer full status. DRDY pin. This is an output pin from the ADAS1000/ ADAS1000-1/ADAS1000-2 that indicates the device read or busy status. No data is valid while this pin is high. The DRDY signals that data is ready to be read by driving low and remaining low until the entire frame has been read. It is cleared when the last bit of the last word in the frame is clocked onto SDO. The use of this pin is optional. SDO pin. The user can monitor the voltage level of the SDO pin by bringing CS low. If SDO is low, data is ready; if high, busy. This does not require clocking the SCLK input. (CPHA = CPOL = 1 only). One of the first bits of valid data in the header word available on SDO is a data ready status bit (see Table 41). Within the configuration of the ADAS1000/ADAS1000-1/ ADAS1000-2, the user can set the header to repeat until the data is ready. See Bit 6 (RDYRPT) in the frame control register in Table 35. Detecting Missed Conversion Data To ensure that the current data is valid, the entire frame must be read at the selected data rate. If a read of the entire frame takes longer than the selected data rate allows, the internal buffer is not loaded with the latest conversion data. The frame header register (see Table 52) provides four settings to indicate an overflow of frame data. The settings of Bits[29:28] report how many frames have been missed since the last valid frame read. A missed frame may occur as a result of the last read taking too long. The data in the current frame is valid data, but it is not the current data. It is the calculation made directly after the last valid read. To clear such an overflow, the user must read the entire frame. Rev. A | Page 50 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 CRC Word ADAS1000 Framed data integrity is provided by CRCs. For the 128 kHz frame rates, the 16-bit CRC-CCITT polynomial is used. For the 2 kHz and 16 kHz frame rates, the 24-bit CRC polynomial used. XTAL1 CLK_IO 09660-034 In both cases, the CRC residue is preset to all 1s and inverted before being transmitted. The CRC parameters are summarized in Table 22. To verify that data was correctly received, software should compute a CRC on both the data and the received checksum. If data and checksum are received correctly, the resulting CRC residue should equal the check constant shown in Table 22. Note that data is shifted through the generator polynomial MSB first, the same order that it is shifted out serially. The bit and byte order of the CRC that is appended to the frame is such that the MSB of the CRC is shifted through the generator polynomial first in the same order as the data so that the CRC residue XOR’d with the inverted CRC at the end of the frame is all 1s (which is why the check constant is identical for all messages). The CRC is based only on the data that is sent out. XTAL2 Figure 77. Input Clock Clocks The ADAS1000/ADAS1000-1/ADAS1000-2 run from an external crystal or clock input frequency of 8.192 MHz. The external clock input is provided for use in gang mode so conversions between the two devices are synchronized. In this mode, the CLK_IO pin is an output from the master and an input from the slave. To reduce power, the CLK_IO is disabled when not in gang mode. All features within the ADAS1000 are a function of the frequency of the externally applied clock. Using a frequency other than the 8.192 MHz previously noted causes scaling of the data rates, filter corners, ac lead off frequency, respiration frequency, and pace algorithm corners accordingly. Table 22. CRC Polynomials Frame Rate 2 kHz, 16 kHz 128 kHz CRC Size 24 bits 16 bits Polynomial x24 + x22 + x20 + x19 + x18 + x16 + x14 + x13 + x11 + x10 + x8 + x7 + x6 + x3 + x1 + x0 x16 + x12 + x5 + x0 Rev. A | Page 51 of 80 Polynomial in Hex 0x15D6DCB 0x11021 Check Constant 0x15A0BA 0x1D0F ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet SECONDARY SERIAL INTERFACE This second serial interface is an optional interface that can be used for the user’s own pace detection purposes. This interface contains ECG data at 128 kHz data rate only. If using this interface, the ECG data is still available on the standard interface discussed previously at lower rates with all the decimation and filtering applied. If this interface is inactive, it draws no power. Data is available in 16-bit words, MSB first. This interface is a master interface, with the ADAS1000/ ADAS1000-1 providing the SCLK, CS, SDO. Is it shared across some of the existing GPIO pins as follows: • • • This interface can be enabled via the GPIO register (see Table 31). CS MISO/GPIO ADAS1000 MASTER SPI MSCLK/GPIO1 MCS/GPIO0 MSDO/GPIO2 09660-035 SCLK Table 23. Master SPI Frame Format; All Words are 16 Bits Header Lead I/LA Lead II/LL Lead III/RA V1’/V1 V2’/V2 CRC The header word consists of four bits of all 1s followed by a 12bit sequence counter. This sequence counter increments after every frame is sent, thereby allowing the user to tell if any frames have been missed and how many. RESET GPIO1/MSCLK GPIO0/MCS GPIO2/MSDO MICROCONTROLLER/ DSP on the falling edge of MSCLK. MSCLK idles high when MCS is deasserted. Figure 78. Master SPI Interface for External Pace Detection Purposes The data format of the frame starts with a header word and five ECG data-words, and completes with the same CRC word as documented in Table 22 for the 128 kHz rate. All words are 16 bits. MSCLK runs at approximately 20 MHz and MCS is asserted for the entire frame with the data available on MSDO There are two methods of resetting the ADAS1000/ADAS1000-1/ ADAS1000-2 to power-on default. Bringing the RESET line low or setting the SWRST bit in the ECGCTL register (Table 26) resets the contents of all internal registers to their power-on reset state. The falling edge of the RESET pin initiates the reset process; DRDY goes high for the duration, returning low when the RESET process is complete. This sequence takes 1.5 ms maximum. Do not write to the serial interface while DRDY is high handling a RESET command. When DRDY returns low, normal operation resumes and the status of the RESET pin is ignored until it goes low again. Software reset using the SWRST bit (see Table 26) requires that a NOP (no operation) command be issued to complete the reset cycle. PD FUNCTION The PD pin powers down all functions in low power mode. The digital registers maintain their contents. The power-down function is also available via the serial interface (ECG control register, see Table 26). Rev. A | Page 52 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 SPI OUTPUT FRAME STRUCTURE (ECG AND STATUS DATA) Three data rates are offered for reading ECG data: low speed 2 kHz/16 kHz rates for electrode/lead data (32-bit words) and a high speed 128 kHz for electrode/lead data (16-bit words). DRDY CS1 EACH SCLK WORD IS 32 CLOCK CYCLES 1 2 3 4 5 6 7 8 9 10 11 SCLK DRIVEN OUTPUT DATA STREAM ORD GPIO ANOTHER FRAME OF DATA CRC W LEA D-OF F RES P MAG IRATIO NITU N DE 2 PAC E DE TEC TION 1 V1’/V V2’/V RA LEA D III/ L A LEA D II/L LEA D I/L HEA DER SDO2 32-BIT DATA WORDS 1 CS MAY BE USED IN ONE OF THE FOLLOWING WAYS: 09660-036 A) HELD LOW ALL THE TIME. B) USED TO FRAME THE ENTIRE PACKET OF DATA. C) USED TO FRAME EACH INDIVIDUAL 32-BIT WORD. 2 SUPER SET OF FRAME DATA, WORDS MAY BE EXCLUDED. Figure 79. Output Frame Structure for 2 kHz and 16 kHz Data Rates with SDO Data Configured for Electrode or Lead Data DRDY CS1 EACH SCLK WORD IS 16 CLOCK CYCLES 1 2 3 4 5 6 8 7 9 10 11 12 13 SCLK DRIVEN OUTPUT DATA STREAM ORD ANOTHER FRAME CRC W GPIO LEA D-OF F RES P MAG IRATIO NITU N DE PAC E V2 V1 RA LL LA HEA DER SDO2 16-BIT DATA WORDS 1 CS 09660-037 MAY BE USED IN ONE OF THE FOLLOWING WAYS: A) HELD LOW ALL THE TIME. B) USED TO FRAME THE ENTIRE PACKET OF DATA. C) USED TO FRAME EACH INDIVIDUAL 16-BIT WORD. 2 SUPER SET OF FRAME DATA, WORDS MAY BE EXCLUDED. Figure 80. Output Frame Structure for 128 kHz Data Rate with SDO Data Configured for Electrode Data (The 128 kHz Data Rate Can Provide Single-Ended Electrode Data or Analog Lead Mode Data Only. Digital Lead Mode Is Not Available at 128 kHz Data Rate.) Rev. A | Page 53 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet SPI REGISTER DEFINITIONS AND MEMORY MAP In 2 kHz and 16 kHz data rates, data takes the form of 32-bit words. Bit A6 to Bit A0 serve as word identifiers. Each 32-bit word has 24 bits of data. A third high speed data rate is also offered: 128 kHz with data in the form of 16-bit words (all 16 bits as data). Table 24. SPI Register Memory Map R/W121 R R/W R/W R/W R/W R/W R/W R/W A[6:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 D[23:0] XXXXXX dddddd dddddd dddddd dddddd dddddd dddddd dddddd Register Name NOP ECGCTL LOFFCTL RESPCTL PACECTL CMREFCTL GPIOCTL PACEAMPTH Table Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 R/W R/W R/W R/W R/W R/W R/W 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E dddddd dddddd dddddd dddddd dddddd dddddd dddddd TESTTONE CALDAC FRMCTL FILTCTL LOFFUTH LOFFLTH PACEEDGETH Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 R/W 0x0F dddddd PACELVLTH Table 40 R R R R R R 0x11 0x12 0x13 0x14 0x15 0x1A XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX LADATA LLDATA RADATA V1DATA V2DATA PACEDATA Table 41 Table 41 Table 41 Table 41 Table 41 Table 42 R 0x1B XXXXXX RESPMAG Table 43 Register Description NOP (no operation) ECG control Lead-off control Respiration control2 Pace detection control Common-mode, reference, and shield drive control GPIO control Pace amplitude threshold2 Test tone Calibration DAC Frame control Filter control AC lead-off upper threshold AC lead-off lower threshold Reset Value 0x000000 0x000000 0x000000 0x000000 0x000F88 0xE00000 0x000000 0x242424 0x000000 0x002000 0x079000 0x000000 0x00FFFF 0x000000 0x000000 Pace edge threshold2 Pace level threshold2 LA or Lead I data LL or Lead II data RA or Lead III data V1 or V1’ data V2 or V2’ data 0x000000 Read pace detection data/status2 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 Read respiration data—magnitude2 0x000000 2 0x000000 R 0x1C XXXXXX RESPPH Table 44 R R R R/W R/W R/W R/W R/W R/W R R R R R R 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x31 0x32 0x33 0x34 0x35 0x3A XXXXXX XXXXXX XXXXXX dddddd dddddd dddddd dddddd dddddd dddddd dddddd dddddd dddddd dddddd dddddd dddddd LOFF DCLEAD-OFF OPSTAT EXTENDSW CALLA CALLL CALRA CALV1 CALV2 LOAMLA LOAMLL LOAMRA LOAMV1 LOAMV2 PACE1DATA Table 45 Table 46 Table 47 Table 48 Table 49 Table 49 Table 49 Table 49 Table 49 Table 50 Table 50 Table 50 Table 50 Table 50 Table 51 Pace1 width and amplitude2 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 R 0x3B dddddd PACE2DATA Table 51 Pace2 width and amplitude2 0x000000 R 0x3C dddddd PACE3DATA Table 51 2 0x000000 R R x 0x40 0x41 Other dddddd XXXXXX XXXXXX FRAMES CRC Reserved13 Table 52 Table 53 Read respiration data—phase Lead-off status DC lead-off Operating state Extended switch for respiration inputs User gain calibration LA User gain calibration LL User gain calibration RA User gain calibration V1 User gain calibration V2 Lead-off amplitude for LA Lead-off amplitude for LL Lead-off amplitude for RA Lead-off amplitude for V1 Lead-off amplitude for V2 Pace3 width and amplitude Frame header Frame CRC Reserved 1 0x800000 0xFFFFFF XXXXXX R/W = register both readable and writable; R = read only. ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. 3 Reserved bits in any register are undefined. In some cases a physical (but unused) memory bit may be present—in other cases not. Do not issue commands to reserved registers/space. Read operations of unassigned bits are undefined. 2 Rev. A | Page 54 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 CONTROL REGISTERS DETAILS For each register address, the default setting is noted in a default column in addition to being noted in the function column by “(default)”; this format applies throughout the register map. Table 25. Serial Bit Assignment B31 R/W [B30:B24] Address bits [B23:B0] Data bits (MSB first) Table 26. ECG Control Register (ECGCTL) Address 0x01, Reset Value = 0x000000 R/W R/W R/W R/W R/W R/W R R/W Default 0 0 0 0 0 0 0 Bit 23 22 21 20 19 [18:11] 10 Name LAEN LLEN RAEN V1EN V2EN Reserved CHCONFIG R/W 00 [9:8] GAIN [1:0] R/W 0 7 VREFBUF R/W 0 6 CLKEXT R/W 0 5 Master R/W 0 4 Gang R/W 0 3 HP R/W 0 2 CNVEN R/W 0 1 PWREN R/W 0 0 SWRST Function ECG channel enable; shuts down power to the channel; the input becomes high-Z. 0 (default) = disables ECG channel. When disabled, the entire ECG channel is shut down and dissipating minimal power. 1 = enables ECG channel. Reserved, set to 0. Setting this bit selects the differential analog front end (AFE) input. See Figure 57. 0 (default) = single-ended input (digital lead mode or electrode mode). 1 = differential input (analog lead mode). Preamplifier and anti-aliasing filter overall gain. 00 (default) = GAIN 0 = ×1.4. 01 = GAIN 1 = ×2.1. 10 = GAIN 2 = ×2.8. 11 = GAIN 3 = ×4.2 (user gain calibration is required for this gain setting). VREF buffer enable. 0 (default) = disabled. 1 = enabled (when using the internal VREF, VREFBUF must be enabled). Use external clock instead of crystal oscillator. The crystal oscillator is automatically disabled if configured as a slave in gang mode and the slave device should receive the clock from the master device. 0 (default) = XTAL is clock source. 1 = CLK_IO is clock source. In gang mode, this bit selects the master (SYNC_GANG pin is configured as an output). When in single channel mode (gang = 0), this bit is ignored. ADAS1000-2 cannot be configured as a master device. 0 (default) = slave. 1 = master. Enable gang mode. Setting this bit causes CLK_IO and SYNC_GANG to be activated. 0 (default) = single channel mode. 1 = gang mode. Selects the noise/power performance. This bit controls the ADC sampling frequency. See the Specifications section for further details. 0 (default) = 1 MSPS, low power. 1 = 2 MSPS, high performance/low noise. Conversion enable. Setting this bit enables the ADC conversion and filters. 0 (default) = idle. 1 = conversion enable. Power enable. Clearing this bit powers down the device. All analog blocks are powered down and the external crystal is disabled. The register contents are retained during power down as long as DVDD is not removed. 0 (default) = power down. 1 = power enable. Software reset. Setting this bit clears all registers to their reset value. This bit automatically clears itself. The software reset requires a NOP command to complete the reset. 0 (default) = NOP. 1 = reset. Rev. A | Page 55 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 27. Lead-Off Control Register (LOFFCTL) Address 0x02, Reset Value = 0x000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 00 Bit 23 22 21 20 19 18 17 16 15 14 13 12 [11:9] [8:7] Name LAPH LLPH RAPH V1PH V2PH CEPH LAACLOEN LLACLOEN RAACLOEN V1ACLOEN V2ACLOEN CEACLOEN Reserved ACCURRENT R/W 00 000 [6:5] [4:2] Reserved DCCURRENT R/W 0 1 ACSEL R/W 0 0 LOFFEN Function AC lead-off phase. 0 (default) = in phase. 1 = 180° out of phase. Individual electrode ac lead-off enable. AC lead-off enables are the OR of ACSEL and the individual ac lead-off channel enables. 0 (default) = ac lead-off disabled. 1 = ac lead-off enabled. Reserved, set to 0. Set current level for ac lead-off. 00 (default) = 12.5 nA rms. 01 = 25 nA rms. 10 = 50 nA rms. 11 = 100 nA rms. Reserved, set to 0. Set current level for dc lead-off (active only for ACSEL = 0). 000 (default) = 0 nA. 001 = 10 nA. 010 = 20 nA. 011 = 30 nA. 100 = 40 nA. 101 = 50 nA. 110 = 60 nA. 111 = 70 nA. DC or AC (out-of-band) lead-off detection. ACSEL acts as a global ac lead-off enable for RA, LL, LA, V1, V2 electrodes (CE ac lead-off is not enabled using ACSEL). AC lead-off enables are the OR of ACSEL and the individual ac lead-off channel enables. If LOFFEN = 0, this bit is don’t care. If LOFFEN = 1, 0 (default) = dc lead-off detection enabled. (Individual ac lead-off can be enabled through Bits[17:12].) 1 = dc lead-off detection disabled. AC lead-off detection enabled (all electrodes except CE electrode). When the calibration DAC is enabled, ac lead-off is disabled. Enable lead-off detection. 0 (default) = lead-off disabled. 1 = lead-off enabled. Rev. A | Page 56 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 28. Respiration Control Register (RESPCTL) Address 0x03, Reset Value = 0x000000 1 R/W Default R/W 0 Bit [23:17] 16 Name Reserved RESPALTFREQ R/W 0 15 RESPEXTSYNC R/W 0 14 RESPEXTAMP R/W 0 13 RESPOUT R/W 0 12 RESPCAP R/W 0000 [11:8] RESPGAIN [3:0] R/W 0 7 RESPEXTSEL R/W 00 [6:5] RESPSEL [1:0] R/W 00 [4:3] RESPAMP R/W 00 [2:1] RESPFREQ R/W 0 0 RESPEN 1 Function Reserved, set to 0. Setting this bit to 1 makes the respiration waveform on the GPIO3 pin periodic every cycle. Use in conjunction with RESFREQ to select drive frequency. 0 (default) = periodic every N cycles (default). 1 = periodic every cycle. Set this bit to 1 to drive the MSB of the respiration DAC out onto the GPIO3 pin. This signal can be used to synchronize an external generator to the respiration carrier. It is a constant period only when RESPALTFREQ = 1. 0 (default) = normal GPIO3 function. 1 = MSB of RESPDAC driven onto GPIO3 pin. For use with an external instrumentation amplifier with respiration circuit. Bypasses the on-chip amplifier stage and input directly to the ADC. See Figure 68. 0 (default) = disabled 1 = enabled Selects external respiration drive output. RESPDAC_RA is automatically selected when RESPCAP = 1 0 (default) = RESPDAC_LL and RESPDAC_RA. 1 = RESPDAC_LA and RESPDAC_RA. Selects source of respiration capacitors. 0 (default) = use internal capacitors. 1 = use external capacitors. Respiration in amp gain (saturates at 10). 0000 (default) = ×1 gain. 0001 = ×2 gain. 0010 = ×3 gain. … 1000 = ×9 gain. 1001 = ×10 gain. 11xx = ×10 gain. Selects between EXT_RESP _LA or EXT_RESP_LL paths. Applies only if the external respiration is selected in RESPSEL. EXT_RESP_RA is automatically enabled. 0 (default) = EXT_RESP_LL. 1 = EXT_RESP_LA. Set leads for respiration measurement. 00 (default) = Lead I. 01 = Lead II. 10 = Lead III. 11 = external respiration path. Set the test tone amplitude for respiration drive signal. 00 (default) = amplitude/8. 01 = amplitude/4. 10 = amplitude/2. 11 = amplitude. Set frequency for respiration. RESPFREQ RESPALTFREQ = 0 RESPALTFREQ = 1 (periodic) 00 (default) 56 kHz 64 kHz 01 54 kHz 56.9 kHz 10 52 kHz 51.2 kHz 11 50 kHz 46.5 kHz Enable respiration. 0 (default) = respiration disabled. 1 = respiration enabled. ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Rev. A | Page 57 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 29. Pace Detection Control Register (PACECTL) Address 0x04, Reset Value = 0x000F88 1 R/W Default R/W 1 Bit [23:12] 11 Name Reserved PACEFILTW R/W 1 10 PACETFILT2 R/W 1 9 PACETFILT1 R/W R/W R/W 11 00 01 [8:7] [6:5] [4:3] PACE3SEL [1:0] PACE2SEL [1:0] PACE1SEL [1:0] R/W R/W R/W 0 0 0 2 1 0 PACE3EN PACE2EN PACE1EN 1 Function Reserved, set to 0 Pace width filter 0 = filter disabled 1 (default) = filter enabled Pace Validation Filter 2 0 = filter disabled 1 (default) = filter enabled Pace Validation Filter 1 0 = filter disabled 1 (default) = filter enabled Set lead for pace detection measurement 00 = Lead I 01 = Lead II 10 = Lead III 11 = Lead aVF Enable pace detection algorithm 0 (default) = pace detection disabled 1 = pace detection enabled ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Rev. A | Page 58 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 30. Common-Mode, Reference, and Shield Drive Control Register (CMREFCTL) Address 0x05, Reset Value = 0xE00000 R/W R/W R/W R/W R/W R/W Default 1 1 1 0 0 Bit 23 22 21 20 19 Name LACM LLCM RACM V1CM V2CM R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 [18:15] 14 13 12 11 10 9 8 Reserved LARLD LLRLD RARLD V1RLD V2RLD CERLD CEREFEN R/W 0000 [7:4] RLDSEL [3:0]1 R/W 0 3 DRVCM R/W 0 2 EXTCM R/W 0 1 RLDSEL1 R/W 0 0 SHLDEN 1 1 Function Common-mode electrode select. Any combination of the five input electrodes can be used to create the common-mode signal, VCM. Bits[23:19] are ignored when Bit 2 is selected. Common mode is the average of the selected electrodes. When a single electrode is selected, common mode is the signal level of that electrode alone. The common-mode signal can be driven from the internal VCM_REF (1.3 V) when Bits [23:19] = 0. 0 = does not contribute to the common mode. 1 = contributes to the common mode. Reserved, set to 0. RLD summing junction. Note that if the RLD amplifier is disabled (using RLDSEL), these switches are not automatically forced open, and the user must disable them using Bits[9:14]. 0 (default) = does not contribute to RLD input. 1 = contributes to RLD input. Common electrode (CE) reference, see Figure 57. 0 (default) = common electrode disabled. 1 = common electrode enabled. Select electrode for reference drive. 0000 (default) = RLD_OUT. 0001 = LA. 0010 = LL. 0011 = RA. 0100 = V1. 0101 = V2. 0110 to 1111 = reserved. Common-mode output. When set, the internally derived common-mode signal is driven out of the common-mode pin. This bit has no effect if an external common mode is selected. 0 (default) = common mode is not driven out. 1 = common mode is driven out of the external common-mode pin. Select the source of common mode (use when operating multiple devices together). 0 (default) = internal common mode selected. 1 = external common mode selected (all the internal common-mode switches are off ). Enable right leg drive reference electrode. 0 (default) = disabled. 1 = enabled. Enable shield drive. 0 (default) = shield drive disabled. 1 = shield drive enabled. ADAS1000 and ADAS1000-1 models only, ADAS1000-2 models does not contain these features. Rev. A | Page 59 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 31. GPIO Control Register (GPIOCTL) Address 0x06, Reset Value = 0x000000 R/W R/W Default 0 0 Bit [23:19] 18 Name Reserved SPIFW Function Reserved, set to 0 Frame secondary SPI words with chip select 0 (default) = MCS asserted for entire frame 1 = MCS asserted for individual word R/W R/W 0 0 17 16 Reserved SPIEN R/W 00 [15:14] G3CTL [1:0] R/W 0 13 G3OUT R 0 12 G3IN R/W 00 [11:10] G2CTL [1:0] R/W 0 9 G2OUT R 0 8 G2IN R/W 00 [7:6] G1CTL [1:0] R/W 0 5 G1OUT R 0 4 G1IN R/W 00 [3:2] G0CTL [1:0] R/W 0 1 G0OUT R 0 0 G0IN Reserved, set to 0 Secondary SPI enable (ADAS1000 and ADAS1000-1 only); SPI interface providing ECG data at 128 kHz data rate for external digital pace algorithm detection, uses GPIO0, GPIO1, GPIO2 pins 0 (default) = disabled 1 = enabled; he individual control bits for GPIO0, GPIO1, GPIO2 are ignored; GPIO3 is not affected by SPIEN State of GPIO3 pin 00 (default) = high impedance 01 = input 10 = output 11 = open drain Output value to be written to GPIO3 when the pin is configured as an output or open drain 0 (default) = low value 1 = high value Read only; input value read from GPIO3 when the pin is configured as an input 0 (default) = low value 1 = high value State of GPIO2 pin 00 (default) = high impedance 01 = input 10 = output 11 = open drain Output value to be written to GPIO2 when the pin is configured as an output or open drain 0 (default) = low value 1 = high value Read only Input value read from GPIO2 when the pin is configured as an input 0 (default) = low value 1 = high value State of GPIO1 pin 00 (default) = high impedance 01 = input 10 = output 11 = open drain Output value to be written to GPIO1 when the pin is configured as an output or open drain 0 (default) = low value 1 = high value Read only; input value read from GPIO1 when the pin is configured as an input 0 (default) = low value 1 = high value State of the GPIO0 pin 00 (default) = high impedance 01 = input 10 = output 11 = open drain Output value to be written to GPIO0 when pin is configured as an output or open drain 0 (default) = low value 1 = high value (Read only) input value read from GPIO0 when pin is configured as an input 0 (default) = low value 1 = high value Rev. A | Page 60 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 32. Pace Amplitude Threshold Register (PACEAMPTH) Address 0x07, Reset Value = 0x242424 1 R/W R/W R/W R/W 1 Default 0010 0100 0010 0100 0010 0100 Bit [23:16] [15:8] [7:0] Name PACE3AMPTH PACE2AMPTH PACE1AMPTH Function Pace amplitude threshold Threshold = N × 2 × VREF/GAIN/216 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 33. Test Tone Register (TESTTONE) Address 0x08, Reset Value = 0x000000 R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 00 Bit 23 22 21 20 19 [18:5] [4:3] Name TONLA TONLL TONRA TONV1 TONV2 Reserved TONTYPE R/W 0 2 TONINT R/W 0 1 TONOUT R/W 0 0 TONEN Function Tone select 0 (default) = 1.3 V VCM_REF 1 = 1 mV sine wave or square wave for TONINT = 1, no connect for TONINT=0 Reserved, set to 0 00 (default) = 10 Hz sine wave 01 = 150 Hz sine wave 1x = 1 Hz, 1 mV square wave Test tone internal or external 0 (default) = external test tone; test tone to be sent out through CAL_DAC_IO and applied externally to enabled channels 1 = internal test tone; disconnects external switches for all ECG channels and connects the calibration DAC test tone internally to all ECG channels; in gang mode, the CAL_DAC_IO is connected, and the slave disables the calibration DAC Test tone out enable 0 (default) = disconnects test tone from CAL_DAC_IO during internal mode only 1 = connects CAL_DAC_IO to test tone during internal mode Enables an internal test tone to drive entire signal chain, from preamplifier to SPI interface; this tone comes from the calibration DAC and goes to the preamplifier through the internal mux; when TONEN (calibration DAC) is enabled, ac lead-off is disabled 0 (default) = disable the test tone 1 = enable the 1 mV sine wave test tone (calibration mode has priority) Rev. A | Page 61 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 34. Calibration DAC Register (CALDAC) Address 0x09, Reset Value = 0x002000 1 R/W R/W Default 0 1 Bit [23:14] 13 Name Reserved CALCHPEN R/W 0 12 CALMODEEN R/W 0 11 CALINT R/W 0 10 CALDACEN R/W 0000000000 [9:0] CALDATA[9:0] 1 Function Reserved, set to 0. Calibration chop clock enable. The calibration DAC output (CAL_DAC_IO) can be chopped to lower 1/f noise. Chopping is performed at 256 kHz. 0 = disabled. 1 (default) = enabled. Calibration mode enable. 0 (default) = disable calibration mode. 1 = enable calibration mode; connect CAL DAC_IO, begin data acquisition on ECG channels. Calibration internal or external. 0 (default) = external calibration to be performed externally by looping CAL_DAC_IO around into ECG channels. 1 = internal calibration; disconnects external switches for all ECG channels and connects calibration DAC signal internally to all ECG channels. Enable 10-bit calibration DAC for calibration mode or external use. 0 (default) = disable calibration DAC. 1 = enable calibration DAC. If a master device and not in calibration mode, also connects the calibration DAC signal out to the CAL_DAC_IO pin for external use. If in slave mode, the calibration DAC is disabled to allow master to drive the slave CAL_DAC_IO pin. When the calibration DAC is enabled, ac lead-off is disabled. Set the calibration DAC value. To ensure successful update of the calibration DAC, the serial interface must issue four additional SCLK cycles after writing the new calibration DAC register word. Rev. A | Page 62 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 35. Frame Control Register (FRMCTL) Address 0x0A, Reset Value = 0x079000 R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 1111 0 Bit 23 22 21 20 19 [18:15] 14 Name LEAD I/LADIS LEADII/LLDIS LEADIII/RADIS V1DIS V2DIS Reserved PACEDIS1 R/W 0 13 RESPMDIS 1 R/W 1 12 RESPPHDIS1 R/W 0 11 LOFFDIS R/W 0 10 GPIODIS R/W 0 9 CRCDIS R/W R/W 0 0 8 7 RESERVED ADIS R/W 0 6 RDYRPT R/W 0 5 Reserved R/W 0 4 DATAFMT R/W 00 [3:2] SKIP[1:0] R/W 00 [1:0] FRMRATE[1:0] 1 Function Include/exclude word from ECG data frame. If the electrode/lead is included in the dataword and the electrode falls off, the data-word is undefined. 0 (default) = included in frame. 1 = exclude from frame. Reserved, set to 1111. Pace detection. 0 (default) = included in frame. 1 = exclude from frame. Respiration magnitude. 0 (default) = included in frame. 1 = exclude from frame. Respiration phase. 0 = included in frame. 1 (default) = exclude from frame. Lead-off status. 0 (default) = included in frame. 1 = exclude from frame. GPIO word disable. 0 (default) = included in frame. 1 = exclude from frame. CRC word disable. 0 (default) = included in frame. 1 = exclude from frame. Reserved, set to 0. Automatically excludes PACEDIS[14], RESPMDIS[13], LOFFDIS[11] words if their flags are not set in the header. 0 (default) = fixed frame format. 1 = autodisable words (words per frame changes). Ready repeat. If this bit is set and the frame header indicates data is not ready, the frame header is continuously sent until data is ready. 0 (default) = always send entire frame. 1 = repeat frame header until ready. Reserved, set to 0 . Sets the output data format, see Figure 57. 0 (default) = digital lead/vector format (available only in 2 kHz and 16 kHz data rates). 1 = electrode format. Skip interval. This field provides a way to decimate the data. 00 (default) = output every frame. 01 = output every other frame 1× = output every 4th frame. Sets the output data rate. 00 (default) = 2 kHz output data rate. 01 = 16 kHz output data rate. 10 = 128 kHz output data rate (DATAFMT must be set to 1). 11 = 31.25 Hz. ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Rev. A | Page 63 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 36. Filter Control Register (FILTCTL) Address 0x0B, Reset Value = 0x000000 R/W R/W R/W Default 0 0 Bit [23:6] 5 Name Reserved MN2K R/W 0 4 N2KBP R/W 00 [3:2] LPF[1:0] R/W 00 [1:0] Reserved Function Reserved, set to 0 2 kHz notch bypass for SPI master 0 (default) = notch filter bypassed 1 = notch filter present 2 kHz notch bypass 0 (default) = notch filter present 1 = notch filter bypassed 00 (default) = 40 Hz 01 = 150 Hz 10 = 250 Hz 11 = 450 Hz Reserved, set to 0 Table 37. AC Lead-Off Upper Threshold Register (LOFFUTH) Address 0x0C, Reset Value = 0x00FFFF R/W Default 0 Bit [23:20] Name Reserved Function Reserved, set to 0 R/W 0 [19:16] ADCOVER[3:0] ADC overrange threshold An ADC out-of-range error is flagged if the ADC output is greater than the overrange threshold; the overrange threshold is offset from the maximum value Threshold = max_value – ADCOVER × 26 R/W 0xFFFF [15:0] LOFFUTH[15:0] 0000 = maximum value (disabled) 0001 = max_value − 64 0010 = max_value − 128 … 1111 = max_value − 960 Applies to ac lead-off upper threshold only; lead-off is detected if the output is ≥ N × 2 × VREF/GAIN/216 0=0V Table 38. AC Lead-Off Lower Threshold Register (LOFFLTH) Address 0x0D, Reset Value = 0x000000 R/W Default 0 Bit [23:20] Name Reserved Function Reserved, set to 0 R/W 0 [19:16] ADCUNDR[3:0] ADC underrange threshold An ADC out-of-range error is flagged if the ADC output is less than the underrange threshold Threshold = min_value + ADCUNDR × 26 R/W 0 [15:0] LOFFLTH[15:0] 0000 = minimum value (disabled) 0001 = min_value + 64 0010 = min_value + 128 … 1111 = min_value + 960 Applies to ac lead-off lower threshold only; lead-off is detected if the output is ≤ N × 2 × VREF/GAIN/216 0=0V Rev. A | Page 64 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 39. Pace Edge Threshold Register (PACEEDGETH) Address 0x0E, Reset Value = 0x000000 1 R/W R/W R/W Default 0 0 Bit [23:16] [15:8] Name PACE3EDGTH PACE2EDGTH R/W 0 [7:0] PACE1EDGTH 1 Function Pace edge trigger threshold 0 = PACEAMPTH/2 1 = VREF/GAIN/216 N = N × VREF/GAIN/216 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 40. Pace Level Threshold Register (PACELVLTH) Address 0x0F, Reset Value = 0x000000 1 R/W R/W R/W Default 0 0 Bit [23:16] [15:8] Name PACE3LVLTH[7:0] PACE2LVLTH[7:0] R/W 0 [7:0] PACE1LVLTH[7:0] 1 Function Pace level threshold; This is a signed value −1 = 0xFF = −VREF/GAIN/216 0 = 0x00 = 0 V +1 = 0x01 = +VREF/GAIN/216 N = N × VREF/GAIN/216 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 41. Read Electrode/Lead Data Registers (Electrode/Lead) Address 0x11 to 0x15, Reset Value = 0x000000 1 R/W Default Bit [31:24] Name Address [7:0] R 0 [23:0] ECG data Function 0x11: LA or Lead I. 0x12: LL or Lead II. 0x13: RA or Lead III. 0x14: V1 or V1’. 0x15: V2 or V2’. Channel data value. Data left justified (MSB) irrespective of data rate. In electrode format, the value is an unsigned integer. In vector format, the value is a signed two’s complement integer format. Lead/Vector format has a 2× range compared to electrode format because it can swing from +VREF to –VREF; therefore, the LSB size is doubled. Electrode format and Analog Lead Format: Minimum value (000…) = 0 V Maximum value (1111….) = VREF/GAIN LSB = (2 × VREF/GAIN)/(2N– 1) Digital Lead format: Minimum value (1000…) = −(VREF/GAIN) Maximum value (0111….) = +VREF/GAIN LSB = 4 × (VREF/GAIN)/(2N – 1) where N = number of data bits: 16 for 128 kHz data rate or 24 for 2 kHz/16 kHz data rate. 1 If using 128 kHz data rate in frame mode, only the upper 16 bits are sent. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. Rev. A | Page 65 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 42. Read Pace Detection Data/Status Register (PACEDATA) Address 0x1A, Reset Value = 0x000000 1, 2, 3 R/W R Default 0 Bit 23 Name Pace 3 detected R 000 [22:20] Pace Channel 3 width R 0000 [19:16] Pace Channel 3 height R 0 15 Pace 2 detected R 000 [14:12] Pace Channel 2 width R 0000 [11:8] Pace Channel 2 height R 0 7 Pace 1 detected R 000 [6:4] Pace Channel 1 width R 0000 [3:0] Pace Channel 1 height Function Pace 3 detected. This bit is set once a pace pulse is detected. This bit is set on the trailing edge of the pace pulse. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. This bit is log2 (width) − 1 of the pace pulse. Width = 2N + 1/128 kHz. This bit is the log2 (height) of the pace pulse. Height = 2N × VREF/GAIN/216. Pace 2 detected. This bit is set once a pace pulse is detected. This bit is set on the trailing edge of the pace pulse. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. This bit is log2 (width) − 1 of the pace pulse. Width = 2N + 1/128 kHz. This bit is the log2 (height) of the pace pulse. Height = 2N × VREF/GAIN/216. Pace 1 detected. This bit is set once a pace pulse is detected. This bit is set on the trailing edge of the pace pulse. 0 = pace pulse not detected in current frame. 1 = pace pulse detected in this frame. This bit is log2 (width) − 1 of the pace pulse. Width = 2N + 1/128 kHz. This bit is the log2 (height) of the pace pulse. Height = 2N × VREF/GAIN/216. If using 128 kHz data rate in frame mode, this word is stretched over two 16-bit words. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. Log data for width and height is provided here to ensure that it fits in one full 32-bit data-word. As a result there may be some amount of error in the resulting value. For more accurate reading, read the 0x3A, 0x3B, 0x3C registers (see Table 51). 3 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. 1 2 Table 43. Read Respiration Data—Magnitude Register (RESPMAG) Address 0x1B, Reset Value = 0x000000 1, 2 R/W R 1 2 Default 0 Bit [23:0] Name Respiration magnitude[23:0] Function Magnitude of respiration signal. This is an unsigned value. 2 × VREF × (224 − 1)/(1.6468 × respiration gain). If using 128 kHz data rate in frame mode, this word is stretched over two 16-bit words. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 44. Read Respiration Data—Phase Register (RESPPH) Address 0x1C, Reset Value = 0x000000 1, 2 R/W R 1 2 Default 0 Bit [23:0] Name Respiration phase[23:0] Function Phase of respiration signal. Can be interpreted as either signed or unsigned value. If unsigned, the range is from 0 to 2π. If signed, the range is from – π to +π. 0x000000 = 0. 0x000001 = 2π/224. 0x400000 = π/2. 0x800000 = +π = − π. 0xC00000 = +3π/2 = − π/2. 0xFFFFFF = +2π(1 − 2−24) = −2π/224. This register is not part of framing data, but may be read by issuing a register read command of this address. ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Rev. A | Page 66 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 45. Lead-Off Status Register (LOFF) Address 0x1D, Reset Value = 0x000000 R/W R Default 0 R R 0 0 R 0 Bit 23 22 21 20 19 18 13 Name RLD lead-off Status LA lead-off status LL lead-off status RA lead-off status V1 lead-off status V2 lead-off status CELO [17:14] 12 11 10 9 8 [7:0] Reserved LAADCOR LLADCOR RAADCOR V1ADCOR V2ADCOR Reserved Function Electrode connection status. If either dc or ac lead-off is enabled, these bits are the corresponding lead-off status. If both dc and ac lead-off are enabled, these bits reflect only the ac lead-off status. DC lead-off is available in the DCLEAD-OFF register (see Table 46). The common electrodes have only dc lead-off detection. An ac lead-off signal can be injected into the common electrode, but there is no ADC input to measure its amplitude. If the common electrode is off, it affects the ac lead-off amplitude of the other electrodes. These bits accumulate in the frame buffer and are cleared when the frame buffer is loaded into the SPI buffer. 0 = electrode is connected. 1 = electrode is disconnected. Reserved. ADC out of range error. These status bits indicate the resulting ADC code is out of range. These bits accumulate in the frame buffer and are cleared when the frame buffer is loaded into the SPI buffer. Reserved. Table 46. DC Lead-Off Register (DCLEAD-OFF) Address 0x1E, Reset Value = 0x000000 1 R/W R Default 0 Bit 23 22 21 20 13 R 0 R 0 [19:14] [8:3] 12 11 10 9 2 R 1 0 [1:0] Name RLD input overrange LA input overrange LL input overrange RA input overrange CE input overrange Reserved Function The dc lead-off detection is comparator based and compares to a fixed level. Individual electrode bits flag indicate if the dc lead-off comparator threshold level has been exceeded. 0 = electrode < overrange threshold, 2.4 V. 1 = electrode > overrange threshold, 2.4 V. RLD input underrange LA input underrange LL input underrange RA input underrange CE input underrange Reserved The dc lead-off detection is comparator based and compares to a fixed level. Individual electrode bits indicate if the dc lead-off comparator threshold level has been exceeded. 0 = electrode > underrange threshold, 0.2 V. 1 = electrode < underrange threshold, 0.2 V. Reserved. This register is not part of framing data, but can be read by issuing a register read command of this address. Rev. A | Page 67 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 47. Operating State Register (OPSTAT) Address 0x1F, Reset Value = 0x000000 1 R/W R R R Default 0 0 0 Bit [23:4] 3 2 Name Reserved Internal error Configuration status R 0 1 PLL lock R 0 0 PLL locked status 1 Function Reserved. Internal digital failure. This is set if an error is detected in the digital core. This bit is set after a reset indicating that the configuration has not been read yet. Once the configuration is set, this bit is ready. 0 = ready. 1 = busy. PLL lock lost. This bit is set if the internal PLL loses lock after it is enabled and locked. This bit is cleared once this register is read or the PWREN bit (Address 0x01[1]) is cleared. 0 = PLL locked. 1 = PLL lost lock. This bit indicates the current state of the PLL locked status. 0 = PLL not locked. 1 = PLL locked. This register is not part of framing data, but can be read by issuing a register read command of this address. This register assists support efforts giving insight into potential areas of malfunction within a failing device. Table 48. Extended Switch for Respiration Inputs Register (EXTENDSW) Address 0x20, Reset Value = 0x000000 R/W R/W Default 0 R/W R/W R/W R/W 1 0 Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Name EXT_RESP_RA to ECG1_LA EXT_RESP_RA to ECG2_LL EXT_RESP_RA to ECG3_RA EXT_RESP_RA to ECG4_V1 EXT_RESP_RA to ECG5_V2 EXT_RESP_LL to ECG1_LA EXT_RESP_LL to ECG2_LL EXT_RESP_LL to ECG3_RA EXT_RESP_LL to ECG4_V1 EXT_RESP_LL to ECG5_V2 EXT_RESP_LA to ECG1_LA EXT_RESP_LA to ECG2_LL EXT_RESP_LA to ECG3_RA EXT_RESP_LA to ECG4_V1 EXT_RESP_LA to ECG5_V2 AUX_V1 0 7 AUX_V2 0 6 NOMATH_V1 0 5 NOMATH_V2 0 [4:0] Reserved Switch SW1a SW1b SW1c SW1d SW1e SW2a SW2b SW2c SW2d SW2e SW3a SW3b SW3c SW3d SW3e Function External respiration electrode input switch to channel electrode input (see Figure 69). 1 0 = switch open. 1 = switch closed. V1 and V2 electrodes can be used for measurement purposes other than ECG. To achieve this, they must be disconnected from the patient VCM voltage provided from the internal common-mode buffer and, instead, connected to the internal VCM_REF level of 1.3 V. Setting the AUX_Vx bits high connects the negative input of the V1 channel amplifier to internal VCM_REF level. This allows the user to make alternative measurements on V1 relative to the VCM_REF level. If using digital lead mode, use these bits in conjunction with Bits[6:5] (NO_MATH_Vx). In digital lead mode, the digital core always calculates V1’ and V2’ with respect to WCT (LA + LL + RA)/3. Where V1 or V2 are used for alternative measurement purposes other than ECG, this math calculation must be disabled. These bits are most likely used in conjunction with Bits[8:7] (AUX_Vx). Set NOMATH_Vx bits high to disable the math calculation in V1 and V2, respectively. Reserved, set to 0. ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these EXT_RESP_xx pins. Rev. A | Page 68 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 49. User Gain Calibration Registers (CALxx) Address 0x21 to Address 0x25, Reset Value = 0x000000 R/W Default Bit Name Function [31:24] Address [7:0] 0x21: calibration LA. 0x22: calibration LL. 0x23: calibration RA. 0x24: calibration V1. 0x25: calibration V2. User can choose between default calibration values or user calibration values for GAIN 0, GAIN 1, GAIN 2. Note that for GAIN 3, there is no factory calibration. 0 = default calibration values (factory calibration). 1 = user calibration values. Reserved, set to 0 Gain calibration value. Result = data × (1 + GAIN × 2−17). The value read from this register is the current gain calibration value. If the USRCAL bit is set to 0, this register returns the default value for the current gain setting. 0x7FF (+2047) = ×1.00000011111111111b. 0x001 (+1) = ×1.00000000000000001b. 0x000 (0) = ×1.00000000000000000b. 0xFFF (−1) = ×0.11111111111111111b. 0x800 (−2048) = ×0.11111100000000000b. R/W 0 23 USRCAL R/W R/W 0 0 [22:12] [11:0] Reserved CALVALUE Table 50. Read AC Lead-Off Amplitude Registers (LOAMxx) Address 0x31 to Address 35, Reset Value = 0x000000 1 R/W Default Bit [31:24] Name Address [7:0] R/W R 0 0 [23:16] [15:0] Reserved LOFFAM 1 Function 0x31: LA ac lead-off amplitude. 0x32: LL ac lead-off amplitude. 0x33: RA ac lead-off amplitude. 0x34: V1 ac lead-off amplitude. 0x35: V2 ac lead-off amplitude. Reserved. Measured amplitude. When ac lead-off is selected, the data is the average of the rectified 2 kHz band-pass filter with an update rate of 8 Hz and cutoff frequency at 2 Hz. The output is the amplitude of the 2 kHz signal scaled by 2/π approximately = 0.6 (average of rectified sine wave). To convert to RMS, scale the output by π/(2√2). Lead-off (unsigned). Minimum 0x0000 = 0 V. LSB 0x0001= VREF/GAIN/216. Maximum 0xFFFF = VREF/GAIN. This register is not part of framing data, but can be read by issuing a register read command of this address. Rev. A | Page 69 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Table 51. Pace Width and Amplitude Registers (PACExDATA) Address 0x3A to Address 0x3C, Reset Value = 0x000000 1, 2 R/W Default Bit [31:24] Name Address [7:0] R 0 [23:8] Pace height R 0 [7:0] Pace width 1 2 Function 0x3A: PACE1DATA 0x3B: PACE2DATA 0x3C: PACE3DATA Measured pace height in signed two’s complement value 0=0 1 = VREF/GAIN/216 N = N × VREF/GAIN/216 Measured pace width in 128 kHz samples N: N/128 kHz = width 12: 12/128 kHz = 93 µs 255:255/128 kHz = 2.0 ms These registers are not part of framing data but can be read by issuing a register read command of these addresses. ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Rev. A | Page 70 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 52. Frame Header (FRAMES) Address 0x40, Reset Value = 0x800000 1 R/W R R Default 1 0 Bit 31 30 Name Marker Ready bit R 0 [29:28] Overflow [1:0] R 0 27 Fault R 0 26 Pace 3 detected R 0 25 Pace 2 detected R 0 24 Pace 1 detected R 0 23 Respiration R 0 22 Lead-off detected R 0 21 DC lead-off detected R 0 20 ADC out of range 0 [19:0] Reserved 1 Function Header marker, set to 1 for the header. Ready bit indicates if ECG frame data is calculated and ready for reading. 0 = ready, data frame follows. 1 = busy. Overflow bits indicate that since the last frame read, a number of frames have been missed. This field saturates at the maximum count. The data in the frame including this header word is valid but old if the overflow bits are >0. When using skip mode (FRMCTL register (0x0A), Bits[3:2]), the overflow bit acts as a flag, where a nonzero value indicates an overflow. 00 = 0 missed. 01 = 1 frame missed. 10 = 2 frames missed. 11 = 3 or more frames missed. Internal device error detected. 0 = normal operation. 1 = error condition. Pace 3 indicates pacing artifact was qualified at most recent point. 0 = no pacing artifact. 1 = pacing artifact present. Pace 2 indicates pacing artifact was qualified at most recent point. 0 = no pacing artifact. 1 = pacing artifact present. Pace 1 indicates pacing artifact was qualified at most recent point. 0 = no pacing artifact. 1 = pacing artifact present. 0 = no new respiration data. 1 = respiration data updated. If both dc and ac lead-off are enabled, this bit is the OR of all the ac lead-off detect flags. If only ac or dc lead-off is enabled, this bit reflects the OR of all dc and ac lead-off flags. 0 = all leads connected. 1 = one or more lead-off detected. 0 = all leads connected. 1 = one or more lead-off detected. 0 = ADC within range. 1 = ADC out of range. Reserved If using 128 kHz data rate in frame mode, only the upper 16 bits are sent. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. Table 53. Frame CRC Register (CRC) Address 0x41, Reset Value = 0xFFFFFF 1 R/W R 1 Bit [23:0] Name CRC Function Cyclic redundancy check The CRC register is a 32-bit word for 2 kHz and 16 kHz data rate and a 16-bit word for 128 kHz rate. See Table 22 for more details. Rev. A | Page 71 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet EXAMPLES OF INTERFACING TO THE ADAS1000 The following examples shows register commands required to configure the ADAS1000 device into particular modes of operation and to start framing ECG data. Example 2: Enable Respiration and Stream Conversion Data 1. Example 1: Initialize the ADAS1000 for ECG Capture and Start Streaming Data 1. 2. 3. 4. 5. Write 1 configures the CMREFCTL register for CM = WCT = (LA + LL + RA)/3; RLD is enabled onto the RLD_OUT electrode. The shield amplifier is enabled. Write 2 configures the FRMCTL register to output nine words per frame/packet. The frame/packet of words consist of the header, five ECG words, pace, respiration magnitude, and lead-off. The frame is configured to always send, irrespective of ready status. The ADAS1000 is in vector format mode with a data rate of 2 kHz. Write 3 addresses the ECGCTL register, enabling all channels into a gain of 1.4, low noise mode, and differential input, which configures the device for analog lead mode. This register also configures the device as a master, using the external crystal as the input source to the XTALx pins. The ADAS1000 is also put into conversion mode in this write. Write 4 issues the read command to start putting the converted data out on the SDO pin. Continue to issue SCLK cycles to read the converted data at the configured packet data rate (2 kHz). The SDI input should be held low when reading back the conversion data because any commands issued to the interface during read of frame/packet are understood to be a change of configuration data and will stop the ADC conversions to allow the interface to process the new command. 2. 3. 4. Write 1 configures the RESPCTL register with a 56 kHz respiration drive signal, gain = 1, driving out through the respiration capacitors and measuring on Lead I. Write 2 issues the read command to start putting the converted data out on the SDO pin. Continue to issue SCLK cycles to read the converted data at the configured packet data rate. Note that this example assumes that the FRMCTL register has already been configured such that the respiration magnitude is available in the data frame, as arranged in Write 2 of Example 1. Example 3: DC Lead-Off and Stream Conversion Data 1. 2. 3. 4. Write 1 configures the LOFFCTL register with a dc lead-off enabled for a lead-off current of 50 nA. Write 2 issues the read command to start putting the converted data out on the SDO pin. Continue to issue SCLK cycles to read the converted data at the configured packet data rate. Note that this example assumes that the FRMCTL register has already been configured such that the dc lead-off word is available in the data frame, as arranged in Write 2 of Example 1. Table 54. Example 1: Initialize the ADAS1000 for ECG Capture and Start Streaming Data Write Command Write 1 Write 2 Write 3 Write 4 Register Addressed CMREFCTL FRMCTL ECGCTL FRAMES Read/Write Bit 1 1 1 0 Register Address 000 0101 000 1010 000 0001 100 0000 Data 1110 0000 0000 0000 0000 1011 0000 0111 1001 0110 0000 0000 1111 1000 0000 0100 1010 1110 0000 0000 0000 0000 0000 0000 32-Bit Write Command 0x85E0000B 0x8A079600 0x81F804AE 0x40000000 Data 0000 0000 0010 0000 1001 1001 0000 0000 0000 0000 0000 0000 32-Bit Write Command 0x83002099 0x40000000 Data 0000 0000 0000 0000 0001 0101 0000 0000 0000 0000 0000 0000 32-Bit Write Command 0x82000015 0x40000000 Table 55. Example 2: Enable Respiration and Stream Conversion Data Write Command Write 1 Write 2 Register Addressed RESPCTL FRAMES Read/Write Bit 1 0 Register Address 000 0011 100 0000 Table 56. Example 3: Enable DC Lead-Off and Stream Conversion Data Write Command Write 1 Write 2 Register addressed LOFFCTL FRAMES Read/Write Bit 1 0 Register Address 000 0010 100 0000 Rev. A | Page 72 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Example 5: Enable Pace Detection and Stream Conversion Data 1. 1. 2. 3. 4. 5. 6. 7. Write 1 configures the CMREFCTL register to VCM_REF = 1.3 V (no electrodes contribute to VCM). RLD is enabled to RLD_OUT, and the shield amplifier enabled. Write 2 addresses the TESTTONE register to enable the 150 Hz sine wave onto all electrode channels. Write 3 addresses the FILTCTL register to change the internal low-pass filter to 250 Hz to ensure that the 150 Hz sine wave can pass through. Write 4 configures the FRMCTL register to output nine words per frame/packet. The frame/packet of words consists of the header and five ECG words, pace, respiration magnitude, and lead-off. The frame is configured to always send, irrespective of ready status. The ADAS1000 is in electrode format mode with a data rate of 2 kHz. Electrode format is required to see the test tone signal correctly on each electrode channel. Write 5 addresses the ECGCTL register, enabling all channels into a gain of 1.4, low noise mode. It configures the device as a master and driven from the XTAL input source. The ADAS1000 is also put into conversion mode in this write. Write 6 issues the read command to start putting the converted data out on the SDO pin. Continue to issue SCLK cycles to read the converted data at the configured packet data rate. 2. 3. 4. 5. Write 1 configures the PACECTL register with all three pace detection instances enabled, PACE1EN detecting on Lead II, PACE2EN detecting on Lead I, and PACE3EN detecting on Lead aVF. The pace width filter and validation filters are also enabled. Write 2 issues the read command to start putting the converted data out on the SDO pin. Continue to issue SCLK cycles to read the converted data at the configured packet data rate. When a valid pace is detected, the detection flags are confirmed in the header word and the PACEDATA register contains information on the width and height of the measured pulse from each measured lead. Note that the PACEAMPTH register default setting is 0x242424, setting the amplitude of each of the pace instances to 1.98 mV/gain. Note that this example assumes that the FRMCTL register has already been configured such that the PACEDATA word is available in the data frame, as arranged in Write 2 of Example 1. Table 57. Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Write Command Write 1 Write 2 Write 3 Write 4 Write 5 Write 6 Register Addressed CMREFCTL TESTTONE FILTCTL FRMCTL ECGCTL FRAMES Read/Write Bit 1 1 1 1 1 0 Register Address 000 0101 000 1000 000 1011 000 1010 000 0001 100 0000 Data 0000 0000 0000 0000 0000 1011 1111 1000 0000 0000 0000 1101 0000 0000 0000 0000 0000 1000 0000 0111 1001 0110 0001 0000 1111 1000 0000 0000 1010 1110 0000 0000 0000 0000 0000 0000 32-Bit Write Command 0x8500000B 0x88F8000D 0x8B000008 0x8A079610 0x81F800AE 0x40000000 Data 0000 0000 0000 1111 1000 1111 0000 0000 0000 0000 0000 0000 32-Bit Write Command 0x84000F8F 0x40000000 Table 58. Example 5: Enable Pace Detection and Stream Conversion Data Write Command Write 1 Write 2 Register Addressed PACECTL FRAMES Read/Write Bit 1 0 Register Address 000 0100 100 0000 Rev. A | Page 73 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet Example 6: Writing to Master and Slave Devices and Streaming Conversion Data Master Configuration Slave Configuration 1. Write 4 configures the FRMCTL register to output nine 1. Write 1 configures the FRMCTL register to output seven words per frame/packet (note that this differs from the words per frame/packet. The frame/packet of words consist number of words in a frame available from the slave of the header, five ECG words, and lead-off. The frame is device). The frame/packet of words consists of the header, configured to always send, irrespective of ready status The five ECG words, pace, respiration magnitude, and lead-off. slave ADAS1000-2 is in electrode mode format with a data In this example, the frame is configured to always send rate of 2 kHz. irrespective of ready status. The master, ADAS1000, is in 2. Write 2 configures the CMREFCTL register to receive an vector mode format with a data rate of 2 kHz. Similar external common mode from the master. to the slave device, the master could be configured for 3. Write 3 addresses the ECGCTL register, enabling all electrode mode; the host controller would then be required channels into a gain of 1.4, low noise mode. It configures to make the lead calculations. the device as a slave, in gang mode and driven from the 2. Write 5 configures the CMREFCTL register for CM = CLK_IN input source (derived from master ADAS1000). WCT = (LA + LL + RA)/3; RLD is enabled onto The ADAS1000-2 slave is also put into conversion mode RLD_OUT electrode. The shield amplifier is enabled. in this write, but waits for the SYNC_GANG signal from The CM = WCT signal is driven out of the master device the master device before it starts converting. (CM_OUT) into the slave device (CM_IN). 3. Write 6 addresses the ECGCTL register, enabling all channels into a gain of 1.4, low noise mode. It configures the device as a master in gang mode and driven from the XTAL input source. The ADAS1000 master is set to differential input, which places it in analog lead mode. This ECGCTL register write puts the master into conversion mode, where the device sends an edge on the SYNC_GANG pin to the slave device to trigger the simultaneous conversions of both devices. 4. Write 7 issues the read command to start putting the converted and decimated data out on the SDO pin. 5. Continue to issue SCLK cycles to read the converted data at the configured packet data rate. Table 59. Example 6: Writing to Master and Slave Devices and Streaming Conversion Data Device Slave Master Write Command Write 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write 7 Register Addressed FRMCTL CMREFCTL ECGCTL FRMCTL CMREFCTL ECGCTL FRAMES R/W 1 1 1 1 1 1 0 Register Address 000 1010 000 0101 000 0001 000 1010 000 0101 000 0001 100 0000 Rev. A | Page 74 of 80 Data 0000 0111 1111 0110 0001 0000 0000 0000 0000 0000 0000 0100 1111 1000 0000 0000 1101 1110 0000 0111 1001 0110 0000 0000 1110 0000 0000 0000 0000 1011 1111 1000 0000 0100 1011 1110 0000 0000 0000 0000 0000 0000 32-Bit Write Command 0x8A07F610 0x85000004 0x81F800DE 0x8A079600 0x85E0000B 0x81F804BE 0x40000000 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 SOFTWARE FLOWCHART Figure 81 shows a suggested sequence of steps to be taken to interface to multiple ADAS1000/ADAS1000-1/ADAS1000-2 devices. POWER UP ADAS1000 DEVICES WAIT FOR POR ROUTINE TO COMPLETE, 1.5ms INITIALIZE SLAVE DEVICES INITIALIZE MASTER DEVICE ENABLING CONVERSION ISSUE READ FRAME COMMAND (WRITE TO 0x40) NO DRDY LOW? YES ISSUE SCLK CYCLES (SDI = 0) TO CLOCK FRAME DATA OUT AT PROGRAMMED DATA RATE IS CRC CORRECT? NO DISCARD FRAME DATA YES NO ACTIVITY ON SDI? YES ADAS1000 STOPS CONVERTING, SDI WORD USED TO RECONFIGURE DEVICE RETURN TO ECG CAPTURE? NO YES ISSUE READ FRAME COMMAND (WRITE TO 0x40) NO POWER-DOWN? YES ADAS1000 GOES INTO POWER-DOWN MODE 09660-038 ECG CAPTURE COMPLETE POWER-DOWN ADAS1000 ECGCTL = 0x0 Figure 81. Suggested Software Flowchart for Interfacing to Multiple ADAS1000/ADAS1000-1/ADAS1000-2 Devices Rev. A | Page 75 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet POWER SUPPLY, GROUNDING, AND DECOUPLING STRATEGY The ADAS1000/ADAS1000-1/ADAS1000-2 should have ample supply decoupling of 0.01 μF on each supply pin located as close to the device pin as possible, ideally right up against the device. In addition, there should be one 4.7 μF capacitor for each of the power domains, AVDD and IOVDD, again located as close to the device as possible. IOVDD is best split from AVDD due to its noisy nature. Similarly, the ADCVDD and DVDD power domains each require one 2.2 μF capacitor with ESR in the range of 0.5 Ω to 2 Ω. The ideal location for each 2.2 μF capacitor is dependent on package type. For the LQFP package and DVDD decoupling, the 2.2 μF capacitor is best placed between Pin 30 and Pin 31, while for ADCVDD, the 2.2 μF capacitor should be placed between Pin 55 and Pin 56. Similarly for the LFCSP package, the DVDD 2.2 μF capacitor is ideal between Pin 43 and Pin 44, and between Pin 22 and Pin 23 for ADCVDD. A 0.01 μF capacitor is recommended for high frequency decoupling at each pin. The 0.01 μF capacitors should have low effective series resistance (ESR) and effective series inductance (ESL), such as the common ceramic capacitors that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Digital lines running under the device should be avoided because these couple noise onto the device. The analog ground plane should be allowed to run under the device to avoid noise coupling. The power supply lines should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. It is essential to minimize noise on VREF lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough throughout the board. As is the case for all thin packages, take care to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. During layout of board, ensure that bypass capacitors are placed as close to the relevant pin as possible, with short, wide traces ideally on the topside. ADCVDD AND DVDD SUPPLIES The AVDD supply rail powers the analog blocks in addition to the internal 1.8 V regulators for the ADC and the digital core. If using the internal regulators, connect the VREG_EN pin to AVDD and then use the ADCVDD and DVDD pins for decoupling purposes. The DVDD regulator can be used to drive other external digital circuitry as required; however the ADCVDD pin is purely provided for bypassing purposes and does not have available current for other components. Where overall power consumption must be minimized, using external 1.8 V supply rails for both ADCVDD and DVDD would provide a more efficient solution. The ADCVDD and DVDD inputs have been designed to be driven externally and the internal regulators may be disabled by tying VREG_EN pin directly to ground. UNUSED PINS/PATHS In applications where not all ECG paths or functions might be used, the preferred method of biasing the different functions is as follows: • • • • Unused ECG paths power up disabled. For low power operation, they should be kept disabled throughout operation. Ideally, these pins should be connected to RLD_OUT if not being used. Unused external respiration inputs can be tied to ground if not in use. If unused, the shield driver can be disabled and output left to float. CM_OUT, CAL_DAC_IO, DRDY, GPIOx, CLK_IO, SYNC_GANG can be left open. LAYOUT RECOMMENDATIONS To maximize CMRR performance, pay careful attention to the ECG path layout for each channel. All channels should be identical to minimize difference in capacitance across the paths. Place all decoupling as close to the ADAS1000/ADAS1000-1/ ADAS1000-2 devices as possible, with an emphasis on ensuring that the VREF decoupling be prioritized, with VREF decoupling on the same side as the ADAS1000/ADAS1000-1/ADAS1000-2 devices, where possible. AVDD While the ADAS1000/ADAS1000-1/ADAS1000-2 are designed to operate from a wide supply rail, 3.15 V to 5.5 V, the performance is similar over the full range, but overall power increases with increasing voltage. Rev. A | Page 76 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 0.42 0.24 0.60 0.42 0.24 0.275 43 PIN 1 INDICATOR 8.75 BSC SQ 6.05 5.95 SQ 5.85 *EXPOSED PAD 1 0.50 BSC 0.75 0.65 0.55 29 14 15 28 TOP VIEW BOTTOM VIEW 6.50 REF 0.70 MAX 0.65 NOM 12° MAX 0.05 MAX 0.01 NOM 0.30 0.23 0.18 0.20 REF 06-20-2012-A SEATING PLANE *FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 82. 56-Lead, Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-56-7) Dimensions shown in millimeters 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE VIEW A 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 83. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters Rev. A | Page 77 of 80 051706-A 0.90 0.85 0.80 0.150 56 42 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet ORDERING GUIDE Model 1 ADAS1000BSTZ ADAS1000BSTZ-RL ADAS1000BCPZ ADAS1000BCPZ-RL ADAS1000-1BCPZ ADAS1000-1BCPZ-RL ADAS1000-2BSTZ ADAS1000-2BSTZ-RL ADAS1000-2BCPZ ADAS1000-2BCPZ-RL EVAL-ADAS1000SDZ EVAL-SDP-CB1Z Description 5 ECG Channels, Pace Algorithm, Respiration Circuit 5 ECG Channels, Pace Algorithm, Respiration Circuit 5 ECG Channels, Pace Algorithm, Respiration Circuit 5 ECG Channels, Pace Algorithm, Respiration Circuit 5 ECG Channels 5 ECG Channels Companion for Gang Mode Companion for Gang Mode Companion for Gang Mode Companion for Gang Mode ADAS1000 Evaluation Board System Demonstration Board (SDP), used as a controller board for data transfer via USB interface to PC Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead LQFP 64-Lead LQFP 56-Lead LFCSP_VQ 56-Lead LFCSP_VQ 56-Lead LFCSP_VQ 56-Lead LFCSP_VQ 64-Lead LQFP 64-Lead LQFP 56-Lead LFCSP_VQ 56-Lead LFCSP_VQ Evaluation Kit 2 Controller Board 3 Package Option ST-64-2 ST-64-2 CP-56-7 CP-56-7 CP-56-7 CP-56-7 ST-64-2 ST-64-2 CP-56-7 CP-56-7 1 Z = RoHS Compliant Part. 2 This evaluation kit consists of ADAS1000BSTZ × 2 for up to 12-lead configuration. Because the ADAS1000 contains all features, it is the evaluation vehicle for all ADAS1000 variants. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator. Rev. A | Page 78 of 80 Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 NOTES Rev. A | Page 79 of 80 ADAS1000/ADAS1000-1/ADAS1000-2 Data Sheet NOTES ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09660-0-1/13(A) Rev. A | Page 80 of 80