ADC12L080 12-Bit, 80 MSPS, 450 MHz Bandwidth A/D Converter with Internal Reference General Description Features The ADC12L080 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 80 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. The ADC12L080 can be operated with either the internal or an external reference. Operating on a single 3.3V power supply, this device consumes just 425 mW at 80 MSPS, including the reference current. The Power Down feature reduces power consumption to just 50 mW. The differential inputs provide a full scale input swing equal to ± VREF. The buffered, high impedance, single-ended external reference input is converted on-chip to a differential reference for use by the processing circuitry. Output data format may be selected as either offset binary or two’s complement. This device is available in the 32-lead LQFP package and operates over the industrial temperature range of −40˚C to +85˚C. n n n n n n Single supply operation Low power consumption Power down mode Internal or external reference Selectable Offset Binary or 2’s Complement data format Pin-compatible with ADC12010, ADC12020, ADC12040, ADC12L063, ADC12L066 Key Specifications n n n n n Full Power Bandwidth DNL SNR (fIN = 10 MHz) SFDR (fIN = 10 MHz) Power Consumption, 80 MHz — Operating — Power Down 450 MHz ± 0.4 LSB (typ) 66 dB (typ) 80 dB (typ) 425 mW (typ) 50 mW (typ) Applications n n n n n n n n Ultrasound and Imaging Instrumentation Cellular Base Stations/Communication Receivers Sonar/Radar xDSL Wireless Local Loops Data Acquisition Systems DSP Front Ends Connection Diagram 20061001 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS200610 www.national.com ADC12L080 12-Bit, 80 MSPS, 450 MHz Bandwidth A/D Converter with Internal Reference October 2004 ADC12L080 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) Package ADC12L080CIVY 32 Pin LQFP ADC12L080EVAL Evaluation Board Block Diagram 20061002 www.national.com 2 ADC12L080 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 2 VIN+ 3 VIN− 1 VREF 31 VRP 32 VRM 30 VRN Differential analog signal Input pins. With a 1.0V reference voltage the full-scale differential input signal level is 2.0 VP-P with each input pin centered on a common mode voltage, VCM. The VIN- pin may be connected to VCM for single-ended operation, but a differential input signal is required for best performance. Reference input. This pin should be connected to VA to use the internal 1.0V reference. If it is desired to use an external reference voltage, this pin should be bypassed to AGND with a 0.1 µF low ESL capacitor. Specified operation is with a VREF of 1.0V, but the device will function well with a VREF range indicated in the Electrical Tables. These pins are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to AGND. Connect a 1.0 µF capacitor from VRP to VRN. DO NOT LOAD these pins. DIGITAL I/O CLK Digital clock input. The range of frequencies for this input is 10 MHz to 80 MHz with guaranteed performance at 80 MHz. The input is sampled on the rising edge of this input. 11 OF Output format selection. When this pin is LOW, the output format is offset binary. When this pin is HIGH the output format is two’s complement. This pin may be changed asynchronously, but such a change will result in errors for one or two conversions. 8 PD PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode. 10 3 www.national.com ADC12L080 Pin Descriptions and Equivalent Circuits Pin No. Symbol 14–19, 22–27 D0–D11 Equivalent Circuit (Continued) Description Digital data output pins that make up the 12-bit conversion results. D0 is the LSB, while D11 is the MSB of the output word. ANALOG POWER 5, 6, 29 VA 4, 7, 28 AGND Positive analog supply pins. These pins should be connected to a quiet +3.3V source and bypassed to AGND with 0.1 µF low ESL capacitors located within 1 cm of these power pins, and with a 10 µF capacitor. The ground return for the analog supply. DIGITAL POWER 13 VD 9, 12 DGND 21 20 www.national.com Positive digital supply pin. This pin should be connected to the same quiet +3.3V source as is VA and bypassed to DGND with a 0.1 µF monolithic capacitor in parallel with a 10 µF capacitor, both located within 1 cm of the power pin. The ground return for the digital supply. VDR Positive digital supply pin for the ADC12L080’s output drivers. This pin should be connected to a voltage source in the range indicated in the Operating Ratings table and be bypassed to DR GND with a 0.1 µF capacitor. If the supply for this pin is different from the supply used for VA and VD, it should also be bypassed with a 10 µF capacitor. The voltage at this pin should never exceed the voltage on VD by more than 300 mV. All bypass capacitors should be located within 1 cm of the supply pin. DR GND The ground return for the digital supply for the ADC12L080’s output drivers. This pin should be connected to the system digital ground, but not be connected in close proximity to the ADC12L080’s DGND or AGND pins. See Section 6.0 (Layout and Grounding) for more details. 4 Operating Ratings (Notes 1, 2) (Notes 1, 2) Operating Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA, VD) VA, VD, VDR ≤ 100 mV VDR–VD ≤ 300 mV Voltage on Any Pin +2.4V to VD VREF 0.8V to 1.5V CLK, PD, OF −0.05V to VD + 0.05V VIN Input −0V to (VA − 0.5V) VCM −0.3V to VA or (VD + 0.3V) 0.5V to (VA-1.5V) |AGND–DGND| 0V ± 25 mA ± 50 mA Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25˚C Package Thermal Resistances See (Note 4) ESD Susceptibility Human Body Model (Note 5) 2500V Machine Model (Note 5) Package θJ-A 32-Lead LQFP 79˚C / W 250V Soldering Temperature, Infrared, 10 sec. (Note 6) Storage Temperature +3.0V to +3.60V Output Driver Supply (VDR) 4.2V |VA–VD| −40˚C ≤ TA ≤ +85˚C 235˚C −65˚C to +150˚C Converter Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V external, VCM = 1.65V, RS < 100Ω, fCLK = 80 MHz, tr = tf = 2 ns, fIN = 70 MHz, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 10) Symbol Parameter Typical (Note 10) Conditions Limits (Note 10) Units (Limits) STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes INL DNL GE Integral Non Linearity Differential Non Linearity ± 1.2 Best Fit Method ± 0.4 No missing codes 12 Bits 4.0 LSB (max) -3.3 LSB (min) 1.5 LSB (max) -1.0 LSB (min) %FS (max) %FS (min) Positive Error −0.15 +5.7 -2 Negative Error +0.4 +5 -3.7 %FS (max) %FS (min) +0.2 +1.7 -0.6 %FS (max) Gain Error Offset Error (VIN+ = VIN−) Under Range Output Code 0 0 Over Range Output Code 4095 4095 REFERENCE AND ANALOG INPUT CHARACTERISTICS VCM Common Mode Input Voltage CIN VIN Input Capacitance (each pin to GND) VREF 1.65 VIN = 1.0 Vdc + 1 VP-P Reference Voltage (Note 12) (CLK LOW) 8 (CLK HIGH) 7 1.0 5 0.5 V (min) 2.0 V (max) pF pF 0.8 V (min) 1.5 V (max) www.national.com ADC12L080 Absolute Maximum Ratings ADC12L080 DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V external, VCM = 1.65V, RS < 100Ω, fCLK = 80 MHz, tr = tf = 2 ns, fIN = 70 MHz, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 10) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) DYNAMIC CONVERTER CHARACTERISTICS BW SNR SINAD ENOB THD 2nd Harm 3rd Harm SFDR IMD Full Power Bandwidth Signal-to-Noise Ratio Signal-to-Noise & Distortion Effective Number of Bits Total Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion -0.5 dBFS Input, Output at −3 dB 450 fIN = 10 MHz, Differential VIN = −0.5 dBFS 66 fIN = 40 MHz, Differential VIN = −0.5 dBFS 65 fIN = 70 MHz, Differential VIN = −0.5 dBFS 65 fIN = 150 MHz, Differential VIN = −0.5 dBFS 63 fIN = 10 MHz, Differential VIN = −0.5 dBFS 66 fIN = 40 MHz, Differential VIN = −0.5 dBFS 64.5 fIN = 70 MHz, Differential VIN = −0.5 dBFS 64 fIN = 150 MHz, Differential VIN = −0.5 dBFS 62 fIN = 10 MHz, Differential VIN = −0.5 dBFS 10.7 fIN = 40 MHz, Differential VIN = 0.5 dBFS 10.4 fIN = 70 MHz, Differential VIN = −0.5 dBFS 10.3 fIN = 150 MHz, Differential VIN = −0.5 dBFS 10.0 fIN = 10 MHz, Differential VIN = −0.5 dBFS −77 fIN = 40 MHz, Differential VIN = −0.5 dBFS -74 fIN = 70 MHz, Differential VIN = −0.5 dBFS -71 fIN = 150 MHz, Differential VIN = −0.5 dBFS -70 fIN = 10 MHz, Differential VIN = −0.5 dBFS −80 fIN = 40 MHz, Differential VIN = −0.5 dBFS -80 fIN = 70 MHz, Differential VIN = −0.5 dBFS -80 fIN = 150 MHz, Differential VIN = −0.5 dBFS -79 MHz 64 dB (min) 63 dB (min) 63 dB (min) 62.7 dB (min) 10.2 Bits (min) dB dB dB dB Bits 10.1 Bits (min) -66 dB (max) Bits dB -65 dB (max) -68 dB (max) -65.5 dB (max) dB dB dB fIN = 10 MHz, Differential VIN = −0.5 dBFS −84 fIN = 40 MHz, Differential VIN = −0.5 dBFS -81 -69 dB (max) fIN = 70 MHz, Differential VIN = −0.5 dBFS -79 -66 dB (max) fIN = 150 MHz, Differential VIN = −0.5 dBFS -78 fIN = 10 MHz, Differential VIN = −0.5 dBFS 80 fIN = 40 MHz, Differential VIN = −0.5 dBFS 77 fIN = 70 MHz, Differential VIN = −0.5 dBFS 74 fIN = 150 MHz, Differential VIN = −0.5 dBFS 73 dB fIN1 = 19.6MHz, fIN2 = 20.5 MHz, each = -6.0 dBFS 66 dBFS dB dB 68 dB (min) -65.5 dB (min) dB CLK, PD, OF DIGITAL INPUT CHARACTERISTICS VIN(1) Logical “1” Input Voltage VD = 3.3V 2.0 V (min) 0.8 V (max) VIN(0) Logical “0” Input Voltage VD = 3.3V IIN(1) Logical “1” Input Current VIN+, VIN− = 3.3V 10 µA IIN(0) Logical “0” Input Current VIN+, VIN− = 0V −10 µA CIN Digital Input Capacitance 5 pF D0–D11 DIGITAL OUTPUT CHARACTERISTICS VOUT(1) Logical “1” Output Voltage IOUT = −0.5 mA VDR − 0.18 V (min) VOUT(0) Logical “0” Output Voltage IOUT = 1.6 mA 0.4 V (max) +ISC Output Short Circuit Source Current VOUT = 0V −20 mA −ISC Output Short Circuit Sink Current VOUT = 2.5V 20 mA www.national.com 6 (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V external, VCM = 1.65V, RS < 100Ω, fCLK = 80 MHz, tr = tf = 2 ns, fIN = 70 MHz, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 10) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) POWER SUPPLY CHARACTERISTICS IA Analog Supply Current PD Pin = DGND PD Pin = VDR 120 10 168 mA (max) mA ID Digital Supply Current PD Pin = DGND PD Pin = VDR 6 5 11.5 mA (max) mA IDR Digital Output Supply Current PD Pin = DGND, fin = 0, (Note 13) PD Pin = VDR <1 Total Power Consumption PD Pin = DGND, CL = 0 pF (Note 14) PD Pin = VDR 425 50 Rejection of Full-Scale Gain Error change with VA = 3.0V vs. 3.6V 41 PSRR1 Power Supply Rejection Ratio mA mA 0 590 mW (max) mW dB AC Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0V, VREF = +1.0V external, VCM = 1.65V, RS < 100Ω, fCLK = 80 MHz, tr = tf = 2 ns, fIN = 70 MHz, CL = 15 pF/pin. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 10, 11) Symbol Parameter Conditions Typical (Note 10) Maximum Clock Frequency Limits (Note 10) Units (Limits) 80 MHz (min) Minimum Clock Frequency 10 MHz Clock Duty Cycle 60 40 % (max) % (min) tCH Clock High Time 5.5 ns (min) tCL Clock Low Time 5.5 ns (min) tCONV Conversion Latency tOD Data Output Delay after Rising CLK Edge tAD Aperture Delay 2 ns tAJ Aperture Jitter 0.7 ps rms tPD Power Down Mode Exit Cycle 1 µs 6 Clock Cycles VDR = 2.5V 5.2 8.3 ns (max) VDR = 3.3V 4.8 7.5 ns (max) 0.1 µF on pins 30, 31, 32, and 1.0 µF from pin 30 to 31 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA, VD or VDR), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above 183˚C is allowed per reflow cycle. Note 7: The inputs are protected as shown below. Input voltages above VA or below GND will not damage this device, provided current is limited per (Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 3.3V, the full-scale input voltage must be ≤3.4V to ensure accurate conversions. 7 www.national.com ADC12L080 DC and Logic Electrical Characteristics ADC12L080 AC Electrical Characteristics (Continued) 20061007 Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. Note 9: With the test condition for VREF = +1.0V (2 VP-P differential input), the 12-bit LSB is 488 µV. Note 10: Typical figures are at TA = TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 11: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. Note 12: Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ or the LM4051CIM3-1.2 band gap voltage reference is recommended for this application. Note 13: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling. Note 14: Power consumption excludes output driver power. See (Note 13). www.national.com 8 APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power supply voltage. PSRR1 is the ratio of the change in FullScale Gain Error that results from a change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding upon the power supply is rejected at the output. CONVERSION LATENCY See PIPELINE DELAY. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as: Gain Error = Positive Full Scale Error − Offset Error INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight line. The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS. MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12L080 is guaranteed not to have any missing codes. NEGATIVE FULL SCALE ERROR is the difference between the input voltage (VIN+ − VIN−) just causing a transition from negative full scale to the first code and its ideal value of 0/5 LSB. OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10 0000 0000/ OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins. PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data is pre- where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power in the first 9 harmonic frequencies. Second Harmonic Distortion (2nd Harm) is the difference expressed in dB, between the RMS power in the input frequency at the output and the power in its 2nd harmonic level at the output. Third Harmonic Distortion (3rd Harm) is the difference, expressed in dB, between the RMS power in the input frequency at the output and the power in its 3rd harmonic level at the output. 9 www.national.com ADC12L080 sented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the conversion by the pipeline delay. POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of 11⁄2 LSB below positive full scale. Specification Definitions ADC12L080 Timing Diagram 20061009 Output Timing Transfer Characteristic 20061010 FIGURE 1. Transfer Characteristic www.national.com 10 ADC12L080 Typical Performance Characteristics DNL, INL VA = VD = 3.3V, VDR = 2.5V, VREF = 1.0V external, VCM = 1.65V, fCLK = 80 MHz, fIN = 0, unless otherwise stated. DNL INL 20061041 20061045 DNL vs. fCLK INL vs. fCLK 20061042 20061046 DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle 20061043 20061047 11 www.national.com ADC12L080 Typical Performance Characteristics DNL, INL VA = VD = 3.3V, VDR = 2.5V, VREF = 1.0V external, VCM = 1.65V, fCLK = 80 MHz, fIN = 0, unless otherwise stated. (Continued) DNL vs. Temperature INL vs. Temperature 20061044 20061048 DNL vs. VDR INL vs. VDR 20061070 www.national.com 20061071 12 ADC12L080 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, VREF = 1.0V external, VCM = 1.65V, fCLK = 80 MHz, fIN = 70 MHz, unless otherwise stated. Distortion vs. VA SNR,SINAD,SFDR vs. VA 20061049 20061056 SNR,SINAD,SFDR vs. VDR Distortion vs. VDR 20061050 20061057 SNR,SINAD,SFDR vs. VCM Distortion vs. VCM 20061051 20061058 13 www.national.com ADC12L080 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, VREF = 1.0V external, VCM = 1.65V, fCLK = 80 MHz, fIN = 70 MHz, unless otherwise stated. (Continued) SNR,SINAD,SFDR vs. fCLK Distortion vs. fCLK 20061052 20061059 SNR,SINAD,SFDR vs. Clock Duty Cycle Distortion vs. Clock Duty Cycle 20061053 20061060 SNR,SINAD,SFDR vs. VREF Distortion vs. VREF 20061054 www.national.com 20061061 14 ADC12L080 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, VREF = 1.0V external, VCM = 1.65V, fCLK = 80 MHz, fIN = 70 MHz, unless otherwise stated. (Continued) SNR,SINAD,SFDR vs. fIN Distortion vs. fIN 20061072 20061073 SNR,SINAD,SFDR vs. Temperature Distortion vs. Temperature 20061055 20061062 Spectral Response @ 10 MHz Input tOD vs. VDR 20061063 20061064 15 www.national.com ADC12L080 Typical Performance Characteristics VA = VD = 3.3V, VDR = 2.5V, VREF = 1.0V external, VCM = 1.65V, fCLK = 80 MHz, fIN = 70 MHz, unless otherwise stated. (Continued) Spectral Response @ 40 MHz Input Spectral Response @ 70 MHz Input 20061065 20061066 Intermodulation Distortion, fIN1= 19.6 MHz, fIN2 = 20.5 MHz Spectral Response @ 150 MHz Input 20061068 www.national.com 20061069 16 Operating on a single +3.3V supply, the ADC12L080 uses a pipeline architecture with error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 12 bits. Each analog input signal should have a peak-to-peak voltage equal to the input reference voltage, VREF, be centered around VREF and be 180˚ out of phase with each other. Table 1 and Table 2 indicate the input to output relationship of the ADC12L080. Although a differential input signal is required for rated operation, single-ended operation is possible with reduced performance if one input is biased to VREF and the other input is driven. If the driven input is presented with its full range signal, there will be a 6 dB reduction of the output range, limiting it to the range of 1⁄4 to 3⁄4 of the minimum output range obtainable if both inputs were driven with complimentary signals. Section 2.2 explains how to avoid this signal reduction. An input voltage below 2.0V at pin 1 (VREF) is interpreted to be an external reference and is used as such. Connecting this pin to the analog supply (VA) will force the use of the internal 1.0V reference. It is very important that all grounds associated with the reference voltage and the input signal make connection to the analog ground plane at a single, quiet point to minimize the effects of noise currents in the ground path. The reference input pin serves two functions. When the input at this pin at or below 2V, this voltage is accepted as the reference for the converter. When this voltage is connected to VA, then internal 1.0V reference is used. Functionality is undefined with voltages at this pin between 2V and VA. The three Reference Bypass Pins (VRP, VRM and VRN) are made available for bypass purposes only. These pins should each be bypassed to ground with a 0.1 µF capacitor, and a 1.0 µF should be connected from VRP to VRN. Higher capacitances will result in a longer power down exit cycle. Lower capacitances may result in degraded dynamic performance. DO NOT LOAD these pins. TABLE 1. Input to Output Relationship — Differential Input VIN+ VIN− Output VCM − VREF VCM + VREF 0000 0000 0000 VCM −0.5 * VREF VCM +0.5 * VREF 0100 0000 0000 VCM VCM 1000 0000 0000 VCM +0.5 * VREF VCM −0.5 * VREF 1100 0000 0000 VCM + VREF VCM − VREF 1111 1111 1111 2.2 Signal Inputs The signal inputs are VIN+ and VIN−. The input signal, VIN, is defined as VIN = (VIN+) – (VIN−) Figure 2 shows the expected input signal range. Note that the nominal input common mode voltage, VCM, is VA/2 and the nominal input signals each run between the limits of AGND and VREF. The Peaks of the input signals should never exceed the voltage described as Peak Input Voltage = VA − 0.5V to maintain dynamic performance. TABLE 2. Input to Output Relationship — Single-Ended Input VIN+ VIN− Output VCM − 2 * VREF VCM 0000 0000 0000 VCM − VREF VCM 0100 0000 0000 VCM VCM 1000 0000 0000 VCM + VREF VCM 1100 0000 0000 VCM + 2 * VREF VCM 1111 1111 1111 The output word rate is the same as the clock frequency, which may be in within the range indicated in the Electrical Tables. The analog input voltage is acquired at the rising edge of the clock and the digital data for that sample is delayed by the pipeline for 6 clock cycles. A logic high on the power down (PD) pin reduces the converter power consumption to 50 mW. Applications Information 20061011 1.0 OPERATING CONDITIONS We recommend that the conditions in the Operating Table be observed for operation of the ADC12L080. FIGURE 2. Expected Input Signal Range The ADC12L080 performs best with a differential input, each of which should be centered around a common mode voltage, VCM. The peak-to-peak voltage swing at both VIN+ and VIN− should not exceed the value of the reference voltage or the output data will be clipped. The two input signals should be exactly 180˚ out of phase from each other and of the same amplitude. For single frequency inputs, angular errors result in a reduction of the effective full scale input. For a complex waveform, however, angular errors will result in distortion. 2.0 ANALOG INPUTS The ADC12L080 has two analog signal inputs, VIN+ and VIN−, which form a differential input pair. There is one reference input pin, VREF. 2.1 Reference Pins The ADC12L080 can be used with the internal 1.0V reference or with an external reference. While designed and specified to operate with a 1.0V reference, the ADC12L080 17 www.national.com ADC12L080 performs well with reference voltages in the range of indicated in the Operating Ratings table. Lower reference voltages will decrease the signal-to-noise ratio (SNR) of the ADC12L080. Higher reference voltages (and input signal swing) will degrade THD performance for a full-scale input. Functional Description ADC12L080 Applications Information TABLE 3. Resistor values for Circuit of Figure 5 (Continued) The full scale error in LSB for a sine wave input can be described as approximately SIGNAL RANGE EFS = 4096 ( 1 - sin (90˚ + dev)) 0 - 0.25V 0Ω open 200Ω 1780Ω 1000Ω Where dev is the angular difference between the two signals having a 180˚ relative phase relationship to each other (see Figure 3). Drive the analog inputs with a source impedance less than 100Ω. 0 - 0.5V 0Ω open 249Ω 1400Ω 499Ω ± 0.5V 100Ω 1210Ω 100Ω 1210Ω 499Ω R1 R2 R3 R4 R5, R6 3.0 DIGITAL INPUTS Digital inputs consist of CLK, OF and PD. All digital inputs are 3V CMOS compatible. 3.1 CLK The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock signal in the range indicated in the Electrical Table with rise and fall times of less than 2 ns. The trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog or digital, not even at 90˚. 20061012 FIGURE 3. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the minimum sample rate. For differential operation, each analog input signal should have a peak-to-peak voltage equal to the input reference voltage, VREF, and be centered around VCM. For singleended operation (which will result in reduced performance), one of the analog inputs should be connected to the d.c. common mode voltage of the driven input. The peak-to-peak differential input signal should be twice the reference voltage to maximize SNR and SINAD performance (Figure 2b). For example, set VREF to 1.0V, bias VIN− to 1.0V and drive VIN+ with a signal range of 0V to 2.0V. The duty cycle of the clock signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the ADC12L080 is designed to maintain performance over a range of duty cycles. While it is specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a clock duty cycle range indicated in the Electrical Table. The clock line should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 for information on setting characteristic impedance. It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is used to drive other things, each driven pin should be a.c. terminated with a series RC to ground, as shown in Figure 4, such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is Because very large input signal swings can degrade distortion performance, better performance with a single-ended input can be obtained by reducing the reference voltage while maintaining a full-range output. Table 1 and Table 2 indicate the input to output relationship of the ADC12L080. The VIN+ and the VIN− inputs of the ADC12L080 consist of an analog switch followed by a switched-capacitor amplifier. The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving source tries to compensate for this, it adds noise to the signal. To minimize this, use 33Ω series resistors at each of the signal inputs with a 51 pF capacitor to ground, as can be seen in Figure 5 and Figure 6. These components should be placed close to the ADC because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input. The 51 pF capacitor value is for Nyquist applications and should be replaced with a smaller capacitor for undersampling applications. The resulting pole should be at 1.7 to 2.0 times the highest input frequency. When determining this capacitor value, take into consideration the 8 pF ADC input capacitance. Table 3 gives component values for Figure 5 to convert a signals to a range 1.0V ± 0.5V at each of the differential input pins of the ADC12L080. www.national.com where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and tPD should be the same (inches or centimeters). 3.2 OF The OF pin is used to determine the digital data output format. When this pin is high, the output formant is two’s complement. When this pin is low the output format is offset binary. Changing this pin while the device is operating will result in uncertainty of the data for a few conversion cycles. 18 conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can cause on-chip noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 15 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic performance. To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by connecting buffers between the ADC outputs and any other circuitry (74ACQ541, for example). Only one driven input should be connected to each output pin. Additionally, inserting series 100Ω resistors at the digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4. While the ADC12L080 will operate with VDR voltages down to 1.8V, tOD increases with reduced VDR. Be careful of external timing when using reduced VDR. (Continued) 3.3 PD The PD pin, when high, holds the ADC12L080 in a powerdown mode to conserve power when the converter is not being used. The power consumption in this state is 50 mW and is not affected by the clock frequency, or by whether there is a clock signal present. The output data pins are undefined and the data in the pipeline is corrupted while in the power down mode. The Power Down Mode Exit Cycle time is determined by the value of the capacitors on pins 30, 31 and 32. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before conversions can be accurate. See Section 2.1 4.0 OUTPUTS The ADC12L080 has 12 TTL/CMOS compatible Data Output pins. The output data is present at these outputs while the PD pin is low. While the tOD time provides information about output timing, a simple way to capture a valid output is to latch the data on the rising edge of the conversion clock (pin 10). Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each 20061013 FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer 19 www.national.com ADC12L080 Applications Information ADC12L080 Applications Information (Continued) 20061014 FIGURE 5. Differential Drive Circuit of Figure 4 20061015 FIGURE 6. Driving the Signal Inputs with a Transformer www.national.com 20 nificant impact upon system noise performance. The best logic family to use in systems with A/D converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. (Continued) 5.0 POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF low ESL ceramic chip capacitor within 3 millimeters of each power pin. As is the case with all high-speed converters, the ADC12L080 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept below 100 mVP-P. The effects of the noise generated from the ADC output switching can be minimized through the use of 100Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible. No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be especially careful of this during turn on and turn off of power. The VDR pin provides power for the output drivers and may be operated from a supply in the range of 1.8V to VD. This can simplify interfacing to devices and systems operating with supplies less than VD. DO NOT operate the VDR pin at a voltage higher than VD. Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ground plane volume. Generally, analog and digital lines should cross each other at 90˚ to avoid crosstalk. To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the generally accepted 90˚ crossing should be avoided with the clock line as even a little coupling can cause problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to degradation of SNR. Also, the high speed clock can introduce noise into the analog chain. 6.0 LAYOUT AND GROUNDING Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate analog and digital areas of the board, with the ADC12L080 between these areas, is required to achieve specified performance. The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output current can exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the ADC12L080’s other ground pins. Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the clock line as short as possible. Digital circuits create substantial supply and ground current transients. The logic noise thus generated could have sig- Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the signal path through all components should form a straight line wherever possible. Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies beside each other. 20061016 FIGURE 7. Example of a Suitable Layout The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected be- 21 www.national.com ADC12L080 Applications Information ADC12L080 Applications Information cause faulty or erratic operation. It is not uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot that goes above the power supply or below ground. A resistor of about 50Ω to 100Ω in series with any offending digital input, close to the signal source, will eliminate the problem. Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or power down. (Continued) tween the converter’s input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane. Figure 7 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of the board. All digital circuitry and I/O lines should be placed in the digital area of the board. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the ground plane at a single point. All ground connections should have a low inductance path to ground. Best performance will be obtained with a single ground plane and separate analog and digital power planes. The power planes define analog and digital board areas of the board. Analog and digital components and signal lines should be kept within their own areas. Be careful not to overdrive the inputs of the ADC12L080 with a device that is powered from supplies outside the range of the ADC12L080 supply. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate bypassing and maintaining separate analog and digital areas on the PC board will reduce this problem. Additionally, bus capacitance beyond the specified 15 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance. The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be improved by adding series resistors at each digital output, close to the ADC12L080, which reduces the energy coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors is 100Ω. Using an inadequate amplifier to drive the analog input. As explained in Section 2.2, the sampling input is difficult to drive without degrading dynamic performance. 7.0 DYNAMIC PERFORMANCE To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. The maximum allowable jitter to avoid the addition of noise to the conversion process is Max Jitter = 1 / (2n+1 x π x fIN) Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 8. To avoid adding jitter to the clock signal, the elements of Figure 8 should be capable of toggling at a up to ten times the frequency used. As mentioned in Section 6.0, it is good practice to keep the ADC clock line as short as possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90˚ crossings have capacitive coupling, so try to avoid even these 90˚ crossings of the clock line. If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a capacitor at each of the ADC analog inputs to ground (as shown in Figure 5 and Figure 6) will improve performance. The LMH6702, LMH6628, LMH6622 and LMH6655 have been successfully used to drive the analog inputs of the ADC12L080. Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180o out of phase with each other. Board layout, including equality of the length of the two traces to the input pins, will affect the effective phase between these two signals. Remember that an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same device operating in the inverting configuration. Operating with the reference pins outside of the specified range. As mentioned in Section 2.1, VREF should be in the range specified in the Operating Ratings table. Operating outside of these limits could lead to performance degradation. Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR and SINAD performance. 20061017 FIGURE 8. Isolating the ADC Clock from other Circuitry with a Clock Tree 8.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above the supply pins). Exceeding these limits on even a transient basis may www.national.com 22 inches (millimeters) unless otherwise noted 32-Lead LQFP Package Ordering Number ADC12L080CIVY NS Package Number VBE32A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 ADC12L080 12-Bit, 80 MSPS, 450 MHz Bandwidth A/D Converter with Internal Reference Physical Dimensions