ADM8211 IEEE802.11b WLAN NIC Solution PCI/miniPCI/Cardbus Interface with MAC Unit + Baseband Processor (BBP) DATASHEET Rev. 1.1 Feb, 2003 Information in this document is provided in connection with ADMtek products. ADMtek may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." ADMtek reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The products may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. 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ADMtek Partnership Now & Future 1 REVISION HISTORY Revision Date Revision Description Mar, 2002 0.1 Draft Apr, 2002 0.3 Preliminary version Apr, 2002 0.4 Change EEPROM format Rename GPIO0 May, 2002 0.5 Rename EEPROM [54:60] as Tx Power May, 2002 0.6 Add missed pins in Pin Description, C1, C2, D1, D2 Oct, 2002 0.7 Remove unnecessary chapters Update EEPROM format Nov, 2002 0.8 Remove PWRLEDACT Remove GPIO2 Feb, 2003 1.0 Formal release Mar, 2003 1.1 Correct Chapter 6, Electrical Specifications ADMtek Partnership Now & Future 2 Content 1 GENERAL DESCRIPTION .................................................................5 2 FEATURES ............................................................................................6 2.1 HOST PCI INTERFACE .....................................................................................................................6 2.2 INDUSTRY STANDARD ......................................................................................................................6 2.3 802.11 MAC ....................................................................................................................................6 2.4 WEP ................................................................................................................................................6 2.5 WLAN TX/RX FIFO .....................................................................................................................7 2.6 WLAN SYNTHESIZER INTERFACE .................................................................................................7 2.7 EEPROM INTERFACE ....................................................................................................................7 2.8 LED DISPLAY ..................................................................................................................................7 2.9 MISCELLANEOUS.............................................................................................................................7 3 APPLICATION DIAGRAM.................................................................8 4 PIN ASSIGNMENT DIAGRAM..........................................................9 5 PIN DESCRIPTION............................................................................10 5.1 PCI INTERFACE.............................................................................................................................10 5.2 EEPROM INTERFACE .................................................................................................................. 11 5.3 SERIAL INTERFACE TO SYNTHESIZER ..........................................................................................12 5.4 RF I/F ............................................................................................................................................12 5.5 LED DISPLAY, GPIO.....................................................................................................................12 5.6 MISCELLANEOUS...........................................................................................................................13 5.7 ON CHIP REGULATOR PINS ............................................................................................................13 5.8 DIGITAL POWER PINS ...................................................................................................................13 5.9 ANALOG POWER PINS ...................................................................................................................13 ADMtek Partnership Now & Future 3 5.10 6 CLOCK PINS ..................................................................................................................................13 ELECTRICAL SPECIFICATIONS AND TIMINGS ......................14 6.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................................14 6.2 OPERATING CONDITION................................................................................................................14 6.3 DC SPECIFICATIONS .....................................................................................................................14 6.4 EEPROM INTERFACE DC SPECIFICATION..................................................................................14 6.5 GPIO INTERFACE DC SPECIFICATION ........................................................................................15 6.6 RESET TIMING...............................................................................................................................15 6.7 EEPROM INTERFACE TIMING SPECIFICATION ..........................................................................15 7 PACKAGE............................................................................................17 ADMtek Partnership Now & Future 4 1 General Description ADM8211 is a high performance PCI/miniPCI/Cardbus single chip with WLAN MAC controller and Baseband processor integrated. ADMtek is the leading of networking SOC, based on mature experience, ADM8211 is designed as hardwired architecture to reach the cost effective target. With the features of SRAM-needless, power saving, WEP/fix, small-package…etc. ADM8211 is versatile for WLAN system manufacturers to develop IEEE 802.11b wireless product. Tx Buffer Management Tx FIFO Tx MAC Arbiter WLAN CSR WEP Engine Preamble/Header Rx MAC Rx FIFO DAC Demodulator ADC Synthesizer, RF I/F PCI/IF Control Rx Buffer Management Modulator Magic Pkt / Wake-up Frame WLAN CR EEPROM I/F ADMtek Partnership Now & Future LED/GPIO Clock Gen 5 2 Features 2.1 Host PCI interface Provides 32-bit PCI bus master data transfer Supports network operation with PCI system clock from 22 MHz to 33MHz Provides performance meter, PCI bus master latency timer, for tuning the threshold to enhance the performance Provides burst-transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization. Supports memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-invalidate command while being bus master Supports big or little endian byte ordering Arbitration between DMA channel to minimize underflow or overflow 2.2 Industry standard PCI 2.2 /Cardbus interface ACPI and PCI power management 1.1 standard compliant IEEE802.11, IEEE802.11b 2.3 802.11 MAC MAC implements with State Machine No External SRAM needed Support auto-fallback from 11Mbps to 5.5, 2 and 1Mbps. Support Infrastructure, Ad-hoc under Distributed Coordination Function (DCF) Implementation the Point Coordination Function (PCF) operation RTS/CTS generation, Fragmentation, Beacon monitor/loss detection/generation. RX DA address filtering (multicast) with 64 entries. TIM (Traffic Indication Map) field decoding at Beacon frame reception Support DSSS (Direct Sequence Spread Spectrum) PHY. Front end chip power sequence control 2.4 WEP Internal encryption engine for WEP function, RC4, 40/104 bits key length selectable. ADMtek Partnership Now & Future 6 Randomly generated IV (Initialization Vector) for TX. ICV (Integrity Check Value) generation and check. 4 default shared key supported. TA/RA WEP individual key management with a 20-entry table. 2.5 WLAN TX/RX FIFO Provides two independent long FIFOs with 4k bytes each for transmission and receiving Bus master descriptor based host memory access Pre-fetch up to two transmit packets to guarantee standard inter frame space (IFS) Re-transmits no-ACKed packet without reloading from host memory. Support two TX descriptors for DCF and PCF application Automatically re-transmitting if TX under-run happened. 2.6 WLAN Synthesizer Interface Support RFMD compatible interface 2.7 EEPROM Interface Provides serial interface for read/write 93C46/93C66 EEPROM Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and Minimum-Grand from the 64 byte contents of 93C46/93C66 after PCI reset de-asserted in PCI environment. CIS data is recalled from 93C66 through ADM8211 in CARDBUS environment. 2.8 LED Display Power: Power on indication Link: Keep on while link Activity: Blinking at 10Hz while activity 2.9 Miscellaneous Low power application Support 3 GPIO pins CMOS .25um Process Provides 156/BGA package On chip 3.3V ~ 2.5V regulator 3.3V power supply with 5V/3.3V I/O tolerance ADMtek Partnership Now & Future 7 3 Application Diagram * Please refer to schematic provided by ADMtek PCI / miniPCI / Cardbus Interface EEPROM ADM8211 MAC+BBP Partnership Now & Future PA SAW 44M Hz Crystal ADMtek RF LEDs 8 4 Pin Assignment Diagram A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Bottom View 156-Pin BGA 1 A 2 3 4 5 6 VSS 7 8 9 10 11 12 13 PA_PE PE1 PE2 VD33 EECS EEDI LEDACT VD33 VD33 EECK EEDO B VDDA GNDA LE_IF# SYNDATA SYNCLK C Q_in I_in D Q_out I_out TXVGC LNA_GS E VREF ANTSEL F VDDA GNDA VD33 VSSPST GPIO1 INTA# VSS VSSPST VSENSE VD33 OSC44O CLK_44 VSSPST VSSPST OSC44I GPIO3 VSSPST BW_SEL VSSPST VSSPST VSA VCTL VDDAH VD33 VSSPST VAUX3.3 AD0 VD33 AD2 AD1 K GNT# VSSPST VSSPST RST# AD5 AD3 VSSPST VD33 L AD28 AD29 AD30 AD17 AD26 AD20 AD12 AD11 AD4 AD6 M VDD FRAME# VDD VDD AD27 VD33 VSSPST AD13 AD15 VSS AD8 C-BEB0 N AD24 C-BEB3 AD22 VDD C-BEB2 VSS AD18 SERR# PAR VSS AD14 AD7 IDSEL AD23 AD19 AD21 IRDY# VD33 C-BEB1 AD10 VSS H REQ# PCI-CLK J AD31 P PME#/ CSTSCHG VDD ADMtek Partnership Now & Future MCLK VSSPST LEDLINK G RXVGC 14 GNDD VDDD AD25 DEVSEL# AD16 AD9 PERR# STOP# VSS VD33 TRDY# VSSPST VSSPST PCI/CB VCC_DETECT CLKRUN 9 5 Pin Description 5.1 PCI Interface Pin Name G2 INTA# Type O/D Description K4 RST# I PCI reset signal, at least 100µs. During the reset period, all the output pins of ADM8211 will be set to tri-state and all the O/D pins are floated. H2 PCI-CLK I This PCI clock inputs to ADM8211. The bus signals are recognized on rising edge of PCI-CLK. The frequency range of PCI-CLK is limited between 20MHz and 33MHz. K1 GNT# I This signal indicates that the bus request of ADM8211 have been accepted. H1 REQ# O Bus master device request. J2 PME# / I/O CSTSCHG PCI interrupt acknowledge. The Power Management Event signal is an open drain, active low signal for PCI (PME#) When CSR18.bit19 is set into “1”, means that the ADM8211 is set into Power Save mode. In this mode, when the ADM8211 receives a Beacon (TIM) or ATIM frame from network then the ADM8211 will active this signal too. J1 AD31 L3 AD30 L2 AD29 L1 AD28 M5 AD27 L5 AD26 L7 AD25 N1 AD24 P3 AD23 N3 AD22 P5 AD21 L6 AD20 P4 AD19 N8 AD18 L4 AD17 L9 AD16 M11 AD15 N13 AD14 M8 AD13 L11 AD12 M12 AD11 P13 AD10 ADMtek Partnership Now & Future I/O Multiplexed address data pin of PCI Bus 10 L10 AD9 M13 AD8 N14 AD7 L14 AD6 K11 AD5 L13 AD4 K12 AD3 J11 AD2 J12 AD1 H14 AD0 N2 C-BEB3 N5 C-BEB2 P12 C-BEB1 M14 C-BEB0 P2 I/O Bus command and byte enable IDSEL I Initialization Device Select. This signal is asserted when host issues the configuration cycles to the ADM8211. M2 FRAME# I/O Begin and duration of bus access, driven by master device P6 IRDY# I/O Master device is ready to data transaction P7 TRDY# I/O Slave device is ready to data transaction L8 DEVSEL# I/O Device select, target is driving to indicate the address is decoded M10 STOP# I/O Target device request the master device to stop the current transaction M9 PERR# I/O Data parity error is detected, driven by the agent receiving data N8 SERR# O/D Address parity error N11 PAR I/O Parity, even parity (AD[31:0] + C/BE[3:0]), master drives par for address and write data phase, target drives par for read data phase J14 CLKRUN I/O Clock Run for PCI system. In the normal operation situation, Host should assert this signal to indicate ADM8211 about the normal situation. On the other hand, when Host will deassert this signal when the clock is going down to a nonoperating frequency. When ADM8211 recognizes the deasserted status of clk-run, then it will assert clk-run to request host to maintain the normal clock operation. When clk-run function is disabled then the ADM8211 will set clk-run in tri-state. O/D P10 PCI/CB I Bonding low to select CARD bus mode. Internal pull up. 5V-tolerant 5.2 EEPROM Interface Pin Name Type B11 EECK I/O Description ECK: Clock output to serial EEPROM. pull-up, 5V tolerant A12 EEDI I/O EDI: Data output to serial EEPROM. pull-up, 5V tolerant ADMtek Partnership Now & Future 11 B12 EEDO I/O EDO: Data input from serial EEPROM pull-up, 5V tolerant A11 EECS O Chip Select of serial EEPROM Pull-down, 5V tolerant 5.3 5.4 Serial Interface to Synthesizer Pin B5 Name LEIF# Type O, pull-up Description Synthesizer 2 Chip Select B7 SYNCLK O, pull-up Clock B6 SYNDATA O, pull-up Data RF I/F Pin 5.5 Name Type Description A8 PE1 O, pull-up Power enable 1 A9 PE2 O, pull-up Power enable 2 E12 BW_SEL O Channel 14 control pin A7 PA_PE O, pull-up Transmit PA Power Enable C1 Q_in I Analog Q input D1 Q_out O Analog Q output 1.6V-1.8V C2 I_in I Analog I input D2 I_out O Analog I output 1.6V-1.8V LED display, GPIO Pin Name Type Description LED Drive. C12 LEDLINK O, pull-up 10 Hz blinking while either of following 2 conditions effective, even at D3-Cold. (1) Association successful with AP (2) Beacon reception when join IBSS A13 F12 LEDACT O, pull-up GPIO1 I/O D14 GPIO3 I/O LED Drive. 10 Hz blinking while TX/RX Frame is detected General-purpose I/O pins, refer to GPIOEN setting (CSR11A). Pull-up, 5V tolerant General-purpose I/O pins, capable of event, rise/fall edge or toggle, capturing to generate interrupt to host, if enabled. Pull-up, 5V tolerant ADMtek Partnership Now & Future 12 5.6 Miscellaneous Pin Name H13 Vaux3.3 Type I, Schmmit 5V tolerant J13 VDD_detect I, Schmmit 5V tolerant 5.7 ACPI purpose, for detecting the auxiliary power source. When asserted, it indicates PCI power source is supported. ACPI purpose, for detecting the main power is remained or not, this pin should be connected to PCI bus power source +3.3V. On chip regulator Pins Pin 5.8 Description When asserted, it indicates an auxiliary power source is supported Name Type Description G13 REGCTL I/O Regulator control pin G12 VSA Power GND for regulator G14 VDDAH Power 3.3V for regulator G11 VSENSE I 2.5V sense input Digital Power Pins Pin 5.9 Name Description F4, H4, J4, M6, B9, A10, B10,H11, N10, P11, VDD33 J14 Power 3.3V for IO K2, K3, G4, M7, P8, P9, D11, E11, F11, D12, VSSPST H12, E13, K13, B14, E14 Power Gnd for IO G1, M1, J1, M3, M4, N4, M12, N12 VDD Power 2.5V for core A2, G3, N6, N9, VSS Power Gnd for core D8 VDDD Power Vcc for BBP (leave open) D7 GNDD Power Gnd for BBP Analog Power Pins Pin 5.10 Type Name Type Description B1, F2 VDDA Power 3.0V for BBP B2, F3 GNDA Power Analog Gnd for BBP Clock Pins Pin Name Type Description A13 OSC44I I 44 MHz clock input C13 OSC44O O 44 MHz clock output C14 CLK44 O, pull-up Buffered 44Mhz clock output This signal will be stopped, forced low, during MAC enter into power saving mode. ADMtek Partnership Now & Future 13 6 Electrical Specifications and Timings 6.1 Absolute Maximum Ratings Supply Voltage (VDD) DC Input Voltage (VIN) DC Output Voltage (VOUT) Storage Temperature Ambient Temperature ESD Rating 6.2 6.3 Operating Condition Symbol Parameter VDD Supply Voltage Condition Min Max Units 3.0 3.6 V DC Specifications Symbol Parameter 6.4 -0.3 V to 3.6 V -0.5 V to VDD+0.5V -0.5 V to VDD+0.5V -65 C to 150 C 0 C to 70 C 2000V Condition Min Max Vih Input High Voltage Vil Input Low Voltage Iih Differential Input Sensitivity 0.1 Vcm Differential Common Mode Range 0.8 2.5 V Voh Output High Voltage 2.8 3.6 V Vol Output Low Voltage 0.0 0.3 V Vcrs Output Voltage 0.8 2.5 V Min Max Units Signal 2.0 Units V 0.8 Crossover V V EEPROM Interface DC specification Standard Vcc (4.5V to 5.5V) DC Specification Symbol Parameter Condition Vih Input High Voltage 2.0 Vcc +1 V Vil Input Low Voltage -0.1 0.8 V Iih Input High Leakage Current 0<Vin < Vcc 1 µA Iil Input Low Leakage Current 0<Vin < Vcc -1 µA Vol Output Low Voltage IoH = -10 µA Voh Output High Voltage IoL = 10 µA Cin Input Pin Capacitance ADMtek Partnership Now & Future Vcc –0.2 V 0.2 V 5 pF 14 Low Vcc (2.7V to 5.5V) DC Specification Symbol Parameter 6.5 Min Max Units Vih Input High Voltage 0.8Vcc Vcc +1 V Vil Input Low Voltage -0.1 0.15Vcc V Iih Input High Leakage Current 0<Vin < Vcc 1 µA Iil Input Low Leakage Current 0<Vin < Vcc -1 µA Voh Output High Voltage IoH = -10 µA Vol Output Low Voltage IoL = 10 µA Cin Input Pin Capacitance 0.9Vcc V 0.1Vcc V 5 pF Max Units GPIO Interface DC Specification Symbol Parameter 6.6 Condition Condition Min Vih Input High Voltage 2.0 V Vil Input Low Voltage 0.8 V Iih Input High Leakage Current 0<Vin < Vcc 10 µA Iil Input Low Leakage Current 0<Vin < Vcc -10 µA Voh Output High Voltage IoH = -4 mA Vol Output Low Voltage IoL = 4 mA 2.4 V 0.4 V Reset Timing ADM8211 can be reset either by hardware, software or USB reset. A hardware reset is accomplished by asserting the RST# pin after power up the device. It should have a duration of at least 50 ms to ensure the external 48MHz crystal is in stable and correct frequency. All registers will be reset to default values. A software reset is accomplished by setting the reset bit. This software reset will reset all registers to default values. 6.7 EEPROM Interface Timing Specification Symbol Parameter Min Max Units tEESK EESK Clock Frequency 0 1 MHz TEECSS EECS Setup Time to EESK 0.2 µs TEECSH EECS Hold Time from EESK 0 ns TEEDOH EEDO Hold Time from EESK 70 ns TEEDOP EEDO Output Delay to “1” or “0” ADMtek Partnership Now & Future 2 µs 15 tEEDIS EEDI Setup Time to EESK 0.4 µs tEEDIH EEDI Hold Time from EESK 0.4 µs ADMtek Partnership Now & Future 16 7 Package Package: 156-pin BGA Dimension: 15mm*15mm*1.81mm ADMtek Partnership Now & Future 17