ASIX AX88178A

AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Document No: AX88179/V1.02/08/07/12
Features
Single chip USB 3.0 to 10/100/1000M Gigabit
Ethernet controller with Energy Efficient
Ethernet (EEE)
USB Device Controller
Integrates on-chip USB 3.0 PHY and
controller compliant to USB Spec 3.0, 2.0 and
1.1
Supports all USB 3.0 power saving modes (U0,
U1, U2, and U3)
Supports USB Super/High/Full Speed modes
with Bus-power or Self-power device
auto-detect capability
High performance packet transfer rate over
USB bus using proprietary burst transfer
mechanism (US Patent Approval)
Gigabit Ethernet Controller
Supports IEEE 802.3az (Energy Efficient
Ethernet)
IEEE 802.3, 802.3u, and 802.3ab compatible
Integrates
10/100/1000Mbps
Gigabit
Ethernet MAC/PHY
Supports dynamic cable length detection and
dynamic power adjustment Green Ethernet
(Gigabit mode only)
Supports parallel detection and automatic
polarity correction
Supports crossover detection and autocorrection
Supports IPv4/IPv6 packet Checksum
Offload Engine (COE) to reduce CPU
loading,
including
IPv4
IP/TCP/UDP/ICMP/IGMP
&
IPv6
TCP/UDP/ICMPv6 checksum check &
generation
Supports TCP Large Send Offload V1
Supports full duplex operation with IEEE
802.3x flow control and half duplex
operation with back-pressure flow control.
Supports IEEE 802.1P Layer 2 Priority
Encoding and Decoding
Supports IEEE 802.1Q VLAN tagging and
2 VLAN ID filtering; received VLAN Tag (4
bytes) can be stripped off or preserved
Supports Jumbo frame
PHY loop-back diagnostic capability
Support Wake-on-LAN Function
Supports suspend mode and remote wakeup
via link-change, Magic Packet, Microsoft
wakeup frame and external wakeup pin
Supports Bonjour wake-on-demand
Advanced Power Management Features
Supports power management offload (ARP &
NS)
Supports dynamic power management to
reduce power dissipation during idle or light
traffic
Supports AutoDetach power saving.
Soft-disconnected from USB host when
Ethernet cable is unplugged
Supports advanced link down power saving
during Ethernet cable is unplugged
Supports optional serial EEPROM (93c56/66)
for storing USB Descriptors, Node-ID, etc
Supports embedded eFuse (64-byte) to store
USB Device Descriptors, Node-ID, etc. to save
external EEPROM
Supports automatic loading of USB Device
Descriptors, Node-ID, etc. from embedded
eFuse or external EEPROM after power-on
initialization
Single 25MHz clock input from either crystal or
oscillator source
Integrates on-chip power-on reset circuit
68-pin QFN 8mm x 8mm RoHS/REACH
compliant package
Operating over 0°C to 70°C temperature range
Target Applications










USB Dongle
Docking Station
USB Port Replicator
Network Printer
POS, Card Reader
UMPC, MID, Netbook
Ultrabook
Game Console
IP STB, IP TV
Embedded system
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300
TEL: 886-3-579-9500
FAX: 886-3-579-9558
Released Date: 08/07/2012
http://www.asix.com.tw/
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Typical System Block Diagrams

Hosted by USB to operate with internal Ethernet PHY only
Figure 1
: USB 3.0 to LAN Adaptor
1
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
DISCLAIMER
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may make
changes to the product specifications and descriptions in this document at any time, without notice.
ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without
limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.
Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined” or
“NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a
design of ASIX products.
TRADEMARKS
ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the property of
their respective owners.
2
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Table of Contents
1
2
3
4
INTRODUCTION ....................................................................................................................................................... 7
1.1
GENERAL DESCRIPTION .......................................................................................................................................... 7
1.2
BLOCK DIAGRAM ................................................................................................................................................... 7
1.3
PINOUT DIAGRAM ................................................................................................................................................... 8
SIGNAL DESCRIPTION ........................................................................................................................................... 9
2.1
68-PIN PINOUT DESCRIPTION .................................................................................................................................. 9
2.2
HARDWARE SETTING FOR OPERATION MODE AND MULTI-FUNCTION PINS ......................................................... 11
FUNCTION DESCRIPTION ................................................................................................................................... 12
3.1
USB CORE AND INTERFACES ................................................................................................................................ 12
3.2
ENERGY EFFICIENT ETHERNET (EEE) .................................................................................................................. 12
3.3
10/100/1000M ETHERNET PHY ........................................................................................................................... 12
3.4
GMAC CORE ....................................................................................................................................................... 13
3.5
CHECKSUM OFFLOAD ENGINE (COE)................................................................................................................... 13
3.6
MEMORY ARBITER ............................................................................................................................................... 13
3.7
USB TO ETHERNET BRIDGE .................................................................................................................................. 14
3.8
EFUSE AND CONTROL ........................................................................................................................................... 14
3.9
SEEPROM LOADER INTERFACE .......................................................................................................................... 14
3.10
GENERAL PURPOSE I/O AND LED ........................................................................................................................ 14
3.11
PLL CLOCK GENERATOR ..................................................................................................................................... 15
3.12
RESET GENERATION ............................................................................................................................................. 16
SERIAL EEPROM/EFUSE MEMORY MAP ........................................................................................................ 17
4.1
4.1.1
Node ID (00~02h) ........................................................................................................................................ 19
4.1.2
Flag (EEPROM: 05h, eFuse:18h) ............................................................................................................... 19
4.1.3
Max. Power for Self/Bus Power (07h) ......................................................................................................... 20
4.1.4
EndPoint1 for SS/HS/FS (EEPROM:08h, eFuse: 06h) ................................................................................ 20
4.1.5
Max. Burst for EP3/EP2 (EEPROM: 3Ch, eFuse: 17h) .............................................................................. 20
4.1.6
LED Mode (EEPROM: 42h, eFuse: 19h~1Ah) ............................................................................................ 21
4.1.7
Fixed_pattern (EEPROM: 41~3Dh, eFuse: 1F~1Ah) ................................................................................. 22
4.2
5
DETAILED DESCRIPTION ....................................................................................................................................... 19
INTERNAL ROM DEFAULT SETTINGS ................................................................................................................... 23
4.2.1
Internal ROM Description ........................................................................................................................... 24
4.2.2
External EEPROM Description ................................................................................................................... 26
USB CONFIGURATION STRUCTURE ................................................................................................................ 27
3
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6
5.1
USB CONFIGURATION .......................................................................................................................................... 27
5.2
USB INTERFACE ................................................................................................................................................... 27
5.3
USB ENDPOINTS................................................................................................................................................... 27
USB COMMANDS .................................................................................................................................................... 28
6.1
USB STANDARD COMMANDS ............................................................................................................................... 28
6.2
USB VENDOR COMMANDS DESCRIPTION ............................................................................................................. 29
6.2.1
USB Vendor Command Format ................................................................................................................... 29
6.2.1.1
Read MAC Register (C001_AA00_CC00_EE00) ................................................................................... 29
6.2.1.2
Write MAC Register (4001_AA00_CC00_EE00) ................................................................................... 30
6.2.1.3
Read Wakeup Frame Register (C003_AA00_CC00_EE00) .................................................................. 30
6.2.1.4
Write Wakeup Frame Register (4003_AA00_CC00_EE00) .................................................................. 31
6.2.1.5
Read Non-Volatile Setting Register (C004_AA00_CC00_EE00) .......................................................... 31
6.2.1.6
Read eFuse Register (C005_AA00_CC00_EE00) .................................................................................. 32
6.2.1.7
Write eFuse Register (4005_ AA00_CC00_EE00) ................................................................................. 32
6.2.1.8
Reload EEPROM/eFuse Control Register (4006_0000_0000_0000) .................................................... 32
6.2.1.9
Read MFA Control Register (C010_0000_0000_0400) ......................................................................... 33
6.2.1.10
6.2.2
Write MFA Control Register (4010_AABB_CCDD_0000) ............................................................... 34
MAC Register Description ........................................................................................................................... 35
6.2.2.1
Physical Link Status Register (PLSR, 02h, Read only) ......................................................................... 35
6.2.2.2
EEPROM Address Register (EAR, 07h, R/W) ....................................................................................... 36
6.2.2.3
EEPROM Data Low Register (EDLR, 08h, R/W) ................................................................................. 36
6.2.2.4
EEPROM Data High Register (EDHR, 09h, R/W) ............................................................................... 36
6.2.2.5
EEPROM Command Register (ECR, 0Ah) ............................................................................................ 36
6.2.2.6
Rx Control Register (RCR, 0Bh~0Ch) ................................................................................................... 37
6.2.2.7
Node ID Register (NIDR, 10h~15h) ....................................................................................................... 38
6.2.2.8
Multicast Filter Array (16h~1Dh, R/W) ................................................................................................. 38
6.2.2.9
Driving Stregth Control Register (DSCR, 20h~21h, R/W) .................................................................... 40
6.2.2.10
Medium Status Register (MSR, 22h~23h, R/W) ................................................................................ 40
6.2.2.11
Monitor Mode Status Register (MMSR, 24h, R/W) ........................................................................... 41
6.2.2.12
GPIO Status Register (25h, Read) ...................................................................................................... 42
6.2.2.13
GPIO Control Register (25h, Write) ................................................................................................... 42
6.2.2.14
Ethernet PHY Power and Reset Control Register (EPPRCR, 26h~27h, R/W) ................................. 43
6.2.2.15
Jam Limit Count Register (JLCR, 29h, R/W) .................................................................................... 43
6.2.2.16
VLAN Control Register (VCR, 2Ah~2Dh, Write) .............................................................................. 44
6.2.2.17
VLAN Control Register (VCR, 2Ah~2Dh, Read) ............................................................................... 45
6.2.2.18
COE RX Control Register (CRCR, 34h, R/W) ................................................................................... 46
6.2.2.19
COE TX Control Register (CTCR, 35h, R/W) .................................................................................... 47
4
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.2.20
COE PPPoE Control Register (CPCR, 36h, R/W) ............................................................................. 48
6.2.2.21
Pause Water Level HIGH Register (PWLHR, 54h) ........................................................................... 48
6.2.2.22
Pause Water Level LOW Register (PWLLR, 55h) ............................................................................. 48
6.2.2.23
PIN Control Register (PINCR, 70h)................................................................................................... 48
6.2.3
6.3
7
Wakeup Frame Command Structure ............................................................................................................ 49
INTERRUPT ENDPOINT .......................................................................................................................................... 52
ELECTRICAL SPECIFICATIONS ........................................................................................................................ 53
7.1
DC CHARACTERISTICS ......................................................................................................................................... 53
7.1.1
Absolute Maximum Ratings ......................................................................................................................... 53
7.1.2
Recommended Operating Condition ............................................................................................................ 53
7.1.3
Leakage Current and Capacitance .............................................................................................................. 54
7.1.4
DC Characteristics of 3.3V I/O Pins ........................................................................................................... 54
7.2
THERMAL CHARACTERISTICS ............................................................................................................................... 54
7.3
POWER CONSUMPTION ......................................................................................................................................... 55
7.4
POWER-UP SEQUENCE .......................................................................................................................................... 56
7.5
AC TIMING CHARACTERISTICS ............................................................................................................................. 57
7.5.1 Clock Timing ...................................................................................................................................................... 57
7.5.2 Reset Timing ...................................................................................................................................................... 57
7.5.3 Serial EEPROM Timing ..................................................................................................................................... 58
8
PACKAGE INFORMATION ................................................................................................................................... 59
8.1
68-PIN QFN 8X8 PACKAGE ................................................................................................................................... 59
8.2
RECOMMENDED PCB FOOTPRINT FOR 68-PIN QFN 8X8 PACKAGE ....................................................................... 60
9
10
ORDERING INFORMATION ................................................................................................................................. 61
REVISION HISTORY .......................................................................................................................................... 62
APPENDIX A. DEFAULT WAKE-ON-LAN (DWOL) READY MODE..................................................................... 63
5
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
List of Figures
FIGURE 1
: USB 3.0 TO LAN ADAPTOR ............................................................................................................................. 1
FIGURE 2
: BLOCK DIAGRAM ............................................................................................................................................. 7
FIGURE 3
: PINOUT DIAGRAM ............................................................................................................................................. 8
FIGURE 4
: 25MHZ CRYSTAL OSCILLATOR DIAGRAM ...................................................................................................... 15
FIGURE 5
: MULTICAST FILTER EXAMPLE ........................................................................................................................ 38
FIGURE 6
: MULTICAST FILTER ARRAY HASHING ALGORITHM ........................................................................................ 39
FIGURE 7
: MULTICAST FILTER ARRAY BIT MAPPING ...................................................................................................... 39
FIGURE 8
: 802.1Q VLAN PACKET FORMAT .................................................................................................................... 45
List of Tables
TABLE 1
: PINOUT DESCRIPTION ..................................................................................................................................... 10
TABLE 2
: MFA_3 ~ MFA_0 PIN CONFIGURATION .......................................................................................................... 11
TABLE 3
: THE EXTERNAL 25MHZ CRYSTAL UNITS SPECIFICATIONS ............................................................................. 15
TABLE 4
: SERIAL EEPROM MEMORY MAP ................................................................................................................... 17
TABLE 5
: EFUSE (64-BYTE) MEMORY MAP .................................................................................................................... 18
TABLE 6
: LED MODE SETTING TABLE ........................................................................................................................... 22
TABLE 7
: INTERNAL ROM MEMORY MAP ..................................................................................................................... 23
TABLE 8
: INTERNAL ROM DESCRIPTION ....................................................................................................................... 24
TABLE 9
: USB STANDARD COMMANDS REGISTER MAP ................................................................................................ 28
TABLE 10
: USB VENDOR COMMAND REGISTER MAP .................................................................................................. 29
TABLE 11
: VID1, VID2 SETTING TO FILTER RECEIVED PACKET ................................................................................... 44
TABLE 12
: POWER CONSUMPTION ................................................................................................................................ 55
TABLE 13
: REMOTE WAKEUP TRUTH TABLE ............................................................................................................... 64
6
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
1 Introduction
1.1 General Description
The AX88179 USB 3.0 to 10/100/1000M Gigabit Ethernet controller is a high performance and highly integrated ASIC
which enables low cost, small form factor, and simple plug-and-play Gigabit Ethernet network connection capability for
desktops, notebook PC’s, Ultrabook’s, docking stations, game consoles, digital-home appliances, and any embedded
system using a standard USB port.
The AX88179 features a USB interface to communicate with a USB Host Controller and is compliant with USB
specification V3.0, V2.0, and V1.1. It implements a 10/100/1000Mbps Ethernet LAN function based on IEEE802.3,
IEEE802.3u, and IEEE802.3ab standards with embedded SRAMs for packet buffering. And, it also integrates an on-chip
10/100/1000Mbps EEE-compliant Ethernet PHY to simplify system design.
1.2 Block Diagram
Figure 2
: Block Diagram
7
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
1.3 Pinout Diagram
TEST_N2
GND12A_RX
VCC33IO
XTL25P
XTL25N
GND
EXTWAKE_N
CK25_OUT
VCC3IO
TEST_N3
VCCK
TEST_X
RSET_BG
VCC12A_X
VCC33A_X
CK25_IN
TEST_N4
 68-pin QFN package
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
TEST_N5 52
34 SSRX+
MDIP0 53
33 GND12A_RX
MDIN0 54
32 SSRX-
VCC12A 55
31 VCC12A_RX
MDIP1 56
30 GND12A_TX
MDIN1 57
29 SSTX+
VCC33A_G 58
28 GND12A_TX
AX88179
MDIP2 59
27 SSTX-
MDIN2 60
26 VCC12A_TX
VCC12A 61
25 VCC33A
MDIP3 62
24 D-
MDIN3 63
23 D+
TEST_N6 64
22 GND33A
VCCK 65
21 VBUS
TEST0 66
20 SELF_PWR
TEST1 67
19 VCCK
Figure 3
EECK
EECS
EEDIO
MFA_0
MFA_1
10 11 12 13 14 15 16 17
VCC3IO
GPIO_0/PME
9
TEST_N1
GPIO_1
8
VCCK
GPIO_3
7
GNDK
6
MFA_2
5
MFA_3
3 4
GPIO_2
2
TCLK_1
18 RESET_N
1
TCLK_0
TCLK_EN 68
: Pinout Diagram
8
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
2 Signal Description
The following abbreviations apply to the following pin description table.
I12 Input, 1.2V
AI
Analog Input
I3
Input, 3.3V
AO Analog Output
I5
Input, 3.3V with 5V tolerant
AB Analog Bi-directional I/O
O3
Output, 3.3V
PU
Internal Pull Up (75K ohm)
B5
Bi-directional I/O, 3.3V with 5V tolerant
PD
Internal Pull Down (75K ohm)
B3
Bi-directional I/O, 3.3V
S
Schmitt Trigger
P
Power/GND
T
Tri-stateable
2.1 68-pin Pinout Description
Pin Name
D+
DSSTX+
SSTXSSRX+
SSRXVBUS
Type
AB
AB
AB
AB
AB
AB
I5/PD/S
RSET_BG
AO
MDIP0
MDIN0
AB
AB
MDIP1
MDIN1
AB
AB
MDIP2
MDIN2
AB
AB
MDIP3
MDIN3
AB
AB
XTL25P
XTL25N
CK25_OUT
I3
O3
O3
CK25_IN
I3
EECK
B5/PD/T
EECS
B5/PD/T
EEDIO
B5/PU/T
Pin No
Pin Description
USB Interface
23
USB 2.0 data positive pin.
24
USB 2.0 data negative pin.
29
USB 3.0 transmit data positive pin.
27
USB 3.0 transmit data negative pin.
34
USB 3.0 receive data positive pin.
32
USB 3.0 receive data negative pin.
21
VBUS pin input. Please connect to USB bus power.
Gigabit EEE Ethernet PHY Interface
47
For Ethernet PHY’s internal biasing. Please connect to GND through
a 2.49Kohm ±1% resistor.
53
In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/pair, and is the transmit pair in 10Base-T and 100Base-TX.
54
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is
the receive pair in 10Base-T and 100Base-TX.
56
In MDI mode, this is the second pair in 1000Base-T, i.e. the
BI_DB+/- pair, and is the receive pair in 10Base-T and 100Base-TX.
57
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is
the transmit pair in 10Base-T and 100Base-TX.
59
In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/pair.
60
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
62
In MDI mode, this is the fourth pair in 1000Base-T, i.e., the
BI_DD+/- pair.
63
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
Clock Pins
38
25Mhz ± 0.005% crystal or oscillator clock input.
39
25Mhz crystal or oscillator clock output.
42
A controllable 25Mhz clock output. Please connect it to CK25_IN
pin directly.
50
25Mhz clock input. Please connect it to CK25_OUT pin directly.
Serial EEPROM Interface
16
EEPROM Clock. EECK is an output clock to EEPROM to provide
timing reference for the transfer of EECS, and EEDIO signals.
EECK only drive high / low when access EEPROM otherwise keep
at tri-state and internal pull-down.
17
EEPROM Chip Select. EECS is asserted high synchronously with
respect to rising edge of EECK as chip select signal. EECS only drive
high / low when access EEPROM otherwise keep at tri-state and
internal pull-down.
15
EEPROM Data. EEDIO is the serial output data to EEPROM’s data
input pin and is synchronous with respect to the rising edge of EECK.
EEDIO only drive high / low when access EEPROM otherwise keep
at tri-state and internal pull-up.
9
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
RESET_N
I5/PU/S
EXTWAKE_N
I3/PU/S
SELF_PWR
I5/PD/S
GPIO_3
GPIO_2
GPIO_1
GPIO_0/PME
B3/PD
B3/PD
B3/PD
B3/PD
MFA_3
B3
MFA_2
B3
MFA_1
B3
MFA_0
B3
TCLK_EN
TCLK_0
TCLK_1
TEST0
TEST1
TEST_X
TEST_N1, 2, 3,
4, 5, 6
I3/PD/S
I3/PD
I3/PD
I3/S
I3/S
I3
O3
VCC33A
GND33A
VCC12A_TX
GND12A_TX
VCC12A_RX
GND12A_RX
VCC12A_X
VCC33A_X
VCC12A
VCC33A_G
VCC33IO
GND
VCCK
P
P
P
P
P
P
P
P
P
P
P
P
P
GNDK
VCC3IO
P
P
Misc. Pins
Chip reset input. Active low. This is the external reset source used to
reset this chip. This input feeds to the internal power-on reset
circuitry, which provides the main reset source of this chip.
41
Remote-wakeup trigger from external pin. EXTWAKE_N should be
asserted low for more than 2 cycles of 25MHz clock to be effective.
20
Self_power Indication Input.
0: will respond to Host that this device is a bus-power-device when
Host query device.
1: will respond to Host that this device is a self-power-device when
Host query device.
3
General Purpose Input/ Output Pin 3.
4
General Purpose Input/ Output Pin 2. Please refer to section 2.2.
5
General Purpose Input/ Output Pin 1. Please refer to section 2.2.
6
General Purpose Input/ Output Pin 0 or PME (Power Management
Event). This pin is default as input pin after power-on reset. GPIO_0
also can be defined as PME output to indicate wake up event
detected.
7
It is a multi-function pin. The default is an USB Super-speed
indicator. It also can be a GPIO pin. Please refer to Table 2.
8
It is a multi-function pin. The default is an Ethernet PHY LED
indicator (Link 10/100/1000+Active) and programmable details
please refer to Vndcmd. It also can be a GPIO pin.
Please refer to Table 2.
13
It is a multi-function pin. The default is an Ethernet PHY LED
indicator (Link 10/100/1000) and can be a GPIO pin.
Please refer to Table 2.
14
It is a multi-function pin. The default is an Ethernet PHY LED
indicator (Active) and can be a GPIO pin. Please refer to Table 2.
68
Test pin. For normal operation, user should keep this pin NC.
1
Test pin. For normal operation, user should keep this pin NC.
2
Test pin. For normal operation, user should keep this pin NC.
66
Test pin. For normal operation, user should connect to ground.
67
Test pin. For normal operation, user should connect to ground.
46
Test pin. For normal operation, user should connect to ground.
11, 36, 44, Test pin. No connection
51, 52, 64
Power and Ground Pins
25
Analog Power for USB transceiver. 3.3V.
22
Analog Ground for USB transceiver.
26
Analog Power for USB transceiver. 1.2V.
28,30
Analog Ground for USB transceiver.
31
Analog Power for USB transceiver. 1.2V.
33,35
Analog Ground for USB transceiver.
48
Analog Power for Ethernet PHY. 1.2V.
49
Analog Power for Ethernet PHY. 3.3V.
55,61
Analog Power for Ethernet PHY. 1.2V.
58
Analog Power for Ethernet PHY. 3.3V.
37
Digital I/O Power for Clock pins. 3.3V.
40
Digital Ground for clock pins.
10,19,
Digital Core Power. 1.2V.
45,65
9
Digital Ground to E-pad
12, 43
Digital I/O Power. 3.3V.
18
Table 1
: Pinout Description
10
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
2.2 Hardware Setting For Operation Mode and Multi-Function Pins
The following hardware settings define the desired operation mode and some multi-function pins. The logic level shown on
setting pin below is loaded from the chip I/O pins during power on reset based on the setting of the pin’s pulled-up (as logic
‘1’) or pulled-down (as logic ‘0’) resister on the schematic.
 EEPROM Offset 05h or eFuse Offset 18h, Flag[4]: Defines the multi-function pin GPIO_0 / PME
GPIO_0 is a general purpose I/O normally controlled by vendor commands. Users can change this pin to operate as a PME
(Power Management Event) for remote wake up purpose. Please refer to Section 4.1.2 “Flag” of bit 4 (PME_PIN).
 GPIO_1 pin: Determines whether this chip will go to Default WOL Ready Mode after power on reset. The WOL stands
for Wake-On-LAN.
GPIO_1
0
1
Description
Normal operation mode (default, see Note 1).
Enable Default WOL Ready Mode. Notice that the external pulled-up resistor must be 4.7Kohm.
For more details, please refer to APPENDIX A. Default Wake-On-LAN (WOL) Ready Mode
Note 1: This is the default with internal pulled-down resistor and doesn’t need an external one.
 GPIO_2 pin: Determines whether SSTX+ swaps with SSTX- and SSRX+ swaps with SSRX- for USB3.0 PHY.
GPIO_2
0
1
Description
No swapping (default, see Note 1).
Enable swapping. Notice that the external pulled-up resistor must be 4.7Kohm.
 MFA_3 ~ MFA_0 pins: There are 4 multi-function pins for LED display purpose and as GPIO controlled by vendor
command PIN Control Register MFA_EN (Section 6.2.2.23).
PIN Name
Default definition
MFA_3
LED_USB indicator
(Super-speed)
Programmable LED
(Link 10/100/1000+Active)
Programmable LED
(Link 10/100/1000)
Programmable LED
(Active)
MFA_2
MFA_1
MFA_0
Table 2
Section
4.1.6
LED_3
Section
6.2.1.9 &6.2.1.10
MFAIO_3
LED_2
MFAIO_2
LED_1
MFAIO_1
LED_0
MFAIO_0
: MFA_3 ~ MFA_0 pin configuration
11
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
3 Function Description
3.1 USB Core and Interfaces
The USB core and interfaces contains two USB 3.0 transceiver interfaces (PIPE/UTMI) and a USB3.0 Device Controller.
The USB 3.0 transceiver (or PHY) processes USB3.0/2.0/1.1 Physical layer signals. And, The USB3.0 Device Controller is
interfacing with USB 3.0 transceiver by PIPE/UTMI buses and it processes packets of Link layer and protocol layer. Also,
The USB 3.0 Device Controller contains Bulk IN and Bulk OUT buffers for handling Bulk transfer traffic and a FIFO for
Interrupt IN transfers.
The USB core and interfaces are used to communicate with a USB host controller and is compliant with USB specification
V3.0, V2.0, and V1.1.
3.2 Energy Efficient Ethernet (EEE)
It supports IEEE 802.3az also known as Energy Efficient Ethernet (EEE) at 10Mbps, 100Mbps and 1000Mbps. And also
supports EEE specified a negotiation method to enable link partner to determine whether EEE is supported and to select the
best set of parameters common to both device. It provides a protocol to coordinate transitions to/from a lower power
consumption level (Low Power Idle mode) based on link utilization. When no packets are being transmitted, the system
goes to Low Power Idle mode to save power. Once packets need to be transmitted, the system returns to normal mode, and
does this without changing the link status and without dropping/corrupting frames.
To save power, when the system is in Low Power Idle mode, most of the circuits are disabled; however, the transition time
to/from Low Power Idle mode is kept small enough to be transparent to upper layer protocols and applications.
3.3 10/100/1000M Ethernet PHY
The 10/100/1000M Ethernet PHY is compliant with 10Base-T, 100Base-TX, and 1000Base-T IEEE 802.3 standards. It
provides all the necessary physical layer functions to transmit and receive Ethernet packets over CAT 5 UTP cable or CAT
3 UTP (10Mbps only) cable. It uses state-of-the-art DSP technology and an Analog Front End (AFE) to enable high-speed
data transmission and reception over UTP cable. Functions such as Crossover Detection & Auto-Correction, polarity
correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are
implemented.
12
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
3.4 GMAC Core
The MAC core supports IEEE 802.3, IEEE 802.3u and IEEE 802.3ab MAC sub-layer functions, such as basic MAC frame
receive and transmit, CRC checking and generation, filtering, forwarding, flow-control in full-duplex mode, and
collision-detection and handling in half-duplex mode, etc. It supports virtual local area network (VLAN)-tagged frames
according to IEEE 802.1Q specification in both transmit and receive functions, CRC-32 checking at full speed using a
multi-stage, cyclic redundancy code (CRC) calculation architecture with optional forwarding of the frame check sequence
(FCS) field to the user application CRC-32 generation and append on transmit.
3.5 Checksum Offload Engine (COE)
The Checksum Offload Engine (COE) supports IPv4, IPv6, layer 4 (TCP, UDP, ICMP, ICMPv6 and IGMP) header
processing functions and real time checksum calculation in hardware
The COE supports the following features in layer 3:

IP header parsing, including IPv4 and IPv6

IPv6 routing header type 0 supported

IPv4 header checksum check and generation (There is no checksum field in IPv6 header)

Detecting on RX direction for IP packets with error header checksum
The COE supports the following features in layer 4:

TCP and UDP checksum check and generation for non-fragmented packet

TCP Large Send Offload V1

ICMP, ICMPv6 and IGMP message checksum check and generation for non-fragmented packet
3.6 Memory Arbiter
The memory arbiter block is responsible for storing received MAC frames into on-chip SRAM (packet buffer) and then
forwarding it to the USB bus upon request from the USB host via Bulk IN transfer. It also monitors the packet buffer usage
in full-duplex mode for triggering PAUSE frame (or in half-duplex mode to activate Backpressure jam signal) transmission
out on transmit (TX) direction. The memory arbiter block is also responsible for storing MAC frames received from the
USB host via Bulk OUT transfer and scheduling transmission out towards Ethernet network.
13
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
3.7 USB to Ethernet Bridge
The USB to Ethernet bridge block is responsible for converting Ethernet MAC frame into USB packets or vice-versa. This
block supports proprietary burst transfer mechanism (US Patent Approval) to offload software burden and to offer very high
packet transfer throughput over USB bus.
This USB to Ethernet bridge block not only co-work with “eFuse and Control”, “SEEPROM Loader I/F”, and General
Purpose I/Os and LEDs, but also handle USB Control transfers of Endpoint 0.
3.8 eFuse and Control
The eFuse (64-byte) and Control supports user to program USB descriptions and some device information. The data format
is shown at Section 4.
3.9 SEEPROM Loader Interface
The SEEPROM loader interface is responsible for reading configuration data automatically from the external serial
EEPROM or eFuse after power-on reset.
If the content of EEPROM offset 05h (low byte) was equal to (0xFF - SUM [EEPROM offset 03h ~ 04h]), the EEPROM is
the first candidate for SEEEPROM loader. If failed checksum checking the eFuse will be the second candidate.
If this SEEPROM Loader checks the 1st byte data of efuse is not equal to 0xFF and the eFuse Checksum [7:0] of eFuse
offset 19h is correct, the content of eFuse is valid for SEEPROM loader. If eFuse Checksum [7:0] is incorrect, the chip’s
internal default setting will be brought up to configure the corresponding valus and respond to USB standard commands,
etc.
3.10 General Purpose I/O and LED
There are 4 general-purpose I/O pins (named GPIO_0/1/2/3) and 4 multi-function pins group A (named MFA_0/1/2/3)
provided by this chip. The MFA_0/1/2/3 pins are also used for LED indication. Please refer to Section 4.1.6 for details.
14
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
3.11 PLL Clock Generator
The AX88179 integrates internal oscillator circuits for 25 MHz, respectively, which allow the chip to operate cost
effectively with just external 25 MHz crystals.
The external 25 MHz crystal or oscillator, via pins XTL25P/XTL25N, provides the reference clock to internal oscillation
circuit to generate clock source for the embedded Ethernet PHY, embedded USB PHY, and base clock for ASIC use.
The external 25MHz Crystal spec is listed in below table. For more details on crystal timing, please refer to Section 7.5.1
“Clock Timing” and AX88179 Demo board schematic reference.
Parameter
Symbol
Nominal Frequency
Typical Value
25.000000MHz
Fo
Oscillation Mode
Fundamental
±30ppm
Frequency Tolerance(@25℃)
0℃ ~ +70℃, Commerical version
Operation Temperature Range
-40℃ ~ +85℃, Industrial version
±3ppm/year
Aging
Table 3
: The external 25MHz Crystal Units specifications
Figure 4
: 25MHz crystal oscillator diagram
15
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
3.12 Reset Generation
The AX88179 integrates an internal power-on-reset circuit, which can simplify the external reset circuitry on PCB design.
The power-on-reset circuit generates a reset pulse to reset chip logic after 1.2V core power ramping up to 0.72V (typical
threshold). The external hardware reset input pin, RESET_N, is fed directly to the input of the power-on-reset circuit and
can also be used as additional hardware reset source to reset the system logic. For more details on RESET_N timing, please
refer to 7.5.2 Reset Timing.
16
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4 Serial EEPROM/eFuse Memory Map
EEPROM
OFFSET
00h
HIGH BYTE
LOW BYTE
Node ID 1
Node ID 0 (Note_1)
01h
Node ID 3
Node ID 2
02h
Node ID 5
Node ID 4
03h
PID_HB
PID_LB
04h
VID_HB
VID_LB
05h
Flag
EEPROM Checksum (Note_2)
06h
Reserved
Reserved
07h
Max. Power for Self Power
Max. Power for Bus Power
08h
EndPoint1 for SS/HS
EndPoint1 for FS
09h
Language ID High Byte
Language ID Low Byte
0Ah
Length of Product String (bytes)
Offset of Product String (0Eh)
0Bh
Length of Manufacturer String (bytes)
Offset of Manufacturer String (1Ah)
0Ch
Length of Serial Number String (bytes)
Offset of Serial Number String (26h)
0Dh
Length of BOS-type Descriptor (bytes)
Offset of BOS-type Descriptor (2Dh)
19~0Eh
Product String: (Max.) 24 bytes
25~1Ah
Manufacturer String: (Max.) 24 bytes
2C~26h
Serial Number String: (Max.) 14 bytes
3B~2Dh
BOS-type Descriptor: (Max.) 30 bytes
3Ch
Reserved
41~3Dh
42h
Max. Burst: [7:4] for EP3, [3:0] for EP2
Fixed_pattern (10 bytes)
LED_Mode_HB
Table 4
LED_Mode_LB
: Serial EEPROM Memory Map
Note_1: The Node ID 0 value cannot be set to 0xFF and 1st bit of Node ID 0 can not be set to “1” (i.e. cannot be set to
multicast MAC address).
Note_2: The value of EEPROM Checksum field located at EEPROM offset 05h (low byte). The correct value must be equal
to (0xFF - SUM [EEPROM offset 03h ~ 04h]). If SUM [EEPROM offset 03h ~ 04h] has carry, please add ‘1’ to its
result.
Note_3: Total usage is about 134 bytes.
17
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
eFuse
OFFSET
00h
HIGH BYTE
LOW BYTE
Node ID 1
Node ID 0 (Note_1)
01h
Node ID 3
Node ID 2
02h
Node ID 5
Node ID 4
03h
PID_HB
PID_LB
04h
VID_HB
VID_LB
05h
Reserved
Max. Power for Bus Power
06h
EndPoint1 for SS/HS
EndPoint1 for FS
07h
Language ID High Byte
Language ID Low Byte
08h
Length of Product String (bytes)
Offset of Product String (0Bh)
09h
Length of Manufacturer String (bytes)
Offset of Manufacturer String (11h)
0Ah
Length of BOS-type Descriptor (bytes)
Offset of BOS-type Descriptor (16h)
10~0Bh
Product String: (Max.) 12 bytes
15~11h
Manufacturer String: (Max.) 10 bytes
16h
BOS-type Descriptor: (Max.) 2 bytes,
LowByte: SS USB Device Capability bU1DevExitLat,
HighByte: SS USB Device Capability bU2DevExitLat LowByte
Max. Burst, [7:4] for EP3, [3:0] for EP2
BOS-type Descriptor: 1 byte,
SS USB Device Capability bU2DevExitLat HighByte
Flag
Reserved
17h
18h
19h
LED_Mode_LB
1Ah
Fixed_pattern (First byte)
LED_Mode_HB
th
1E~1Bh
1Fh
eFuse Checksum[7:0] (Note_2)
nd
Fixed_pattern (9 ~2 bytes)
Fixed_pattern (10th byte)
Max. Power for Self Power [3:0] and
Reserved [7:4]
Table 5
: eFuse (64-byte) Memory Map
Note_1: The Node ID 0 value cannot be set to 0xFF and 1st bit of Node ID 0 can not be set to “1” (i.e. cannot be set to
multicast MAC address).
Note_2: The correct value of eFuse Checksum field must be equal to (0xFF - SUM [eFuse offset 00h ~ 1Fh excluding eFuse
Checksum field]). If SUM [eFuse offset 00h ~ 1Fh excluding eFuse Checksum field] has carry, please add ‘1’ to its
result.
18
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4.1 Detailed Description
The following sections provide detailed descriptions for some of the fields in memory maps of serial EEPROM and eFuse.
Please refer to AX88179 EEPROM User Guide for more details.
4.1.1
Node ID (00~02h)
The Node ID 0 to 5 bytes represent the MAC address of the device, for example, if MAC address = 04-23-45-67-89-AB,
then Node ID 0 = 04h, Node ID 1 = 23h, Node ID 2 = 45h, Node ID 3 = 67h, Node ID 4 = 89h, and Node ID 5 = ABh.
Default values: Node ID {0, 1, 2, 3, 4, 5} = 00-0E-C6-81-79-01.
4.1.2
Flag (EEPROM: 05h, eFuse:18h)
Bit 7
PME_IND
Bit 6
PME_TYPE
Bit 5
PME_POL
Bit 4
PME_PIN
Bit 3
SNT
Bit 2
0
Bit 1
WOLLP
Bit 0
RWU
RWU: Remote Wakeup support.
1: Indicate that this device supports Remote Wakeup (default).
0: Not support.
WOLLP: Wake-On-LAN Low Power function.
1: Enabled (default).
0: Disabled.
SNT: Serial Number Type. (Only valid for eFuse)
When SEEPROM loader selected EEPROM:
Please set this bit to ‘0’ for EEPROM. The Serial Number String will refer to Table 4 EEPROM offset 26h ~2Ch.
When SEEPROM loader selected eFuse:
1: Serial Number String is fixed to “00000000000001”.
0: Use Node ID as Serial Number String (default).
For example, when Node ID {0, 1, 2, 3, 4, 5} = 00-0E-C6-81-79-01,
Serial Number String = “00000EC6817901”.
PME_PIN: PME / GPIO_0.
1: Set GPIO_0 pin as PME (default).
0: GPIO_0 pin is controlled by vendor command.
PME_POL: PME pin active Polarity.
1: PME active high (default).
0: PME active low.
19
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
PME_TYP: PME I/O Type.
1: PME output is a Push-Pull driver (default).
0: PME output to function as an open-drain buffer.
PME_IND: PME indication.
1: A 1.363ms pulse active when detecting wake-up event.
0: A static signal active when detecting wake-up event (default).
4.1.3
Max. Power for Self/Bus Power (07h)
They are Max power values’ setting of powerd device for EEPROM at offset 07h. Bus power setting for eFuse is at
offset 05h (Low Byte), and Self power setting for eFuse at offset 1Fh (High Byte) [3:0].
The default value of Bus Power is 3Eh: For USB 3.0, the power value is 496mA (Unit = 8mA).
For USB 2.0, the power value is 248mA (Unit = 4mA).
Self power setting follows conversion above.
4.1.4
EndPoint1 for SS/HS/FS (EEPROM:08h, eFuse: 06h)
It's Interval (named “bInterval”) for polling Interrupt IN endpoint 1 for data transfers of
Super-Speed/High-Speed/Full-Speed. Expressed in frames or microframes depending on the device operating speed
(i.e. either 1 millisecond or 125 μs units).
(11-1)
The default “bInterval” value is 0Bh for Super-Speed/High-Speed (the polling time of endpoint 1= 2
* 125
μs=128ms) and is 80h for Full-Speed (the polling time of endpoint 1= 128 * 1ms=128ms).
Keep this field as the recommended default values (0Bh for Super-Speed/High-Speed & 80h for Full-Speed).
4.1.5
Max. Burst for EP3/EP2 (EEPROM: 3Ch, eFuse: 17h)
This value is bMaxBurst field in SS endpoint companion descriptor. Refer USB 3.0 spec. 9.6.7.
20
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4.1.6
LED Mode (EEPROM: 42h, eFuse: 19h~1Ah)
It’s to define the indication setting for LED_0/1/2/3 function of MFA_0/1/2/3 pins.
Bit 7~Bit 0: LED_Mode_LB; Bit 15~Bit 8: LED_Mode_HB
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
LED1_100
LED1_10 LED1_Active LED0_Duplex LED0_1000 LED0_100
LED0_10
LED0_Active
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
1
LED2_Duplex LED2_1000 LED2_100
LED2_10 LED2_Active LED1_Duplex LED1_1000
Note: Bit 15 must be ‘1’ to enable the LED_mode setting; otherwise, it will work at default LED mode.
The LED mode table is as below:
bit
4
Full duplex
0
LED_0
bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
9
Full duplex
0
LED_1
0
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
Link speed(Mbps)
1000
100
10
0
0
0
0
Active
(TX/RX)
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
8
7
6
Link speed(Mbps)
1000
100
10
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
5
Active
(TX/RX)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description of indication
USB3.0 Super Speed: It keeps radiating
when device operated at USB3.0 Super
Speed.
Active (Default for LED_0)
Link 10
Link 10+Active
Link 100
Link 100+Active
Link 100/10
Link 100/10+Active
Link 1000
Link 1000+Active
Link 1000/10
Link 1000/10+Active
Link 1000/100
Link 1000/100+Active
Link 1000/100/10
Link 1000/100/10+Active
Full duplex
Description of indication
USB3.0 Super Speed: It keeps radiating
when device operated at USB3.0 Super
Speed.
Active
Link 10
Link 10+Active
Link 100
Link 100+Active
Link 100/10
Link 100/10+Active
Link 1000
Link 1000+Active
Link 1000/10
Link 1000/10+Active
Link 1000/100
Link 1000/100+Active
21
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
0
0
1
14
Full duplex
bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4
Full duplex
LED_2
bit
0
1
1
1
1
1
1
0
0
0
13
12
11
Link speed(Mbps)
1000
100
10
0
0
0
0
1
0
10
Active
(TX/RX)
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
3
2
1
Link speed(Mbps)
1000
100
10
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
Active
(TX/RX)
1
LED_3
Table 6
4.1.7
Link 1000/100/10
Link 1000/100/10+Active
Full duplex
Description of indication
USB3.0 Super Speed: It keeps radiating
when device operated at USB3.0 Super
Speed.
Active
Link 10
Link 10+Active
Link 100
Link 100+Active
Link 100/10
Link 100/10+Active
Link 1000
Link 1000+Active
Link 1000/10
Link 1000/10+Active
Link 1000/100
Link 1000/100+Active
Link 1000/100/10
Link 1000/100/10+Active
Full duplex
Description of indication
USB3.0 Super Speed: The LED_0 mode
MUST be set to “Active” only when the
LED_3 is used.
It will radiate when device operated at
USB3.0 super speed and keep flashing
when device is receiving/ transmitting
packets.
: LED Mode Setting Table
Fixed_pattern (EEPROM: 41~3Dh, eFuse: 1F~1Ah)
Please write these 10 bytes of fixed_pattern with hexadecimal (from low bytes to high bytes) = “40 4A 40 00 40 30 0D
49 90 41”.
22
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4.2 Internal ROM Default Settings
AX88179 supports internal ROM default settings inside chip hardware to enable it to communicate with USB host
controller during enumeration when the AX88179 EEPROM is blank (prior to being programmed) or the value of
EEPROM Checksum field is wrong or the 1st byte data of EEPROM is 0xFF. The default settings inside chip facilitate
users to update the EEPROM content through a Windows PC during R&D validation process or program a blank
EEPROM/eFuse during manufacturing process.
Below table shows AX88179’s internal ROM default settings being used in the case of blank EEPROM or
EEPROM with wrong checksum value or 1st byte data is 0xFF on board. Each of the address offset contains 16-bit data
from left to right representing the low-byte and high-byte, respectively. For example, in offset address 0x01, the ‘C6’ is
low-byte data and the ‘81’ is high-byte data.
Offset
Address
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x78
0x80~FF
0
8
00 0E
80 0B
31 37
00 00
6F 72
30 30
10 02
00 00
0D 49
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
1
9
C6 81
09 04
39 00
00 00
70 2E
30 30
02 00
00 00
90 41
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
2
A
79 01
0E 07
00 00
41 53
00 00
30 30
00 00
00 00
00 40
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
3
B
90 17
1A 10
00 00
49 58
00 00
30 30
0A 10
00 00
00 80
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
4
C
95 0B
26 0E
00 00
20 45
00 00
30 31
03 00
F3 FF
20 08
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
5
D
B7 73
2D 16
00 00
6C 65
00 00
05 0F
0E 00
40 42
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
Note: The 6 bytes from Internal ROM memory offset 42h to offset 44h are unused.
Table 7
: Internal ROM Memory Map
23
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
6
E
00 E0
41 58
00 00
63 2E
30 30
16 00
01 0A
40 00
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
7
F
3E 01
38 38
00 00
20 43
30 30
02 07
FF 07
40 30
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4.2.1 Internal ROM Description
The internal ROM is a fixed value. User can’t modify it.
Field Definition
Node ID
Product ID (PID)
Address
Offset
00h ~02h
03h
Vender ID (VID)
Checksum
04h
05h
(Low byte)
Flag - Remote Wakeup 05h
and PME setting, etc.
(High byte)
Max Power for
Bus Power
07h
(Low byte)
Max Power for
Self Power
07h
(High byte)
Length of Product String 0Ah
(High byte)
Length of Manufacturer 0Bh
String
(High byte)
Length of Serial Number 0Ch
String
(High byte)
Product String
0Eh~19h
(Max. 24 bytes)
Manufacture String
1Ah~25h
(Max. 24 bytes)
Serial Number String
26h~2Ch
(Max. 14 bytes)
BOS-type Descriptor
2Dh~3Bh
(Max. 30 bytes)
Default Values
Description
00 0E C6 81 79 01
90 17
Node ID 0 ~ 5
The PID of AX88179 is
0x1790
95 0B
ASIX’s VID is 0x0B95
B7
0xFF - SUM [EEPROM
offset 03h ~ 04h]
73
Enable the “remote
wakeup” and Low Power
WOL function,
(Note 1)
3E
496mA for USB 3.0
248mA for USB 2.0
(Note 2)
01
8mA for USB 3.0
4mA for USB 2.0
(Note 2)
07
Product String Length
(Note 3)
10
Manufacturer String
Length (Note 3)
0E
Serial Number String
Length (Note 3)
41 58 38 38 31 37 39 00 00 00 00 00 00 00 00 “AX88179”
00 00 00 00 00 00 00 00 00
41 53 49 58 20 45 6C 65 63 2E 20 43 6F 72 70 “ASIX Elec. Corp.”
2E 00 00 00 00 00 00 00 00
30 30 30 30 30 30 30 30 30 30 30 30 30 31 “00000000000001”
05 0F 16 00 02
07 10 02 02 00 00 00
0A 10 03 00 0E 00 01 0A FF 07
00 00 00 00 00 00 00 00
Table 8
BOS descriptor
USB 3.0 extension
super speed USB
: Internal ROM Description
24
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Note 1:
Remote Wakeup/PME Settings
The offset 05h field of AX88179 EEPROM is used to configure the Remote Wakeup and PME functions.
Please refer to Section 4 “Serial EEPROM/eFuse Memory Map” for the detailed description of EEPROM offset
05h.
The RWU bit of AX88179 EEPROM offset 05h is used to configure the “bmAttributes” field of Standard
Configuration Descriptor that will be reported to the USB host controller when the GET_DESCRIPTOR
command with CONFIGURATION type is issued. Please refer to below table or “Section 9.6.3 Configuration” of
Universal Serial Bus 3.0 Spec for the detailed description of the “bmAttributes” field of Standard Configuration
Descriptor.
The power mode about Bus-powered or Self-powerd is decided by the SELF_PWR pin when chip powers on.
This will updated to the “bmAttributes” field of Standard Configuration Descriptor.
Note 2: Max Power Setting
The low byte of AX88179 EEPROM offset 07h (for bus-powered) field and high byte of AX88179 EEPROM
offset 07h (for self-powered) field are used to configure the “bMaxPower” field of Standard Configuration
Descriptor that will be reported to the USB host controller when the GET_DESCRIPTOR command with
CONFIGURATION type is issued. Please refer to below table or “Section 9.6.3 Configuration” of Universal
Serial Bus 3.0 Spec for the detailed description of the “bMaxPower” field of Standard Configuration Descriptor.
These fields are used to define the Maximum power consumption of the USB device drawn from the USB bus in
this specific configuration when the device is fully operational.
25
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Note 3: Product/Manufacturer/Serial Number String Settings
The “Offset” fields of Product/Manufacturer/Serial Number String are fixed in AX88179 EEPROM/eFuse
memory map. Please DON’T change the recommended values of these fields.
If you need to change the Product/Manufacturer/Serial Number strings on your AX88179 EEPROM/eFuse, please
modify the “Length” fields of Product/Manufacturer/Serial Number String to meet the exact string length of your
Product/Manufacturer/Serial Number strings.
4.2.2 External EEPROM Description
User can assign the specific VID/PID, Serial Number, Manufacture String, Product String, etc. user defined fields by
external EEPROM or embedded eFuse. Please refer to AX88179 EEPROM User Guide document for more details
about how to configure AX88179 EEPROM/eFuse content.
Note the EEPROM checksum field should be changed together with the VID/PID fields.
26
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
5 USB Configuration Structure
5.1 USB Configuration
The AX88179 supports 1 Configuration.
5.2 USB Interface
The AX88179 supports 1 interface.
5.3 USB Endpoints
The AX88179 supports following 4 endpoints:
 Endpoint 0: Control endpoint. It is used for configuring the device. Please refer to 6.1 USB Standard Commands and 6.2
USB Vendor Commands.
 Endpoint 1: Interrupt endpoint. It is used for reporting network Link status. Please refer to 6.3 Interrupt Endpoint.
 Endpoint 2: Bulk IN endpoint. It is used for receiving Ethernet Packet.
 Endpoint 3: Bulk OUT endpoint. It is used for transmitting Ethernet Packet.
27
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6 USB Commands
6.1 USB Standard Commands

The Language ID is 0x0904 for English

PPLL means buffer length

CC means configuration number

I I means Interface number

AA means Device Address
Setup Command
8006_0001_0000_LLPP
Data Bytes
PPLL bytes in Data stage
Access Type
Read
8006_0002_0000_LLPP
PPLL bytes in Data stage
Read
Get Configuration Descriptor
8006_0003_0000_LLPP
PPLL bytes in Data stage
Read
Get Supported Language ID
8006_000F_0000_LLPP
PPLL bytes in Data stage
Read
Get BOS Descriptor
8006_0103_0904_LLPP
PPLL bytes in Data stage
Read
Get Manufacture String
8006_0203_0904_LLPP
PPLL bytes in Data stage
Read
Get Product String
8006_0303_0904_LLPP
PPLL bytes in Data stage
Read
Get Serial Number String
8006_0403_0904_LLPP
PPLL bytes in Data stage
Read
Get Interface String
8008_0000_0000_0100
1 bytes in Data stage
Read
Get Configuration
0009_CC00_0000_0000
No data in Data stage
Write
Set Configuration
810A_0000 _I I00_0100
1 bytes in Data stage
Read
Get Interface
010B_AS00_0000_0000
No data in Data stage
Write
Set Interface
0005_AA00_0000_0000
No data in Data stage
Write
Set Address
Table 9
Description
Get Device Descriptor
: USB Standard Commands Register Map
28
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2 USB Vendor Commands Description

AA, CC: The index of register or the content of register.

BB, DD: The content of register
No.
1
2
3
4
5
Setup Command
C001_AA00_CC00_EE00
4001_AA00_CC00_EE00
C003_AA00_CC00_EE00
4003_AA00_CC00_EE00
C004_AA00_CC00_EE00
Data stage byte
EE bytes (1~8 bytes)
EE bytes (1~8 bytes)
EE bytes
EE bytes
EE bytes (2~64 bytes)
Access Type
Read
Write
Read
Write
Read
6
7
8
9
10
C005_AA00_CC00_EE00
4005_ AA00_CC00_EE00
4006_0000_0000_0000
C010_0000_0000_0400
4010_AABB_CCDD_0000
EE bytes (2~64 bytes)
EE bytes (2~64 bytes)
None
4 bytes
None
Read
Write
Write
Read
Write
Table 10
Description
Read MAC register
Write MAC register
Read wakeup frame register
Write wakeup frame register
Read Non-Volatile Setting
Register
Read eFuse
Write eFuse
Reload EEPROM/eFuse
Read MFA
Write MFA
: USB Vendor Command Register Map
6.2.1 USB Vendor Command Format
6.2.1.1
Read MAC Register (C001_AA00_CC00_EE00)
This command is used to read MAC registers. This command sends address and length of MAC register to device, and
device will return the data value in the data stage. The limit of length is from 1 to 8 bytes.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
AA [7:0]
00h
CC [7:0]
00h
EE [7:0]
AA [7:0]: The address of MAC register.
CC [7:0]: The length of MAC register in byte. Limit is from 1 to 8.
EE [7:0]: Same as CC.
Data Stage: The data value read from MAC register.
29
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Bit0
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.1.2
Write MAC Register (4001_AA00_CC00_EE00)
This command is used to write MAC registers. This command sends MAC register’s address, length and the written
data value (in data stage) to device. The limit of length is from 1 to 8 bytes.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit1
Bit0
AA [7:0]
00h
CC [7:0]
00h
EE [7:0]
AA [7:0]: The address of MAC register.
CC [7:0]: The length of MAC register in byte. Limit is from 1 to 8.
EE [7:0]: Same as CC.
Data Stage: The data value which will be written to MAC register.
6.2.1.3
Bit7
Read Wakeup Frame Register (C003_AA00_CC00_EE00)
Bit6
Bit5
Bit4
Bit3
Bit2
AA [7:0]
00h
CC [7:0]
00h
EE [7:0]
AA [7:0]: Wakeup frame command type.
0x01: wakeup frame command
0x02: wakeup frame byte mask
CC [7:0]: Byte mask offset. Only used when AA is 0x02.
EE [7:0]: Data length in data stage.
Data stage: When AA is 0x01, this data stage content is the wakeup frame command. This length is fixed to 38
or 50 bytes. Refer to Section 6.2.3.
When AA is 0x02, this data stage content is one set of wakeup frame byte mask. Max length is 64
bytes.
30
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.1.4
Bit7
Write Wakeup Frame Register (4003_AA00_CC00_EE00)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
AA [7:0]
00h
CC [7:0]
00h
EE [7:0]
AA [7:0]: Wakeup frame command type.
0x01: wakeup frame command
0x02: wakeup frame byte mask
CC [7:0]: Byte mask offset. Only used when AA is 0x02.
EE [7:0]: Data length in data stage.
Data stage: When AA is 0x01, this data stage content is the wakeup frame command. The length is fixed to 38 or
50 bytes. Refer to Section 6.2.3.
When AA is 0x02, this data stage content is one set of the wakeup frame byte mask. Max length is 64
bytes.
6.2.1.5
Bit7
Read Non-Volatile Setting Register (C004_AA00_CC00_EE00)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
AA [7:0]
00h
CC [7:0]
00h
EE [7:0]
AA [7:0]: The read start address of non-volatile setting according EEPROM memory map.
CC [7:0]: The read length in word. Limit is from 1 to 32.
EE [7:0]: Data length in data stage.
Data Stage: The data value read from non-volatile setting
If the external EEPROM is in used and valid, this read command will return the external EEPROM value.
If no external EEPROM in use and eFuse is valid, this read command will return the Non-Volatile Setting with
EEPROM memory map included the auto-loaded eFuse setting value.
If both of EEPROM and eFuse data are invalid, this read command will return internal ROM setting value.
Note: If you would like to read/write external EEPROM data of AX88179 devices, please refer to Section 6.2.2.2 ~
6.2.2.5 to read/write the exact external EEPROM data.
31
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.1.6
Bit7
Read eFuse Register (C005_AA00_CC00_EE00)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
AA [7:0]
00h
CC [7:0]
00h
EE [7:0]
AA [7:0]: The read start address of eFuse.
CC [7:0]: The read length in word. Limit is from 1 to 32.
EE [7:0]: Data length in data stage.
Data Stage: The data value read from eFuse.
6.2.1.7
Bit7
Write eFuse Register (4005_ AA00_CC00_EE00)
Bit6
Bit5
Bit4
Bit3
AA [7:0]
00h
CC [7:0]
00h
EE [7:0]
AA [7:0]: The write start address of eFuse.
CC [7:0]: The write length in word. Limit is from 1 to 32.
EE [7:0]: Data length in data stage.
Data Stage: The data value which will be written to eFuse.
6.2.1.8
Reload EEPROM/eFuse Control Register (4006_0000_0000_0000)
Use this command to reload data from EEPROM or eFuse.
32
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.1.9
Read MFA Control Register (C010_0000_0000_0400)
Data Stage:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit3
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
Bit1
Bit0
Bit1
Bit0
Byte 0
Byte 1
Byte 2
Byte 3
Byte 0:
Bit7
Bit6
Bit5
Bit4
Reserved
Byte 1:
Bit7
MFAI_3
Bit6
MFAI_2
Bit5
MFAI_1
Bit4
MFAI_0
Bit3
Bit6
Bit5
Bit4
Bit3
Bit2
Bit3
Bit2
Reserved
Byte 2:
Bit7
Reserved
Byte 3:
Bit7
MFAOE_3
Bit6
MFAOE_2
Bit5
MFAOE_1
Bit4
MFAOE_0
Reserved
MFAOE _n: Output enable of MFA_n pins. N=0, 1, 2, 3.
1: Output.
0: Input.
MFAI_n: Input level on MFA_n pin when MFA_n is an input pin. N=0, 1, 2, 3.
33
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.1.10
Bit7
Write MFA Control Register (4010_AABB_CCDD_0000)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit3
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
Bit1
Bit0
Bit1
Bit0
AA [7:0]
BB [7:0]
CC [7:0]
DD [7:0]
AA [7:0]:
Bit7
Bit6
Bit5
Bit4
Reserved
BB [7:0]:
Bit7
MFAO_3
Bit6
MFAO_2
Bit5
MFAO_1
Bit4
MFAO_0
Bit3
Bit6
Bit5
Bit4
Bit3
Bit2
Bit3
Bit2
Reserved
CC [7:0]:
Bit7
Reserved
DD [7:0]:
Bit7
MFAOE_3
Bit6
MFAOE_2
Bit5
MFAOE_1
Bit4
MFAOE_0
Reserved
MFAOE_n: Pin MFA_n Output Enable. N=0, 1, 2, 3.
1: Output is enabled (meaning MFA_n is used as an output pin).
0: Output is tri-stated (meaning MFA_n is used as an input pin) (default).
MFAO_n: Pin MFA_n Output Value. Default value is ‘0’. N=0, 1, 2, 3.
34
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.2 MAC Register Description
Address
02h
Size in byte
NAME
1
PLSR
Description
Physical Link Status Register
07h
08h
09h
0Ah
1
1
1
1
EAR
EDLR
EDHR
ECR
EEPROM Address Register
EEPROM Data Low Register
EEPROM Data High Register
EEPROM Command Register
0Bh
10h
16h
20h
22h
24h
25h
26h
29h
2Ah
34h
35h
36h
54h
55h
70h
2
6
8
2
2
1
1
2
1
4
1
1
1
1
1
1
RCR
NIDR
MFA
DSCR
MSR
MMSR
GPIOCR
EPPRCR
JLCR
VCR
CRCR
CTCR
CPCR
PWLHR
PWLLR
PINCR
RX Control Register
Node ID Register
Multicast Filter Array
Driving Stregth Control Register
Medium Status Register
Monitor Mode Status Register
GPIO Control/Status Register
Ethernet PHY Power and Reset Control Register
Jam Limit Count Register
VLAN Control Register
COE RX Control Register
COE TX Control Register
COE PPPoE Control Register
Pause Water Level HIGH Register
Pause Water Level LOW Register
PIN control Register
6.2.2.1
Bit7
Reserved
Physical Link Status Register (PLSR, 02h, Read only)
Bit6
EPHY_1000
Bit5
EPHY_100
Bit4
EPHY_10
Bit3
Reserved
Bit2
USB_SS
Bit1
USB_HS
USB_FS: USB linked at Full Speed.
USB_HS: USB linked at High Speed.
USB_SS: USB linked at Super Speed.
EPHY_10: EPHY linked at 10Mbps.
EPHY_100: EPHY linked at 100Mbps.
EPHY_1000: EPHY linked at 1000Mbps.
All default values are “0”
35
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Bit0
USB_FS
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.2.2
Bit7
EEPROM Address Register (EAR, 07h, R/W)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
AA [7:0]
AA [7:0]: The address of Serial EEPROM.
6.2.2.3
Bit7
EEPROM Data Low Register (EDLR, 08h, R/W)
Bit6
Bit5
Bit4
Bit3
AA [7:0]
AA[7:0]: The low byte data of Serial EEPROM. (Read is from output of EEPROM access module, write is to input of
EEPROM module)
6.2.2.4
Bit7
EEPROM Data High Register (EDHR, 09h, R/W)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
AA [7:0]
AA [7:0]: The high byte data of Serial EEPROM. (Read is from output of EEPROM access module, write is to input of
EEPROM module)
6.2.2.5
EEPROM Command Register (ECR, 0Ah)
Bit7
Bit6
Reserved
Bit5
Bit4
BUSY
Bit3
WR
Bit2
RD
Bit1
WD
WE: EEPROM write enable command. (R/W)
WD: EEPROM write disable command. (R/W)
RD: EEPROM read command. (R/W)
WR: EEPROM write command. (R/W)
BUSY: EEPROM access module busy. (R)
36
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Bit0
WE
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.2.6
Bit7
SO
Rx Control Register (RCR, 0Bh~0Ch)
Bit6
Reserved
Bit5
AP
Reserved
Bit4
AM
Bit3
AB
Bit2
0
TX_CRC_Pad_n
Bit1
AMALL
IPE_n
Bit0
PRO
Drop_CRCE_n
AA [7:0] = {SO, Reserved, AP, AM, AB, 0, AMALL, PRO}
BB [7:0] = {Reserved, TX_CRC_Pad_n, IPE_n, Drop_CRCE_n}
PRO: PACKET_TYPE_PROMISCUOUS. (R/W)
1: All frames received by the ASIC are forwarded up toward the host.
0: Disabled (default).
AMALL: PACKET_TYPE_ALL_MULTICAST. (R/W)
1: All multicast frames received by the ASIC are forwarded up toward the host, not just the frames whose
scrambling result of DA matching with multicast address list provided in Multicast Filter Array Register.
0: Disabled. This only allows multicast frames whose scrambling result of DA field matching with multicast address
list provided in Multicast Filter Array Register to be forwarded up toward the host (default).
AB: PACKET_TYPE_BROADCAST. (R/W)
1: All broadcast frames received by the ASIC are forwarded up toward the host (default).
0: Disabled.
AM: PACKET_TYPE_MULTICAST. (R/W)
1: All multicast frames whose scrambling result of DA matching with multicast address list are forwarded up to the
host (default).
0: Disabled.
AP: Accept Physical Address from Multicast Filter Array. (R/W)
1: Allow unicast packets to be forwarded up toward host if the lookup of scrambling result of DA is found within
multicast address list.
0: Disabled, that is, unicast packets filtering are done without regarding multicast address list (default).
SO: Start Operation. (R/W)
1: Ethernet MAC start operating.
0: Ethernet MAC stop operating (default).
Drop_CRCE_n: Drop CRC field (FCS:4-byte) of RX packet(R/W)
1: Don’t drop CRC field.
0: Drop CRC field (default).
IPE_n: IP alignmemt enable(R/W)
1: IP alignmemt enable (default).
0: IP alignmemt not enable.
TX_CRC_Pad_n: Padding CRC field in TX packet (R/W)
1: No padding CRC field in TX packet.
0: Padding CRC field in TX packet (default).
37
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.2.7
Bit7
Node ID Register (NIDR, 10h~15h)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
AA [7:0]
BB [7:0]
CC [7:0]
DD [7:0]
EE [7:0]
FF [7:0]
AA [7:0] = Node ID 0. (R/W)
BB [7:0] = Node ID 1. (R/W)
CC [7:0] = Node ID 2. (R/W)
DD [7:0] = Node ID 3. (R/W)
EE [7:0] = Node ID 4. (R/W)
FF [7:0] = Node ID 5. (R/W)
{FF [7:0], EE [7:0], DD [7:0], CC [7:0], BB [7:0], AA [7:0]} = Ethernet MAC address [47:0] of AX88179.
6.2.2.8
Bit7
Multicast Filter Array (16h~1Dh, R/W)
Bit6
Bit5
Bit4
Bit3
MA0 [7:0]
MA1 [7:0]
MA2 [7:0]
MA3 [7:0]
MA4 [7:0]
MA5 [7:0]
MA6 [7:0]
MA7 [7:0]
Bit2
Bit1
Bit0
The {MA7 [7:0], MA6 [7:0], MA5 [7:0], MA4 [7:0], MA3 [7:0], MA2 [7:0], MA1 [7:0], MA0 [7:0]} equal to the
multicast address bit map for multicast frame filtering block. For example, see below Figure 5.
DA
81 81 81 81 81 81
CRC32
{crc31, 30, 29, 28, 27, 26}
Address [5:0] = 1Ah
MAR [63:0] =
400_0000h
Figure 5
: Multicast Filter Example
38
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
As shown in below figure, the Multicast Filter Array (MFA) provides filtering of multicast addresses hashed through the
CRC logic. All Destination Address field are fed through the 32 bits CRC generation logic. As the last bit of the Destination
Address field enters the CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by
a 1 to 64 decoder to index a unique filter bit (FB0-63) in the Multicast Filter Array. If the filter bit selected is set, the
multicast packet is accepted. The system designer should use a program to determine which filter bits to set in the multicast
registers. All multicast filter bits that correspond to Multicast Filter Array Registers accepted by the node are then set to one.
To accept all multicast packets all of the registers are set to all ones. Note that received Pause Frames are always filtered by
Ethernet MAC regardless of MFA setting.
48 bits DA field
(DA [40] = 1 indicating a multicast DA)
32-bit CRC Generator
CRC [31:26]
1 to 64-bit decoder
Index to MFA
Multicast Filter Array
Selected bit:
0: Reject the multicast packet
1: Accept the multicast packet
Figure 6
: Multicast Filter Array Hashing Algorithm
Example: If the accepted multicast packet’s destination address Y is found to hash to the value 32 (0x20), then FB32 in
MA4 should be initialized to “1”. This will allow the Ethernet MAC to accept any multicast packet with the destination
address Y. Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter
up to 64 logical address filters if these addresses are chosen to map into unique locations in the multicast filter. Note: The
LSB bit of received packet’s first byte being “1” signifies a Multicast Address.
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
D7
FB7
FB15
FB23
FB31
FB39
FB47
FB55
FB63
D6
FB6
FB14
FB22
FB30
FB38
FB46
FB54
FB62
D5
FB5
FB13
FB21
FB29
FB37
FB45
FB53
FB61
Figure 7
D4
FB4
FB12
FB20
FB28
FB36
FB44
FB52
FB60
D3
FB3
FB11
FB19
FB27
FB35
FB43
FB51
FB59
D2
FB2
FB10
FB18
FB26
FB34
FB42
FB50
FB58
D1
FB1
FB9
FB17
FB25
FB33
FB41
FB49
FB57
D0
FB0
FB8
FB16
FB24
FB32
FB40
FB48
FB56
: Multicast Filter Array Bit Mapping
39
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Following is the truth table about multicast packet filtering condition.
PRO bit AMALL bit AM bit Pass Hashing Algorithm
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0/1
0/1
1
0/1
0/1
0/1
Multicast Packet Filtered by Ethernet MAC
Yes
Yes
Yes
No
No
No
Note: Passing Hashing Algorithm means that the selected bit in MFA of CRC-32 result is set to “1”.
6.2.2.9
Bit7
GPIO_E4
Driving Stregth Control Register (DSCR, 20h~21h, R/W)
Bit6
GPIO_E8
Bit5
MFA_E4
Bit4
Bit3
MFA_E8
Reserved
Bit2
2’b00
Bit1
CK25M_E2
Bit0
CK25M_E4
Bit1
FD
PS
Bit0
GM
RE
{GPIO_E8, GPIO_E4}: Driving length of GPIO_0~3.
‘00’: 4mA, ‘01’: 8mA (default), ‘10’: 12mA, ‘11’: 16mA
{MFA_E8, MFA_E4}: Driving length of MFA_0~3.
‘00’: 4mA, ‘01’: 8mA (default), ‘10’: 12mA, ‘11’: 16mA
{CK25M_E4, CK25M_E2}: Driving length of CK25_OUT.
‘11’: 8mA. (default)
Others: Reserved.
6.2.2.10
Medium Status Register (MSR, 22h~23h, R/W)
Bit7
PF
0
Bit6
JFE
0
Bit5
TFC
0
Bit4
RFC
SM
Bit3
0
SBP
Bit2
1
Reserved
AA [7:0] = {PF, JFE, TFC, RFC, 0, 1, FD, 0}.
BB [7:0] = {3’b0, SM, SBP, Reserved, PS, RE}.
GM: Gigabit Mode.
1: GMII mode (default).
0: MII mode.
FD: Full Duplex mode
1: Full Duplex mode (default).
0: Half Duplex mode.
RFC: RX Flow Control enables.
1: Enable receiving of pause frame on RX direction during full duplex mode (default).
0: Disabled.
TFC: TX Flow Control enables.
1: Enable transmitting pause frame on TX direction during full duplex mode (default).
0: Disabled.
40
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
JFE: Jumbo Frame Enable.
1: Enable to support 4KB Jumbo frame in Gigabit mode (default).
0: Disabled.
PF: Check only “length/type” field for Pause Frame.
1: Enable. Pause frames are identified only based on L/T filed.
0: Disabled. Pause frames are identified based on both DA and L/T fields (default).
RE: Receive Enable.
1: Enable RX path of the ASIC.
0: Disabled (default).
PS: Port Speed in MII mode
1: 100 Mbps (default).
0: 10 Mbps.
SBP: Stop Backpressure.
1: When TFC bit = 1, setting this bit enables backpressure on TX direction “continuously” during RX buffer full
condition in half duplex mode.
0: When TFC bit = 1, setting this bit enable backpressure on TX direction “intermittently” during RX buffer full
condition in half duplex mode (default).
SM: Super Mac support.
1: Enable Super Mac to shorten exponential back-off time during transmission retrying.
0: Disabled (default).
6.2.2.11
Bit7
PME_IND
Monitor Mode Status Register (MMSR, 24h, R/W)
Bit6
PME_TYPE
Bit5
PME_POL
Bit4
RW_FLAG
Bit3
RWWF
Bit2
RWMP
Bit1
RWLC
RWLC: Remote Wakeup riggered by Ethernet Link-change event.
1: Enabled (default).
0: Disabled.
RWMP: Remote Wakeup riggered by Magic Packet event.
1: Enabled (default).
0: Disabled.
RWWF: Remote Wakeup riggered by WakeUp Frame event.
1: Enabled.
0: Disabled (default).
RW_FLAG: Remote Wakeup Enable. It equals EEPROM/RWU-flag AND (logic) Set-Feature (RWU).
1: Enable.
0: Disabled.
PME_POL: PME Polarity.
1: PME active high.
41
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Bit0
0
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
0: PME active Low (default).
PME_TYP: PME I/O Type.
1: PME output is a Push-Pull driver.
0: PME output to function as an open-drain buffer.
PME_IND: PME indication.
1: A 1.32ms pulse active when detect a wake-up event.
0: A static signal active when detect wake-up event (default).
6.2.2.12
Bit7
GPO_3_EN
GPIO Status Register (25h, Read)
Bit6
GPO_2_EN
Bit5
GPO_1_EN
Bit4
GPO_0_EN
Bit3
GPI_3
Bit2
GPI_2
Bit1
GPI_1
Bit0
GPI_0 (PME)
GPO_n_EN: Output enable of GPIO_n. n=0, 1, 2, 3.
1: Output.
0: Input.
GPI_n: Input level on GPIO_n pin when GPIO_n is an input pin. N=0, 1, 2, 3.
Note：If 70h.PME_PIN set to ‘0’, GPI_0 can be indicated as input level on GPIO_0 pin.
If 70h.PME_PIN set to ‘1’, GPI_0 can be indicated as PME output signal value.
6.2.2.13
Bit7
GPO3EN
GPIO Control Register (25h, Write)
Bit6
GPO2EN
Bit5
GPO1EN
Bit4
GPO0EN
Bit3
GPO_3
Bit2
GPO_2
Bit1
GPO_1
GPOnEN: Pin GPIO_n Output Enable. N=0, 1, 2, 3.
1: Output is enabled (meaning GPIO_n is used as an output pin).
0: Output is tri-stated (meaning GPIO_n is used as an input pin) (default).
GPO_n: Pin GPIO_n Output Value. Default value is ‘0’. N=0, 1, 2, 3.
42
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Bit0
GPO_0
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.2.14
Ethernet PHY Power and Reset Control Register (EPPRCR, 26h~27h, R/W)
Bit7
Bit6
Reserved
0
WOLLP
Bit5
Reserved
Bit4
BZ
AutoDetach
Bit3
0
Bit2
Bit1
BZ_TYP
0
Reserved
Bit0
0
BZ_TYP: The type of BZ bit. Define BZ bit whether it can auto-clear itself.
1: Disable that BZ auto-clears itself when it force hardware return a Zero-length packet (default).
0: Auto-clears BZ when it forces hardware return a Zero-length packet.
BZ: Force Bulk IN to return a Zero-length packet.
1: Software can force Bulk IN to return a zero-length USB packet.
0: Normal operation mode (default).
AutoDetach: Enable AutoDetach function with USB controller.
1: Enable.
0: Disable. It keeps chip attached When Ethernet cable unplug (default).
WOLLP: Enter WOL Low Power function in Suspend mode.
1: Force Internal Ethernet PHY into lowest speed after entering Suspend mode. This bit only effect if both PHYs are in
auto-negotiation mode with 10/100/1000M capacities.
0: Non-force Internal Ethernet PHY (default).
6.2.2.15
Bit7
Jam Limit Count Register (JLCR, 29h, R/W)
Bit6
Bit5
Bit4
Bit3
Bit2
Jam_Limit [5:0]
0
Bit1
Bit0
Jam_Limit [5:0]: This is used for flow-control in half-duplex mode, which is based on forced collision mechanisms to
backpressure transmitting network node. During the forced collision backpressure process, the Ethernet MAC will
continue counting total collision count. When it has reached the Jam_Limit setting, the Ethernet MAC will stop
backpressure to avoid Ethernet HUB from being partitioned (default = 3Fh) due to excessive collision on network link.
Bit 7, 6: Please always write 0 to these bits.
43
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.2.16
VLAN Control Register (VCR, 2Ah~2Dh, Write)
Bit7
Bit6
Bit5
Reserved
VFE
Bit4
Bit3
VID1 [7:0]
VSO
VID2 [7:0]
Reserved
Bit2
Bit1
Bit0
VID1 [11:8]
VID2 [11:8]
AA [7:0] = {VID1 [7:0]}.
BB [7:0] = {Reserved, VFE, VSO, VID1 [11:8]}.
CC [7:0] = {VID2 [7:0]}.
DD [7:0] = {Reserved, VID2 [11:8]}.
VID1 [11:0]: First VLAN ID for filter.
VSO: VLAN Strip off
1: Strip off VLAN Tag (4 bytes) from the incoming packet.
0: Preserve VLAN Tag in the incoming packet (default).
VFE: VLAN filter enable
1: Enable VLAN filter. The VLAN ID field (12 bits) received 802.1q tagged packets, as in the Figure 26 below, which
will be used to compare with VID1 and VID2 setting. If it matches either VID1 or VID2, or its value is equal to all
zeros, the received 802.1q tagged packets will be forwarded to the USB Host. Meanwhile, the VSO bit determines
whether the VLAN Tag bytes (4 bytes) are stripped off or not during forwarding to the USB Host. Also, if the
incoming packets contain no VLAN Tag bytes, they will be forwarded to the USB Host by default. If there is no
match between the received 802.1q tagged packets and VID1 and VID2, the packets will be discarded. Please see
below table.
Received packet
VID1, VID2
Zero
Not zero
Table 11
Untagged
Tagged
Forwarded
VID=Zero
Forwarded
VID= Not zero
Discarded
Forwarded
Forwarded
Match: Forwarded
No Match: Discarded
: VID1, VID2 setting to filter received packet
0: Disable VLAN filter. The received packets with or without 802.1q Tag bytes will always be forwarded to the USB
Host (default).
VID2 [11:0]: Second VLAN ID for filter. Note that VID1 and VID2 function as two independent VLAN ID filters.
44
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Note that to send the packet with VLANID Tag bytes; the software should append VLAN Tag bytes in the transmitted
packets.
802.1Q
VLAN tagging
7 Bytes
Layer 2
1 Byte
Preamble
SFD
6 Bytes
Destination
Address
6 Bytes
Source
Address
2B
2B
2B
8100
TCI
L/T
Frame (64-1518 Bytes)
VLAN (64-1522 Bytes)
Figure 8
6.2.2.17
46-1500 Bytes
4 Bytes
Data
3 bits
1 bit
12 bits
Priority
CFI
VLAN ID
Pad
FCS
: 802.1q VLAN Packet Format
VLAN Control Register (VCR, 2Ah~2Dh, Read)
Bit7
Bit6
Reserved
Bit5
Bit4
VSO
VFE
Bit3
VID1 [7:0]
Bit2
Bit1
VID1 [11:8]
VID2 [7:0]
Reserved
VID2 [11:8]
AA [7:0] = {VID1 [7:0]}.
BB [7:0] = {Reserved, VSO, VFE, VID1 [11:8]}.
CC [7:0] = {VID2 [7:0]}.
DD [7:0] = {Reserved, VID2 [11:8]}.
Their descriptions are same as Section 6.2.2.16.
45
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Bit0
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.2.18
Bit7
ICMPv6
COE RX Control Register (CRCR, 34h, R/W)
Bit6
UDPv6
Bit5
TCPv6
Bit4
IGMP
Bit3
ICMP
Bit2
UDP
IP: Enable Ipv4 checksum check.
1: Enable IP packet checksum check.
0: Disable IP packet checksum check
TCP: Enable TCP packet checksum check in RX path.
1: Enable the TCP packet checksum check function.
0: Disable the TCP packet checksum check function.
UDP: Enable UDP packet checksum check in RX path.
1: Enable the UDP packet checksum check function.
0: Disable the UDP packet checksum check function.
ICMP: Enable ICMP packet checksum check in RX path.
1: Enable the ICMP packet checksum check function.
0: Disable the ICMP packet checksum check function.
IGMP: Enable IGMP packet checksum check in RX path.
1: Enable the IGMP packet checksum check function.
0: Disable the IGMP packet checksum check function.
TCPv6: Enable TCP packet checksum check in RX path for Ipv6 packet.
1: Enable the TCP packet checksum check function for Ipv6 packet.
0: Disable the TCP packet checksum check function for Ipv6 packet.
UDPv6: Enable UDP packet checksum check in RX path for Ipv6 packet.
1: Enable the UDP packet checksum check function for Ipv6 packet.
0: Disable the UDP packet checksum check function for Ipv6 packet.
ICMPv6: Enable ICMPv6 packet checksum check in RX path for Ipv6 packet.
1: Enable the ICMPv6 packet checksum check function for Ipv6 packet.
0: Disable the ICMPv6 packet checksum check function for Ipv6 packet.
46
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Bit1
TCP
Bit0
IP
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.2.19
Bit7
ICMPv6
COE TX Control Register (CTCR, 35h, R/W)
Bit6
UDPv6
Bit5
TCPv6
Bit4
IGMP
Bit3
ICMP
Bit2
UDP
IP: Enable Ipv4 checksum insertion function.
1: Enable Ipv4 packet checksum insertion function.
0: Disable Ipv4 packet checksum insertion function.
TCP: Enable TCP checksum insertion function.
1: Enable TCP packet checksum insertion function.
0: Disable TCP packet checksum insertion function.
UDP: Enable UDP checksum insertion function.
1: Enable UDP packet checksum insertion function.
0: Disable UDP packet checksum insertion function.
ICMP: Enable ICMP checksum insertion function.
1: Enable ICMP packet checksum insertion function.
0: Disable ICMP packet checksum insertion function.
IGMP: Enable IGMP checksum insertion function.
1: Enable IGMP packet checksum insertion function.
0: Disable IGMP packet checksum insertion function.
TCPv6: Enable TCP checksum insertion function for Ipv6 packet.
1: Enable TCP packet checksum insertion function for Ipv6 packet.
0: Disable TCP packet checksum insertion function for Ipv6 packet.
UDPv6: Enable UDP checksum insertion function for Ipv6 packet.
1: Enable UDP packet checksum insertion function for Ipv6 packet.
0: Disable UDP packet checksum insertion function for Ipv6 packet.
ICMPv6: Enable ICMPv6 checksum insertion function for Ipv6 packet.
1: Enable ICMPv6 packet checksum insertion function for Ipv6 packet.
0: Disable ICMPv6 packet checksum insertion function for Ipv6 packet.
47
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Bit1
TCP
Bit0
IP
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.2.20
COE PPPoE Control Register (CPCR, 36h, R/W)
Bit7
Bit6
Bit5
Bit4
Reserved
Bit3
Bit2
Bit1
TX
Bit0
RX
RX: L2 parser support PPPoE encapsulated packet in RX path.
0: COE doesn’t support PPPoE encapsulated packet in RX path.
1: COE support PPPoE encapsulated packet in RX path.
TX: L2 parser support PPPoE encapsulated packet in TX path.
0: COE doesn’t support PPPoE encapsulated packet in TX path.
1: COE support PPPoE encapsulated packet in TX path.
6.2.2.21
Bit7
Reserved
Pause Water Level HIGH Register (PWLHR, 54h)
Bit6
Bit5
Bit4
Bit3
AA [7:0]
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
Bit2
Bit1
MFA_EN
Bit0
PME_PIN
AA [6:0]: High water level for flow control. Default value is 7’h42 (R/W)
Note that unit is 128bytes.
AA [7]: Reserved
6.2.2.22
Bit7
Reserved
Pause Water Level LOW Register (PWLLR, 55h)
Bit6
Bit5
Bit4
Bit3
AA [7:0]
AA [6:0]: Low water level for flow control. Default value is 7’h24 (R/W)
Note that unit is 128bytes.
AA [7]: Reserved
6.2.2.23
Bit7
PIN Control Register (PINCR, 70h)
Bit6
Bit5
Bit4
Bit3
Reserved
PME_PIN: GPIO_0 is PME PIN. (R/W)
0: GPIO_0 operates as GPIO.
1: GPIO_0 is PME PIN (default).
MFA_EN: Enable MFA function as GPIO. (R/W)
0: MFA pins operate as LED indication (default).
1: MFA pins operate as GPIO function.
48
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.2.3 Wakeup Frame Command Structure
Offset (byte)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Name
expect_CRC_0_L
expect_CRC_0_H
expect_CRC_1_L
expect_CRC_1_H
expect_CRC_2_L
expect_CRC_2_H
expect_CRC_3_L
expect_CRC_3_H
expect_CRC_4_L
expect_CRC_4_H
expect_CRC_5_L
expect_CRC_5_H
expect_CRC_6_L
expect_CRC_6_H
expect_CRC_7_L
expect_CRC_7_H
last_byte_0
last_byte_1
last_byte_2
last_byte_3
last_byte_4
last_byte_5
last_byte_6
last_byte_7
{command_1, command_0}
{command_3, command_2}
{command_5, command_4}
{command_7, command_6}
Mask_MEM_Offset
{4’d0, Mask_timer}
Mask_valid_length_0
Mask_valid_length_1
Mask_valid_length_2
Mask_valid_length_3
Mask_valid_length_4
Mask_valid_length_5
Mask_valid_length_6
Mask_valid_length_7
reply_TX_page_0
reply_TX_page_1
reply_TX_page_2
reply_TX_page_3
reply_TX_page_4
reply_TX_page_5
reply_TX_page_6
reply_TX_page_7
partial_chksum_0_L
partial_chksum_0_H
partial_chksum_1_L
partial_chksum_1_H
Description
The low byte of wakeup frame 0 CRC
The high byte of wakeup frame 0 CRC
The low byte of wakeup frame 1 CRC
The high byte of wakeup frame 1 CRC
The low byte of wakeup frame 2 CRC
The high byte of wakeup frame 2 CRC
The low byte of wakeup frame 3 CRC
The high byte of wakeup frame 3 CRC
The low byte of wakeup frame 4 CRC
The high byte of wakeup frame 4 CRC
The low byte of wakeup frame 5 CRC
The high byte of wakeup frame 5 CRC
The low byte of wakeup frame 6 CRC
The high byte of wakeup frame 6 CRC
The low byte of wakeup frame 7 CRC
The high byte of wakeup frame 7 CRC
The last masked byte of the wakeup frame 0
The last masked byte of the wakeup frame 1
The last masked byte of the wakeup frame 2
The last masked byte of the wakeup frame 3
The last masked byte of the wakeup frame 4
The last masked byte of the wakeup frame 5
The last masked byte of the wakeup frame 6
The last masked byte of the wakeup frame 7
Wakeup frame command 0 & 1
Wakeup frame command 2 & 3
Wakeup frame command 4 & 5
Wakeup frame command 6 & 7
Fix to 0x04
Mask wakeup event trigger to USB host timer
The valid length of the byte mask 0
The valid length of the byte mask 1
The valid length of the byte mask 2
The valid length of the byte mask 3
The valid length of the byte mask 4
The valid length of the byte mask 5
The valid length of the byte mask 6
The valid length of the byte mask 7
The TX buffer page for reply packet 0
The TX buffer page for reply packet 1
The TX buffer page for reply packet 2
The TX buffer page for reply packet 3
The TX buffer page for reply packet 4
The TX buffer page for reply packet 5
The TX buffer page for reply packet 6
The TX buffer page for reply packet 7
The low byte of calculated partial checksum of Ipv6 NA
The high byte of calculated partial checksum of Ipv6 NA
The low byte of calculated partial checksum of Ipv6 NA
The high byte of calculated partial checksum of Ipv6 NA
49
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Wakeup Frame 0~7 CRC: Each one has 16 bits.
Based on desired wakeup frame patterns, software should calculate CRC-16 and set it here. The value is used to compare
with the CRC-16 calculated on the incoming frame on the bytes defined by Byte Mask 0~7. When matched and the Last
Byte 0~7 is also matched, then the frame is considered as a valid wakeup frame.
CRC-16 Polynomial = X^16 + X^15 + X^2 + 1.
If wakeup frame filters are cascaded, the Wakeup Frame CRC must be cumulatively calculated. The last CRC value is
used for verification.
Last Byte 0~7: Each one has 8 bits.
This 1-byte pattern is used to compare the last masked byte in the incoming frame. The last masked byte is the byte of the
last bit mask being 1 in Byte Mask 0~7. A valid wakeup frame shall have match condition on both Wakeup Frame 0~7
CRC and Last Byte 0~7. If wake-up frame filters are cascaded, the Last Byte for the last cascaded wake-up frame filter is
used to verify correctness.
Command 0~7: Each one has 4 bits.
Bit 0: Individual Byte Mask for Byte Mask 0~7.
1: Enable.
0: Disable.
Bit 3: Auto reply function when suspended.
1: Enable.
0: Disable.
Mask Wakeup Timer: Control wakeup event triggering time for some Host system taking
a long time to enter suspend state.
Bit [3:0]: 28s, 24s, 20s, 16s, 12s, 8s, 4s, 0s
Bit [3:0]
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Mask Time
0
4
8
12
16
20
24
28
Unit
Second
Second
Second
Second
Second
Second
Second
Second
50
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Mask_valid_length:
It’s the valid length of byte mask 0~7.
Reply TX Page:
Bit 4~0: The power management offload auto reply packet was stored in different page of TX buffer SRAM.
Bit 6~5: Reply type.
00: Orginal packet in TX buffer.
01: Neighbor advertisement (partial checksum 0).
10: Neighbor advertisement (partial checksum 1).
11: ARP.
Partial checksum: Calculated partial checksum of neighbor advertisement packet.
51
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.3 Interrupt Endpoint
The Interrupt Endpoint contains 8 bytes of data and its frame format is defined as: A1AA_BBCC_DDEE_FFGG.
Where A1 byte in byte 1: A1 is a fixed value.
Where AA byte in byte 2:
Bit7
Bit6
0
0
Bit5
0
Bit4
0
Bit3
0
Bit2
0
Bit1
0
Bit0
0
Where BB byte in byte 3:
Bit7
Bit6
0
0
Bit5
0
Bit4
0
Bit3
1
Bit2
0
Bit1
0
Bit0
PPLS
PPLS: Internal PHY Link State. It shows the link status of internal PHY.
1: Link is up.
0: Link is down.
Where CC byte in byte 4:
Bit7
Bit6
0
0
Bit5
0
Bit4
0
Bit3
0
Bit2
0
Bit1
0
Bit0
0
Where DD byte in byte 5:
Bit7
Bit6
Bit5
Bit4
Bit3
MR01 Low Byte
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
Bit2
Bit1
Bit0
This byte is the low byte of PHY’s register MR01 (address 01h).
Where EE byte in byte 6:
Bit7
Bit6
Bit5
Bit4
Bit3
MR01 High Byte
This byte is the high byte of PHY’s register MR01 (address 01h).
Where FF byte in byte 7:
Bit7
Bit6
Bit5
Bit4
Bit3
MR05 Low Byte
This byte is the low byte of PHY’s register MR05 (address 05h).
Where GG byte in byte 8:
Bit7
Bit6
Bit5
Bit4
Bit3
MR05 High Byte
This byte is the high byte of PHY’s register MR05 (address 05h).
52
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
7 Electrical Specifications
7.1 DC Characteristics
7.1.1 Absolute Maximum Ratings
Symbol
VCCK
VCC12A_TX
VCC12A_RX
VCC12A_X
VCC12A
VCC3IO
VCC33IO
VCC33A
VCC33A_X
VCC33A_G
VIN3
TSTG
IIN
IOUT
Parameter
Digital core power supply
Analog Power for USB Transceiver. 1.2V
Analog Power for USB Transceiver. 1.2V
Analog Power for Ethernet PHY. 1.2V
Analog Power for Ethernet PHY.1.2V
Power supply of 3.3V I/O
Power supply of 3.3V for clock pin.
Analog Power 3.3V for USB Transceiver.
Analog Power for Ethernet PHY. 3.3V
Analog Power for Ethernet PHY. 3.3V
Input voltage of 3.3V I/O
Input voltage of 3.3V I/O with 5V tolerant
Storage temperature
DC input current
Output short circuit current
Rating
- 0.5 to 1.44
- 0.5 to 1.6
- 0.5 to 1.6
- 0.1 to 1.26
- 0.1 to 1.26
- 0.5 to 4.2
- 0.5 to 4.6
- 0.5 to 4.6
- 0.4 to 3.7
- 0.4 to 3.7
- 0.5 to 4.2
- 0.5 to 5.8
- 65 to 150
50
50
Unit
V
V
V
V
V
V
V
V
V
V
V
V
℃
mA
mA
Note: 1.Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be
restricted to the optional sections of this datasheet. Exposure to absolute maximum rating condition for extended
periods may affect device reliability.
2. The input and output negative voltage ratings may be exceeded if the input and output currents under ratings are
observed.
7.1.2 Recommended Operating Condition
Symbol
VCCK
VCC12A_TX
VCC12A_RX
VCC12A_X
VCC12A
VCC3IO
VCC33IO
VCC33A
VCC33A_X
VCC33A_G
VIN3
Tj
Ta
Parameter
Digital core power supply
Analog Power for USB Transceiver. 1.2V
Analog Power for USB Transceiver. 1.2V
Analog Power for Ethernet PHY. 1.2V
Analog Power for Ethernet PHY.1.2V
Power supply of 3.3V I/O
Power supply of 3.3V for clock pin.
Analog Power 3.3V for USB Transceiver.
Analog Power for Ethernet PHY. 3.3V
Analog Power for Ethernet PHY. 3.3V
Input voltage of 3.3 V I/O
Input voltage of 3.3 V I/O with 5V tolerance
Commercial junction operating temperature
Commercial operating temperature
Min
1.14
1.14
1.14
1.14
1.14
3.15
3.15
3.15
2.97
2.97
3.15
3.15
-40
0
Typ
1.2
1.2
1.2
1.2
1.2
3.3
3.3
3.3
3.3
3.3
3.3
3.3
25
-
Max
1.26
1.26
1.26
1.26
1.26
3.45
3.45
3.45
3.63
3.63
3.45
5.25
125
70
53
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
℃
℃
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
7.1.3 Leakage Current and Capacitance
Symbol
IIN
Parameter
True 3.3 V I/O input leakage
current
Conditions
Vin = 3.3 V or 0 V
Min
-
Typ
≤±1
Max
-
Unit
μA
3.3 V with 5 V tolerance I/O
Vin = 5 V or 0 V
-
<±1
-
pF
3.3V I/O cells
-
2.25
-
pF
3.3V with 5V tolerant I/O 3.6
cells
Note: CIN includes the cell layout capacitance and pad capacitance (Estimated to be 0.5 pF).
pF
Input leakage current
CIN
Input capacitance
7.1.4 DC Characteristics of 3.3V I/O Pins
Symbol
Vil
Vih
VtVt+
Vol
Voh
Vopu[1]
[1]
Parameter
Input low voltage
Input high voltage
Schmitt trigger negative
threshold voltage
Schmitt trigger positive
threshold voltage
Output low voltage
Output high voltage
Conditions
LVTTL
going LVTTL
going
|Iol| = 4~8mA
|Ioh| = 4~8mA
Output pull-up voltage for 5 V PU = High, PD =
tolerance I/O cells
Low E = 0, |Ipu| = 1
μA
Min
2.0
0.8
Typ
1.1
Max
0.8
-
Unit
V
V
V
-
1.6
2.0
V
2.4
-
0.4
-
VCC3IO –
0.9
V
V
V
-
-
Rpu
Input pull-up resistance
PU = High, PD =
Low
40
75
190
KΩ
Rpd
Input pull-down resistance
PU = Low, PD =
High
40
75
190
KΩ
This parameter indicates that the pull-up resistor for the 5 V tolerance I/O cells cannot reach the VCC3IO DC level even
without the DC loading current.
7.2 Thermal Characteristics
Description
Thermal resistance of junction to case
Thermal resistance of junction to ambient
Note:
Symbol
Θ JC
Θ JA
Rating
8.3
21.4
 JA ,  JC defined as below
 JA
=
TJ  T A
T  TC
,  JC = J
P
P
TJ: maximum junction temperature (°C)
TA: ambient or environment temperature (°C)
TC: the top center of compound surface temperature (°C) P: input power (watts)
54
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Units
°C/W
°C/W
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
7.3 Power Consumption
Symbol
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IVCC12
IVCC33
IDEVICE
ISYSTEM
ISYSTEM
(Suspend)
Description
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Current Consumption of 1.2V
Current Consumption of 3.3V
Conditions
Operating at Ethernet 1GMbps(full duplex) mode and
USB Super Speed mode
Operating at Ethernet 100Mbps full duplex mode and
USB Super Speed mode
Operating at Ethernet 10Mbps half duplex mode and
USB Super Speed mode
Operating at Ethernet 1GMbps(full duplex) mode and
USB High Speed mode
Operating at Ethernet 100Mbps full duplex mode and
USB High Speed mode
Operating at Ethernet 10Mbps half duplex mode and
USB High Speed mode
Operating at Ethernet 1GMbps(full duplex) mode and
USB Full Speed mode
Operating at Ethernet 100Mbps full duplex mode and
USB Full Speed mode
Operating at Ethernet 10Mbps half duplex mode and
USB Full Speed mode
Ethernet unlink (Disable AutoDetach) and
USB Super Speed mode
Ethernet unlink (Enable AutoDetach)
USB Suspend and Ethernet is 1Gbps:
enable Remote WakeUp and disable
WOLLP (WOL Low Power) (Refer to Section 6.2.2.14)
Current Consumption of 1.2V USB Suspend and enable Remote WakeUp and enable
Current Consumption of 3.3V WOLLP to 10Mbps (Refer to Section 6.2.2.10)
Current Consumption of 1.2V Suspend and disable Remote WakeUp
Current Consumption of 3.3V (Refer to below ISYSTEM (Suspend) item
for total power consumption at Suspend mode)
IDLE Power Consumption For Etherent Linked in EEE /non-EEE
Current Consumption of 1.2V Operating at Ethernet 1GMbps mode and
Current Consumption of 3.3V USB Super Speed mode (Ethernet linked in EEE)
Current Consumption of 1.2V Operating at Ethernet 1GMbps mode and
Current Consumption of 3.3V USB Super Speed mode (Ethernet linked in non-EEE)
Current Consumption of 1.2V USB Suspend and enable Remote WakeUp
Current Consumption of 3.3V (Ethernet linked in EEE 1GMbps mode)
Green Etherent Cable-Length Power Saving (GEPS)
Current Consumption of 1.2V Operating at Ethernet 1GMbps mode @ 1.5 meters and
Current Consumption of 3.3V USB Super Speed mode (Enable GEPS)
Current Consumption of 1.2V Operating at Ethernet 1GMbps mode @ 1.5 meters and
Current Consumption of 3.3V USB Super Speed mode (Disable GEPS)
1.2V/3.3V power consumption
1.2V (Operating at Super Speed/1GMbps mode)
at full loading (chip only)
3.3V (Operating at Super Speed/1GMbps mode)
Total power consumption
VBUS of 5.0V (Operating at Super Speed/1GMbps mode)
at full loading (demo board)
(Using Switching regulator with dual VOUT 3.3/1.2V)
Total power consumption
VBUS of 5.0V (Disable Remote WakeUp)
at Suspend mode (demo board) (Using Switching regulator with dual VOUT 3.3/1.2V)
Table 12
: Power consumption
55
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Min Typ Max Unit
335
mA
67
mA
189
mA
41
mA
151
mA
48
mA
228
mA
79
mA
85
mA
50
mA
48
mA
53
mA
216
mA
63
mA
77
mA
40
mA
42
mA
46
mA
151
mA
29
mA
23
mA
12
mA
200
mA
47
mA
-
25
13
1.5 1.7 -
mA
mA
mA
mA
177
32
320
66
56
0.4
mA
mA
mA
mA
mA
mA
320
66
328
69
335
67
161
mA
mA
mA
mA
mA
mA
mA
1.92
mA
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
7.4 Power-up Sequence
At power-up, the AX88179 requires the VCC33A/VCC33IO/VCC3IO/VCC33A_X/VCC33A_G power supply to
rise to nominal operating voltage within Trise3 and the VCC12 (Note) power supply to rise to nominal operating
voltage within Trise2.
Trise3
3.3V
VCC33A/VCC33IO/VCC3IO/
VCC33A_X/VCC33A_G
0V
Tdelay32
Trise2
1.2V
VCC12
0V
Trst_pu
RESET_N
Tclk
XTL25P/ XTL25N
Note: The VCC12 includes VCCK, VCC12A, and VCC12A_X/TX/RX.
Symbol
Trise3
Trise2
Tdelay32
Tclk
Trst_pu
*1 :
Parameter
3.3V power supply rise time
1.2V power supply rise time
3.3V rise to 1.2V rise time delay
25MHz crystal oscillator stable
time
RESET_N low level interval
time from power-up
Condition
From 0V to 3.3V
From 0V to 1.2V
From VCC3IO = 3.3V to stable clock
period of XTA25P or XTAL25N
From VCC12 = 1.2V and VCC3IO =
3.3V to RESET_N going high
Min
-5
-
Typ
1
Max
10
10
5
-
Unit
ms
ms
ms
ms
Tclk +
-
-
ms
Trst
*1
Please refer to Section 7.5.2 Reset Timing for the details about the Trst.
56
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
7.5 AC Timing Characteristics
Notice that the following AC timing specifications for output pins are based on CL (Output load)
equal to 50pF.
7.5.1 Clock Timing
XTL25P
TP_XTL25P
TH_XTL25P
TL_XTL25P
VIH
VIL
Symbol
TP_XTL25P
TH_XTL25P
TL_XTL25P
Parameter
XTL25P clock cycle time
XTL25P clock high time
XTL25P clock low time
Condition
Min
-
Typ
40.0
20.0
20.0
Max
-
Unit
ns
ns
ns
7.5.2 Reset Timing
XTL25P
RESET_N
Trst
Symbol
Description
Trst Reset pulse width after XTL25P is running
Min
125
Typ
-
Max
250000
Unit
XTL25P clock cycle (Note)
Note: If the system applications require using hardware reset pin, RESET_N, to reset AX88179 during device initialization
or normal operation after VBUS pin is asserted, the above timing spec (Min=5 μ s, Max=10ms) of RESET_N should
be met.
57
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
7.5.3 Serial EEPROM Timing
T ch
T cl
T clk
EECK
T dv
T od
EEDIO (as OUT PUT)
T lcs
T scs
T hcs
EECS
Th
Ts
EEDIO (as INPUT )
Symbol
Tclk
Tch
Tcl
Tdv
Tod
Tscs
Thcs
Tlcs
Ts
Th
Description
EECK clock cycle time
EECK clock high time
EECK clock low time
EEDIO output valid to EECK rising edge time
EECK rising edge to EEDIO output delay time
EECS output valid to EECK rising edge time
EECK falling edge to EECS invalid time
Minimum EECS low time
EEDIO input setup time
EEDIO input hold time
Min
2560
2562
2560
7680
23039
20
0
Typ
5120
2560
2560
-
Max
-
58
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
8 Package Information
8.1 68-pin QFN 8x8 package
59
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
8.2 Recommended PCB Footprint for 68-pin QFN 8x8 package
Symbol
e
b
L
U
V
W
Description
Lead pitch
Pad width
Pad length
-
Typical Dimension
0.40 mm
0.23 mm
0.80 mm
6.30 mm
6.63 mm
7.20 mm
60
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
9
Ordering Information
Part Number
AX88179 QF
Description
68 PIN, QFN Package, Commercial Grade Temperature Range 0°C to
+70 °C (Green, Lead-Free)
61
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
10 Revision History
Revision
Date
Comment
V0.10
V0.20
V0.30
2011/11/30
2011/12/06
2011/12/08
V0.40
2012/01/03
V0.50
2012/02/23
V1.00
2012/04/17
V1.01
2012/07/18
V1.02
2012/08/07
Prelimiary release.
1. Modified some descriptions in Section 4.1.2, 4.2.1, 4.2.2.
1. Modified some descriptions in Section 3.11, 4.1.2, 4.2.
2. Added more information in Section 7.2.
3. Corrected some typos and modified some descriptions in Section
7.3, 9.
1. Modified some descriptions in Section 1.3, 3.9, 4, 4.2, 7.2.
2. Removed the USB Vendor Command
“4004_AA00_CC00_EE00” in Section 6.2.1.
3. Renamed the USB Vendor Command
“C004_AA00_CC00_EE00” to “Read Non-Volatile Setting
Register” in Section 6.2.1.
4. Added the EAR, EDLR, EDHR, ECR MAC registers definition
for EEPROM read/write operation in Section 6.2.2.
1. Modified some descriptions in Section 6.2.2.6.
2. Added Section 8.2 “Recommended PCB Footprint for 68-pin
QFN 8x8 package”.
1. Added the “eFuse Checksum” field definition in Table 5.
2. Changed EEPROM/eFuse LED mode fields definition in Table 4
and Table 5.
3. Modified some EEPROM descriptions in Section 3.9, 4, 4.1.6.
4. Removed Appendix B.
1. Modified some descriptions in Section 4.1.7, 6.1 and 7.3.
2. Modified some descriptions in APPENDIX A.
1. Added Section 7.2 “Thermal Characteristics”.
2. Modified some descriptions in Section 3.11, 3.12, 7.4, 7.5.
62
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
APPENDIX A. Default Wake-On-LAN (DWOL) Ready Mode
This Default WOL Ready Mode application is different from normal operation where AX88179 Suspend/Resume
state usually has to be configured by software driver during normal system operation. This application applies to a system
that needs to use a predefined remote wakeup event to turn on the power supply of the system processor and its peripheral
circuits without having any system software running in the beginning. This is quite useful when a system has been powered
down already and a user needs to power on the system from a remote location.
The AX88179 can be configured to support Default WOL Ready Mode, where no system driver is required to
configure its WOL related settings after power on reset. A system design usually partitions its power supply into two or
more groups and the AX88179 is supplied with an independent power separated from the system processor. The power
supply of AX88179 is usually available as soon as power plug is connected. The power supply of system processor remains
off initially when power plug is connected and is controlled by AX88179’s PME pin, which can be activated whenever
AX88179 detects a predefined wakeup event such as valid Magic Packet reception or the EXTWAKE_N pin trigger. To
conserve power consumption, initially the USB host controller communicating with AX88179 can also be unpowered as the
system processor.
The PME pin of AX88179 can control the power management IC to power up the system processor along with the
USB host controller, which will perform USB transactions with AX88179 after both have been initialized. The pin polarity
of PME is configured as high active when enabling Default WOL Ready Mode (see following A.1 Note 2). Note that the
AX88179 must be in self-power (via setting EEPROM Flag [0]) mode for this function.
A.1 Procedure to Enable Default WOL Ready Mode
63
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
To enable Default WOL Ready Mode, a user needs to configure GPIO_0 pin definition as PME (via setting EEPROM
Flag [12]) and have GPIO_1 pulled-up with a 4.7Kohm resistor. After power on reset, AX88179 will disable most functions
including USB transceiver (see Note 3) but enable Magic Packet detector logic and internal Ethernet PHY and its
auto-negotiation function to be ready to receive Magic Packet. When a valid Magic Packet is received, AX88179 will
assert the PME pin to indicate to system processor the wakeup event. The PME pin, when being configured as static level
output signal (via setting EEPROM Flag [15], see Note 2), can be used to control the power management IC to enable
system power supply. After asserting the PME pin, AX88179 will also exit from the Default WOL Ready Mode and revert
back to normal operation mode to start normal USB device detection, handshaking, and enumeration.
The PME pin, when being configured as static level output signal, maintains its signal level until RESET_N is asserted
again. If asserting RESET_N to AX88179 with GPIO_1 pulled-up, the Default WOL Ready Mode will be re-entered.
Otherwise (GPIO_1 being pulled-down), it will be entered normal operation mode and the normal USB device detection,
handshaking and enumeration process should take place right after RESET_N negation.
Note 1: For complete truth table of wakeup events supported, please refer to below Remote Wakeup Truth Table on the
“GPIO_1 = 1” setting.
Note 2: Please refer to Section 4.1.2 “Flag”. The bit [15:12] of Flag (PME_IND, PME_TYP, PME_POL, PME_PIN) =
0111.
Note 3: When the Default WOL Ready Mode is enabled, the D+/D- pins ofAX88179 will be in tri-state.
Note 4: It is recommended that VBUS pin be connected to system power group directly. This way the VBUS will become
logic high when power management IC enables the system power supply.
Waken
Up by
USB
Host
Device
Device
Device
Device
Device
Device
Device
RWU bit Set_Feature
of Flag
standard
byte in
command
EEPROM
Setting
Wakeup Event
RWWF RWMP RWLC GPIO_1 Host Receiving Receiving a Link status change
(*)
sends a Wakeup
Magic
detected On PHY
resume Frame
Packet
signal
X
X
X
X
X
0
0
1
1
1
1
1
X
0
1
1
1
1
1
0
X
1
0
0
0
X
0
X
0
1
0
0
X
0
X
0
0
1
1
X
0
0
0
0
0
0
0
1
JK
Yes
X
Yes
X
X
X
Yes
Yes
Yes
*: About Default WOL Ready Mode, please refer to section 2.2 GPIO_1 Settings.
Table 13
Device
EXTWAKE_ wakes up
N pin
: Remote Wakeup Truth Table
64
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
Low-pulse
Low-pulse
No
Yes
Yes
Yes
Yes
Yes
Yes
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
A.2 Flow Chart of Default WOL Ready Mode
Step 1:
(1) Operation Mode setting by Pin#19, #21 (see Section 2.2 and Note 1).
(2) Set GPIO_0 as PME definition (see Note 2).
(3) Have GPIO_1 pulled-up to enable Default WOL Ready mode.
(4) Power on reset, either by on-chip power-on reset circuit or RESET_N pin.
The Default WOL Ready Mode is enabled.
Step 2:
Wakeup event asserts?
No
Yes
Step 3:
(1) PME asserts with static level that is used as
power control to system processor.
(2) Default WOL Ready Mode is disabled.
Step 4:
System processor powers on and supplies
VBUS to AX88179.
Step 5:
AX88179 is in normal operation mode.
Step 6:
Assert RESET_N AND
GPIO_1 = 1?
No
Yes
(1) PME de-asserts.
(2) The Default WOL Ready Mode is enabled.
65
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4F, No.8, Hsin Ann Rd., Hsinchu Science Park,
Hsinchu, Taiwan, R.O.C.
TEL: +886-3-5799500
FAX: +886-3-5799558
Email: [email protected]
Web: http://www.asix.com.tw
66
Copyright © 2011-2012 ASIX Electronics Corporation. All rights reserved.