ARIZONA MICROTEK, INC. AZ10LVE111E AZ100LVE111E ECL/PECL 1:9 Differential Clock Driver with Enable PACKAGE AVAILABILITY FEATURES • • • • • • • • Operating Range of 3.0V to 5.5V Low Skew Guaranteed Skew Spec Differential Design Enable VBB Output 75kΩ Internal Input Pulldown Resistors Direct Replacement for ON Semiconductor MC10E111 & MC100E111 PACKAGE PART NO. PLCC 28 AZ10LVE111EFN PLCC 28 AZ100LVE111EFN 1 2 MARKING AZ10 LVE111E <Date Code> AZ100 LVE111E <Date Code> NOTES 1,2 1,2 Add R2 at end of part number for 13 inch (750 parts) Tape & Reel. Date code format: “YY” for year followed by “WW” for week. DESCRIPTION The AZ10/100LVE111E is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q ¯ outputs HIGH. The AZ100LVE111E provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For single–ended input applications, the VBB reference should be connected to one side of the IN/IN ¯¯ differential input pair. The input signal is then fed to the other IN/IN ¯¯ input. The VBB pin should be used only as a bias for the AZ100LVE111E as its current sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01μF capacitor. The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate within-device skew, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met, both sides of the differential output must be terminated into 50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin. NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established. 1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541 www.azmicrotek.com AZ10LVE111E AZ100LVE111E Q0 Q0 Q1 VCCO Q1 Q2 Q2 25 24 23 22 21 20 19 LOGIC SYMBOL VEE 26 18 Q3 Q0 EN 27 17 Q3 Q0 IN 28 16 Q4 Q1 VCC 1 IN VBB Q1 NC Pinout: 28-Lead PLCC (top view) 15 VCCO 2 14 Q4 3 13 Q5 4 12 Q5 5 6 7 8 9 10 11 Q8 Q8 Q7 VCCO Q7 Q6 Q6 Q2 Q2 IN IN Q3 Q3 Q4 Q4 EN Q5 Q5 PIN DESCRIPTION PIN IN, IN ¯¯ EN ¯¯ Q0, Q0 ¯¯ - Q8, Q8 ¯¯ VBB VCC , VCCO VEE NC Q6 Q6 FUNCTION Differential Input Pair Enable Differential Outputs VBB Output Positive Supply Negative Supply No Connect Q7 Q7 Q8 Q8 V BB Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol VCC VI VEE VI IOUT TA TSTG Characteristic PECL Power Supply (VEE = 0V) PECL Input Voltage (VEE = 0V) ECL Power Supply (VCC = 0V) ECL Input Voltage (VCC = 0V) Output Current --- Continuous --- Surge Operating Temperature Range Storage Temperature Range Rating 0 to +8.0 0 to +6.0 -8.0 to 0 -6.0 to 0 50 100 -40 to +85 -65 to +150 Unit Vdc Vdc Vdc Vdc mA °C °C 10K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND) Symbol Characteristic 1 Min -1080 -1950 -1230 -1950 -1430 -40°C Typ Max -890 -1650 -890 -1500 -1300 150 VOH Output HIGH Voltage VOL Output LOW Voltage1 VIH Input HIGH Voltage VIL Input LOW Voltage VBB Reference Voltage Input HIGH Current IIH Input LOW Current 0.5 IIL IEE Power Supply Current 48 60 1. Each output is terminated through a 50Ω resistor to VCC – 2V. November 2006 * REV - 4 Min -1020 -1950 -1170 -1950 -1380 0°C Typ Max -840 -1630 -840 -1480 -1270 150 0.5 Min -980 -1950 -1130 -1950 -1350 25°C Typ Max -810 -1630 -810 -1480 -1250 150 0.5 48 www.azmicrotek.com 2 60 Min -910 -1950 -1060 -1950 -1310 85°C Typ Max -720 -1595 -720 -1445 -1190 150 0.5 48 60 48 60 Unit mV mV mV mV mV μA μA mA AZ10LVE111E AZ100LVE111E 10K LVPECL DC Characteristics (VEE = GND, VCC = VCCO = +3.3V) Symbol Characteristic 1,2 Min 2220 1350 2070 1350 1870 -40°C Typ Max 2410 1650 2410 1800 2000 150 Min 2280 1350 2130 1350 1920 0°C Typ Max 2460 1670 2460 1820 2030 150 Min 2320 1350 2170 1350 1950 VOH Output HIGH Voltage VOL Output LOW Voltage1,2 VIH Input HIGH Voltage1 VIL Input LOW Voltage1 VBB Reference Voltage1 IIH Input HIGH Current Input LOW Current 0.5 0.5 0.5 IIL IEE Power Supply Current 48 60 48 60 1. For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value 2. Each output is terminated through a 50Ω resistor to VCC – 2V. 25°C Typ Max 2490 1670 2490 1820 2050 150 Min 2390 1350 2240 1350 1990 85°C Typ Max 2580 1705 2580 1855 2110 150 0.3 48 60 48 60 Unit mV mV mV mV mV μA μA mA 10K PECL DC Characteristics (VEE = GND, VCC = VCCO = +5.0V) Symbol Characteristic Min 3920 3050 3770 3050 3570 -40°C Typ Max 4110 3350 4110 3500 3700 150 Min 3980 3050 3830 3050 3620 0°C Typ Max 4160 3370 4160 3520 3730 150 Min 4020 3050 3870 3050 3650 VOH Output HIGH Voltage1,2 VOL Output LOW Voltage1,2 VIH Input HIGH Voltage1 VIL Input LOW Voltage1 VBB Reference Voltage1 IIH Input HIGH Current Input LOW Current 0.5 0.5 0.5 IIL IEE Power Supply Current 48 60 48 60 1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value. 2. Each output is terminated through a 50Ω resistor to VCC – 2V. 25°C Typ Max 4190 3370 4190 3520 3750 150 Min 4090 3050 3940 3050 3690 85°C Typ Max 4280 3405 4280 3555 3810 150 0.3 48 60 48 60 Unit mV mV mV mV mV μA μA mA 100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND) Symbol Characteristic 1 Min -1085 -1830 -1165 -1810 -1380 -40°C Typ -1005 -1695 Max -880 -1555 -880 -1475 -1260 150 VOH Output HIGH Voltage VOL Output LOW Voltage1 VIH Input HIGH Voltage VIL Input LOW Voltage VBB Reference Voltage Input HIGH Current IIH Input LOW Current 0.5 IIL IEE Power Supply Current 48 60 1. Each output is terminated through a 50Ω resistor to VCC – 2V. Min -1025 -1810 -1165 -1810 -1380 0°C Typ -955 -1705 Max -880 -1620 -880 -1475 -1260 150 0.5 Min -1025 -1810 -1165 -1810 -1380 25°C Typ -955 -1705 Max -880 -1620 -880 -1475 -1260 150 0.5 48 60 Min -1025 -1810 -1165 -1810 -1380 85°C Typ -955 -1705 Max -880 -1620 -880 -1475 -1260 150 0.5 48 60 55 69 Unit mV mV mV mV mV μA μA mA 100K LVPECL DC Characteristics (VEE = GND, VCC = VCCO = +3.3V) Symbol Characteristic 1,2 Min 2215 1470 2135 1490 1920 -40°C Typ 2295 1605 Max 2420 1745 2420 1825 2040 150 Min 2275 1490 2135 1490 1920 0°C Typ 2345 1595 Max 2420 1680 2420 1825 2040 150 Min 2275 1490 2135 1490 1920 VOH Output HIGH Voltage VOL Output LOW Voltage1,2 VIH Input HIGH Voltage1 VIL Input LOW Voltage1 VBB Reference Voltage1 IIH Input HIGH Current Input LOW Current 0.5 0.5 0.5 IIL IEE Power Supply Current 48 60 48 60 1. For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value. 2. Each output is terminated through a 50Ω resistor to VCC – 2V. November 2006 * REV - 4 www.azmicrotek.com 3 25°C Typ 2345 1595 Max 2420 1680 2420 1825 2040 150 Min 2275 1490 2135 1490 1920 85°C Typ 2345 1595 Max 2420 1680 2420 1825 2040 150 0.5 48 60 55 69 Unit mV mV mV mV mV μA μA mA AZ10LVE111E AZ100LVE111E 100K PECL DC Characteristics (VEE = GND, VCC = VCCO = +5.0V) Symbol Characteristic 1,2 Min 3915 3170 3835 3190 3620 -40°C Typ 3995 3305 Max 4120 3445 4120 3525 3740 150 Min 3975 3190 3835 3190 3620 0°C Typ 4045 3295 Max 4120 3380 4120 3525 3740 150 Min 3975 3190 3835 3190 3620 VOH Output HIGH Voltage VOL Output LOW Voltage1,2 VIH Input HIGH Voltage1 VIL Input LOW Voltage1 VBB Reference Voltage1 IIH Input HIGH Current Input LOW Current 0.5 0.5 0.5 IIL IEE Power Supply Current 48 60 48 60 1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value. 2. Each output is terminated through a 50Ω resistor to VCC – 2V. 25°C Typ 4045 3295 Max 4120 3380 4120 3525 3740 150 Min 3975 3190 3835 3190 3620 85°C Typ 4045 3295 Max 4120 3380 4120 3525 3740 150 0.5 48 60 55 69 Unit mV mV mV mV mV μA μA mA AC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND or VEE = GND, VCC = VCCO = +3.0 to +5.5V) Symbol tPLH / tPHL tS tH tR tskew VPP (AC) Characteristic Propagation Delay to Output IN (Diff)1 IN (SE)2 Enable3 Disable3 Setup Time EN ¯¯ to IN5 Hold Time IN to EN ¯¯ 6 Release Time EN ¯¯ to IN7 Within-Device Skew4 Minimum Input Swing8 Min 380 280 400 400 250 50 350 -40°C Typ Max Min 650 700 900 900 460 410 450 450 200 0 300 0 -200 100 25 0°C Typ 0 -200 100 25 Max Min 560 610 850 850 480 430 450 450 200 0 300 25°C Typ Max Min 580 630 850 850 510 460 450 450 200 0 300 0 -200 100 25 85°C Typ Max 610 660 850 850 0 -200 100 25 75 50 50 50 250 250 250 250 VCC VEE + VCC VEE + VCC VEE + VCC VEE + VCMR Common Mode Range9 1.8 0.4 1.8 0.4 1.8 0.4 1.8 0.4 tr / t f Rise/Fall Time 250 650 275 600 275 600 275 600 1. The differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 3. Enable is defined as the propagation delay from the 50% point of a negative transition on EN ¯¯ to the 50% point of a positive transition on Q (or a negative transition on Q ¯ ). Disable is defined as the propagation delay from the 50% point of a positive transition on EN ¯¯ to the 50% point of a negative transition on Q (or a positive transition on Q ¯ ). 4. The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device. 5. The setup time is the minimum time that EN ¯¯ must be asserted prior to the next transition of IN/IN ¯¯ to prevent an output response greater than ±75mV to that IN/IN ¯¯ transition (see Figure 1). 6. The hold time is the minimum time that EN ¯¯ must remain asserted after a negative going IN or a positive going IN ¯¯ to prevent an output response greater than ±75 mV to that IN/IN ¯¯ transition (see Figure 2). 7. The release time is the minimum time that EN ¯¯ must be de-asserted prior to the next IN/IN ¯¯ transition to ensure an output response that meets the specified IN to Q propagation delay and output transition times (see Figure 3). 8. VPP is defined as the minimum peak-to-peak differential input swing for which AC parameters are guaranteed. The VPP(min) is AC limited for the LVE111E, because differential input as low as 50 mV will still produce full ECL levels at the output. 9. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0 V and greater than or equal to VPP(min). IN IN IN IN IN IN H EN EN November 2006 * REV - 4 www.azmicrotek.com 4 EN Unit ps ps ps ps ps mV V ps AZ10LVE111E AZ100LVE111E DIM A B C E F G H J K R U V W X T Z G1 K1 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 0.64 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 0.50 2O 10O 10.42 10.92 1.02 November 2006 * REV - 4 PACKAGE DIAGRAM PLCC 28 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2O 10O 0.410 0.430 0.040 www.azmicrotek.com 5 NOTES: 1. DATUMS –L-, -M-, AND –N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALOWABLE MOLD FLASH IS 0.010mm (0.250in.) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKGE BOTTOM BY UP TO 0.012mm (0.300in.). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, THE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025mm (0.635in.). AZ10LVE111E AZ100LVE111E Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. November 2006 * REV - 4 www.azmicrotek.com 6