Philips Semiconductors Product Specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mount applications. The device is intended for use in automotive and general purpose switching applications. PINNING - SOT223 PIN BUK581-60A QUICK REFERENCE DATA SYMBOL PARAMETER MAX. UNIT VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V 60 1.5 1.5 150 0.40 V A W ˚C Ω PIN CONFIGURATION DESCRIPTION 1 gate 2 drain 3 source 4 drain (tab) SYMBOL d 4 g 2 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ID ID IDM Ptot Tstg Tj Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction Temperature RGS = 20 kΩ Tamb = 25 ˚C Tamb = 100 ˚C Tamb = 25 ˚C Tamb = 25 ˚C - - 55 - 60 60 15 1.5 1 6 1.5 150 150 V V V A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL Rth j-sp Rth j-amb PARAMETER CONDITIONS 1 From junction to solder point From junction to ambient Mounted on any PCB . Mounted on PCB of Fig.18 MIN. TYP. MAX. UNIT - 14 - 17 85 K/W K/W 1 Temperature measured at solder joint on drain tab. October 1995 1 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET BUK581-60A STATIC CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance VGS(TO) IDSS IDSS IGSS RDS(ON) MIN. TYP. MAX. UNIT VGS = 0 V; ID = 0.25 mA 60 - - V VDS = VGS; ID = 0.1 mA VDS = 60 V; VGS = 0 V; VDS = 60 V; VGS = 0 V; Tj = 125 ˚C VGS = ±15 V; VDS = 0 V VGS = 5 V; ID = 1.5 A 1.0 - 1.5 1 0.1 10 0.28 2.0 10 1.0 100 0.40 V µA mA nA Ω MIN. TYP. MAX. UNIT DYNAMIC CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 1.5 A 1.0 2.2 - S Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 170 60 25 300 100 50 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 Ω; Rgen = 50 Ω - 7 45 15 25 10 55 25 35 ns ns ns ns MIN. TYP. MAX. UNIT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IDR - - - 1.5 A IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage IF = 1.5 A; VGS = 0 V - 0.85 6 1.1 A V trr Qrr Reverse recovery time Reverse recovery charge IF = 1.5 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V - 30 50 - ns nC MIN. TYP. MAX. UNIT - - 10 mJ AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSS Drain-source non repetitive unclamped inductive turn-off energy ID = 1.5 A ; VDD < 25 V VGS = 5 V ; RGS = 50 Ω Tamb = 25 ˚C October 1995 2 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET Normalised Power Derating PD% 10 ID / A BUK581-60A ID 120 BUK581-60A tp = 100 us VD S/ 110 N )= 100 O 90 D S( 1 ms R 80 1 70 10 ms 60 DC 50 40 100 ms 0.1 1s 30 10 s 20 10 0.01 0.1 0 0 20 40 60 80 Tamb / C 100 120 140 Normalised Current Derating ID% 10 VDS / V 100 Fig.4. Safe operating area Tamb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tamb) 120 1 100 BUK581-60A ID / A 10 5 110 4.5 5 4 90 4 80 3 70 3.5 60 50 2 40 3 30 1 20 VGS / V = 2.5 10 0 0 20 40 60 80 Tamb / C 100 120 0 140 0 1E+01 4 6 8 10 VDS / V Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tamb); conditions: VGS ≥ 5 V 1E+02 2 BUKX81 Zth j-amb / (K/W) D= 0.5 1 RDS(ON) / Ohm 3 BUK581-60A 4 3.5 0.9 0.8 0.2 0.1 0.05 0.7 0.6 0.02 0.5 1E+00 PD tp D= tp 4.5 5 0.4 T 0.3 1E-01 0.2 t T 1E-02 1E-07 0 1E-05 1E-03 1E-01 1E+01 0 1E+03 1 2 3 4 5 ID / A t/s Fig.3. Transient thermal impedance. Zth j-amb = f(t); parameter D = tp/T October 1995 VGS / V = 10 0.1 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 3 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET 5 BUK581-60A VGS(TO) / V BUK581-60A ID / A max. 2 4 Tj / C = 25 typ. 150 3 min. 1 2 1 0 0 0 2 1 4 3 -60 5 -40 -20 0 20 VGS / V BUK581-60A gfs / S 80 100 120 140 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.1 mA; VDS = VGS Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 40 60 Tj / C SUB-THRESHOLD CONDUCTION SIZE 1 ID / A 1E-02 1E-03 2% 1E-04 98 % typ 1E-05 1E-06 1E-07 0 2 1 4 3 5 0 0.4 0.8 1.2 VGS / V ID / A Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V a 1.6 2 2.4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised RDS(ON) = f(Tj) 1000 BUK581-60A C / pF 1.5 Ciss 1.0 100 Coss 0.5 Crss 0 10 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 0 20 30 40 VDS / V Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 1.5 A; VGS = 5 V October 1995 10 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET 10 BUK581-60A BUK581-60A VGS / V 120 WDSS% Normalised Avalanche Energy 110 9 VDS / V =12 48 100 90 80 8 7 6 70 60 50 5 4 40 30 20 3 2 1 10 0 0 0 2 4 6 8 20 10 40 QG / nC Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 1.5 A; parameter VDS 5 60 80 100 Tamb/ C 120 140 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tamb); conditions: ID = 1.5 A BUK581-60A IF / A VDD + L 4 Tj / C = 150 25 VDS - 3 VGS -ID/100 2 T.U.T. 0 1 RGS 0 0 1 0.5 1.5 VSDS / V Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj October 1995 R 01 shunt 5 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET BUK581-60A MOUNTING INSTRUCTIONS PRINTED CIRCUIT BOARD Dimensions in mm. Dimensions in mm. 36 3.8 min 1.5 min 18 60 2.3 1.5 min 4.5 4.6 9 6.3 10 (3x) 1.5 min 4.6 7 15 50 Fig.18. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick). Fig.17. soldering pattern for surface mounting SOT223. October 1995 6 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET BUK581-60A MECHANICAL DATA Dimensions in mm 6.7 6.3 Net Mass: 0.11 g B 3.1 2.9 0.32 0.24 0.2 4 A A 0.10 0.02 16 max M 7.3 6.7 3.7 3.3 13 2 1 10 max 1.8 max 1.05 0.80 2.3 0.60 0.85 4.6 3 0.1 M B (4x) Fig.19. SOT223 surface mounting package. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to surface mounting instructions for SOT223 envelope. 3. Epoxy meets UL94 V0 at 1/8". October 1995 7 Rev 1.100 Philips Semiconductors Product Specification PowerMOS transistor Logic level FET BUK581-60A DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1995 8 Rev 1.100