TRIQUINT GA1085

R
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S E M I C O N D U C T O R, I N C .
GA1085
Figure 1. Block Diagram
FBIN
S1
REFCLK
S0
F1
F0
GND
11
10
9
8
7
6
5
TEST 12
4 VDD
Phase
Detector
VDD 13
Phase
Select
VCO
Q0
14
MUX
GND 15
Q1
16
Q2
17
VDD 18
Q10
2
Q9
1 GND
Divide Logic
÷4, ÷5, or ÷6
Group
B
3
11-Output
Configurable
Clock Buffer
Output Buffers
Group
C
28
Q8
27
Q7
26 VDD
Group A
19
20
21
22
23
24
25
GND
Q3
Q4
VDD
Q5
Q6
GND
TriQuint’s GA1085 is a configurable clock buffer which generates 11 outputs
and operates over a wide range of frequencies—from 24 MHz to 105 MHz.
The outputs are available at either 1x and 2x or at 1x and 1/2 x the reference
clock frequency, fREF. When one of the Group A outputs (Q4–Q8) is used as
feedback to the PLL, all Group A outputs will be at fREF , and all Group B
(Q0–Q3) and Group C (Q9, Q10) outputs will be at 1/2 x fREF . When one of
the Group B outputs is used as feedback to the PLL, all Group A outputs
will be at 2x REF and all Group B and Group C outputs will be at fREF . The
Shift Select pins select the phase shift (–2t, –t, +t or +2t) for Group C
outputs (Q9, Q10) with respect to REFCLK. The phase shift increment (t)
is equivalent to the VCO’s period (1/fVCO).
A very stable internal Phase-Locked Loop (PLL) provides low-jitter operation.
This completely self-contained PLL requires no external capacitors or resistors.
The PLL’s Voltage-Controlled Oscillator (VCO) has a frequency range from
280 MHz to 420 MHz. By feeding back one of the output clocks to FBIN,
the PLL continuously maintains frequency and phase synchron-ization
between the reference clock (REFCLK) and each of the outputs.
Features
• Wide frequency range:
24 MHz to 105 MHz
• Output configurations:
Four outputs at fREF
Four outputs at fREF /2
Two outputs at fREF /2
␣ ␣ ␣ ␣ with adjustable phase
␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ or
Five outputs at 2x fREF
Three outputs at fREF
Two outputs at fREF
␣ ␣ ␣ ␣ with adjustable phase
SYSTEM TIMING
PRODUCTS SYSTEMS TIMING
T
• Selectable Phase Shift: –2t, –t,
+t, and +2t (t = 1/fVCO)
• Low output-to-output skew: 150
ps (max) within a group
• Near-zero propagation delay:
–350 ps +1000 ps (max)
• TTL-compatible with 30 mA
output drive
• 28-pin J-lead surface-mount
package
TriQuint’s patented output buffer design delivers a very low output-to-output
skew of 150 ps (max). The GA1085’s symmetrical TTL outputs are capable
of sourcing and sinking 30 mA.
For additional information and latest specifications, see our website: www.triquint.com
1
GA1085
Functional Description
The phase-shift increment (t) is calculated using the
following equation:
The core of the GA1085 is a Phase-Locked Loop (PLL)
that continuously compares the reference clock (REFCLK)
to the feedback clock (FBIN), maintaining a zero
frequency difference between the two. Since one of the
outputs (Q0–Q8) is always connected to FBIN, the PLL
keeps the propagation delay between the outputs and
the reference clock within –350 ps +1000 ps.
The internal Voltage-Controlled Oscillator (VCO) has an
operating range of 280 MHz to 420 MHz. The
combination of the VCO and the Divide Logic enables
the GA1085 to operate between 24 MHz and 105 MHz.
The device features six divide modes: ÷4, ÷5, ÷6, ÷8,
÷10, and ÷12. The Frequency Select pins, F0 and F1,
and the output used as feedback to FBIN set the divide
mode as shown in Table 1.
The Shift Select pins, S0 and S1, control the phase
shift of Q9 and Q10 relative to the other outputs. The
user can select from four incremental phase shifts as
shown in Table 2.
t=
1
(f REF) (n)
where n is the divide mode.
In the test mode, the PLL is bypassed and REFCLK is
connected directly to the Divide Logic block via the
MUX, as shown in Figure 1. This mode is useful for
debug and test purposes. The various test modes are
outlined in Table 3. In the test mode, the frequency of
the reference clock is divided by 4, 5, or 6.
The maximum rise and fall time at the output pins is
1.4 ns. All outputs of the GA1085 are TTL-compatible
with 30 mA symmetric drive and a minimum VOH of 2.4 V.
Power-Up/Reset Synchronization
After power-up or reset, the PLL requires time before it
achieves synchronization lock. The maximum time
required for synchronization (TSYNC) is 500 ms.
Table 1. Frequency Mode Selection
Feedback: Any Group A Output (Q4 – Q8)
Test
0
0
0
0
Select Pins
F0
1
0
0
1
F1
0
0
1
1
Mode
÷4
÷5
÷6
Not Used
Reference Clock
Frequency Range
70 MHz – 105 MHz
56 MHz – 84 MHz
48 MHz – 70 MHz
N.A.
Output Frequency Range
Group A: Q4–Q8
B: Q0–Q3, C: Q9–Q10
70 MHz – 105 MHz
35 MHz – 52 MHz
1
56 MHz – 84 MHz
28 MHz – 42 MHz
48 MHz – 70 MHz
24 MHz – 35 MHz
N.A.
N.A.
Reference Clock
Frequency Range
35 MHz – 52 MHz
28 MHz – 42 MHz
24 MHz – 35 MHz
N.A.
Output Frequency Range
Group A: Q4–Q8
B: Q0–Q3, C: Q9–Q10
70 MHz – 105 MHz
35 MHz – 52 MHz
1
56 MHz – 84 MHz
28 MHz – 42 MHz
48 MHz – 70 MHz
24 MHz – 35 MHz
N.A.
N.A.
Feedback: Any Group B Output (Q0 – Q3)
Test
0
0
0
0
Note:
2
Select Pins
F0
1
0
0
1
F1
0
0
1
1
Mode
÷8
÷ 10
÷ 12
Not Used
1. This mode produces outputs with 40/60 duty cycle for Q4 – Q8 only.
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GA1085
Table 2. Phase Shift Selection
S0
0
S1
0
Phase Difference (Q9, Q10)
+2t
0
1
+t
1
0
–t
1
1
–2t
Table 3. Test Mode Selection
Test
F0
F1
Mode
Ref. Clock
Group A:
Outputs Q4–Q8
Groups B, C:
Q0–Q3, Q9, Q10
1
1
1
1
0
0
0
0
1
÷4
÷5
÷6
f REF
f REF
f REF
f REF ÷ 4
f REF ÷ 5
f REF ÷ 6
f REF ÷ 8␣ ␣
f REF ÷ 10
f REF ÷ 12
1
1
1
—
—
—
—
Multiple ground and power pins on the GA1085 reduce
ground bounce. Good layout techniques, however, are
necessary to guarantee proper operation and to meet
the specifications across the full operating range.
TriQuint recommends bypassing each of the VDD supply
pins to the nearest ground pin, as close to the chip as
possible.
Figure 2 shows the recommended power layout for the
GA1085. The bypass capacitors should be located on
the same side of the board as the GA1085. The VDD
traces connect to an inner-layer VDD plane. All of the
ground pins (GND) are connected to a small ground
plane on the surface beneath the chip. Multiple
through-holes connect this small surface plane to an
inner-layer ground plane. The capacitors (C1–C5) are
0.1 µF. TriQuint’s test board uses X7R temperaturestable capacitors in 1206 SMD cases.
SYSTEM TIMING
SYSTEM TIMING
PRODUCTS
Layout Guidelines
Figure 2. Top Layer Layout of Power Pins
(magnified approximately 3.3x)
V DD
C4
V DD
C3
Pin 1
Ground
Plane
V DD
C2
C1
C5
V DD
V DD
Pin 15
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3
GA1085
Absolute Maximum Ratings1
Storage temperature
–65 °C to +150 °C
Ambient temperature with power applied 2
–55 °C to +100 °C
Supply voltage to ground potential
DC input voltage
DC input current
Package thermal resistance (MQuad)
Die junction temperature
–0.5 V to +7.0 V
–0.5 V to (VDD + 0.5) V
–30 mA to +5 mA
θJA = 45 °C/W
TJ = 150 °C␣ ␣ ␣ ␣
DC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C)
Min3
Typ
VDD = Min IOH = –30 mA
VIN = VIH or VIL
2.4
3.4
V
VDD = Min IOH = –1 mA
VIN = VIH or VIL
VDD = Min IOL = 30 mA
VIN = VIH or VIL
Guaranteed input logical
3.2
4.1
V
Symbol
Description
Test Conditions
VOHT
Output HIGH voltage
VOHC
Output HIGH voltage
VOL
Output LOW voltage
VIH 4
Input HIGH level
VIL4
Input LOW level
IIL
IIH
Input LOW current
Input HIGH current
HIGH voltage for all Inputs
Guaranteed input logical
LOW voltage for all inputs
VDD = Max VIN = 0.40 V
VDD = Max VIN = 2.7 V
II
IDDS5
VI
Input HIGH current
Power supply current
Input clamp voltage
VDD = Max VIN = 5.5 V
VDD = Max
VDD = Min IIN = –18 mA
Max3
0.27
Unit
0.5
V
2.0
V
0.8
V
–156
0
–400
25
µA
µA
2
119
–0.70
1000
160
–1.2
µA
mA
V
Capacitance
Symbol
CIN
Notes:
4
6
Description
Test Conditions
Input capacitance
VIN = 2.0 V at f = 1 MHz
Min
Typ
Max
6
1. Exceeding these parameters may damage the device.
2. Maximum ambient temperature with device not switching and unloaded.
3. Typical limits are at VDD = 5.0 V and TA = 25 °C.
4. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
5. This parameter is measured with device not switching and unloaded.
6. These parameters are not 100% tested, but are periodically sampled.
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Unit
pF
GA1085
AC Characteristics
(VDD = +5 V + 5%, TA = 0 °C to +70 °C)
Symbol
Input Clock (REFCLK)
Test Conditions (Figure 3)1
tCPWH
tCPWL
CLK pulse width HIGH
CLK pulse width LOW
Figure 4
Figure 4
tIR
Input rise time (0.8 V – 2.0 V)
Min Typ
Max
Unit
3
3
-----
—
—
ns
ns
—
—
2.0
ns
Output Clocks (Q0–Q10)
Rise/fall time (0.8 V–2.0 V)
CLK Î to FBIN Î (GA1085-MC1000)
Figure 4
Figure 4
tSKEW13
Rise–rise, fall–fall (within group)
Figure 5
—
60
150
ps
tSKEW23
Rise–rise, fall–fall
(group-to-group, aligned)
Figure 6
(skew2 takes into account skew1)
—
75
350
ps
tSKEW33
ps
1200
ps
tCYC4
Duty-cycle Variation
Figure 7
— —
(skew3 takes into account skew1, skew2)
Figure 8
— —
(skew4 takes into account skew3)
Figure 4
–1000 0
650
tSKEW43
Rise–rise, fall–fall
(group-to-group, non-aligned)
Rise–fall, fall–rise
+1000
ps
tJP5
tJR5
Period-to-Period Jitter
Random Jitter
Synchronization Time
200
400
500
ps
ps
µs
tSYNC6
Notes:
350 — 1400
–1350–350 +650
Figure 4
Figure 4
— 80
— 190
— 10
ps
ps
SYSTEM TIMING
SYSTEM TIMING
PRODUCTS
tOR, tOF
tPD2
1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.
4. This specification represents the deviation from 50/50 on the outputs.
5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock.
tJP is the jitter on the output with respect to the output’s previous rising edge.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and
a connection from one of the outputs to FBIN.
Figure 3. AC Test Circuit
Y
+5 V
R1
50 Ω
X
Z
FBIN
R2
+5 V
R1
Z
CLK
R2
Q0
Q1
Q2
•
•
•
•
Q10
•
•
•
•
+5 V
R1
+5 V
R2
R1
R2
+5 V
R1
R2
Notes:
R1 = 160 Ω
R2 = 71 Ω
Y+Z=X
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5
GA1085
Switching Waveforms
Figure 3. General Timing
Figure 6. tSKEW3
(For Group B Feedback)
tCPW
tCPW
REFCLK
Period =
f = 2x f REF
t PD1,2
t JR
Group A
t1
t SKEW3 =
FBIN
Period
– t1
2
(For Group A or B Feedback)
t PERIOD
Q0 – Q10
(INDIVIDUALLY)
1
f REFCLK
t JP
Group A
t4
Group C
t SKEW3 =
n – t4
t SKEW3 =
n – t4
Group B
Figure 4. tSKEW1
t4
Group C
Group A
Group A
Note:“n” is the phase-shift increment: 2t, t, –t, –2t.
t SKEW1
t SKEW1
Group B
Group B
t SKEW1
t SKEW1
Group C
Figure 7. tSKEW4
Period =
f = f REF
1
f REFCLK
Groups B, C
Group C
t SKEW1
t SKEW1
t2
f = 2x f REF
Group A
t3
Figure 5. tSKEW2
t SKEW4 =
Period
– t2 =
2
Group B
Group A
t SKEW2
6
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t4
Period
– t3 =
4
Period
– t4
4
GA1085
28-Pin MQuad J-Leaded Package Mechanical Specification
(All dimensions are in inches)
.172 ±.005
.490 ±.005
.132 ±.005
.445 ±.005
.040 MIN
PIN 1
8
.490
±.005
22
.445
±.005
.445 .028
±.005
0.125
VENT PLUG
15
.015
X 45°°
.018
.410
±.015
.050 TYP.
.060
.104
±.005
.050 TYP.
NON-ACCUM.
SYSTEM TIMING
SYSTEM TIMING
PRODUCTS
.045
X 45°°
28-Pin MQuad Pin Description
Pin #
Pin Name
Description
I/O
Pin #
Pin Name
Description
I/O
1
2
GND
Q9
Ground
Output Clock 9 (C1)
—
O
15
16
GND
Q1
Ground
Output Clock 1 (B2)
—
O
3
4
5
6
7
8
9
10
11
12
13
14
Q10
VDD
GND
F0
F1
S0
REFCLK
S1
FBIN
TEST
VDD
Q0
Output Clock 10 (C2)
+5 V
Ground
Frequency Select 0
Frequency Select 1
Shift Select 0
Reference Clock
Shift Select 1
Feedback In
Test
+5 V
Output Clock 0 (B1)
O
—
—
I
I
I
I
I
I
I
—
O
17
18
19
20
21
22
23
24
25
26
27
28
Q2
VDD
GND
Q3
Q4
VDD
Q5
Q6
GND
VDD
Q7
Q8
Output Clock 2 (B3)
+5 V
Ground
Output Clock 3 (B4)
Output Clock 4 (A1)
+5 V
Output Clock 5 (A2)
Output Clock 6 (A3)
Ground
+5 V
Output Clock 7 (A4)
Output Clock 8 (A5)
O
—
—
O
O
—
O
O
—
—
O
O
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7
GA1085
Output Characteristics
The IV characteristics, transition times, package
characteristics, device and bond-wire characteristics
for the GA1085 are described in Tables 4 through 9 and
Figures 9 through 11.
These output characteristics are provided for
modelling purposes only. TriQuint does not guarantee
the information in these tables and figures.
Figure 9. IOH vs.VOH
Figure 10. IOL vs.VOL
HIGH
1.0
2.0
3.0
4.0
LOW
5.0
160
-20
VOH min
140
VOL min
-40
VOH max
120
VOL max
-60
IOL (mA)
IOH (mA)
0
0.0
-80
-100
100
80
60
-120
40
-140
20
0
-160
Volts
0.0
2.0
3.0
4.0
5.0
Volts
Table 4. IOH vs.VOH
Table 5. IOL vs.VOL
VOH
IOH min (mA)
IOH max (mA)
VOL
IOL min (mA)
IOL max (mA)
0.0
0.5
–70
–70
–160
–157
–2.5
–2.0
–145
–135
–435
–410
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
6.0
7.0
8.0
9.0
10.0
–68
–65
–59
–48
–29
0
0
0
0
0
0
0
0
0
–152
–142
–130
–106
–79
–42
0
0
0
0
0
0
1
5
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10.0
–115
–90
–40
0
37
49
53
54
54
54
54
54
54
54
54
–350
–265
–120
0
97
140
155
157
159
160
160
160
160
160
160
Notes:
8
1.0
1. These are worst-case corners for process, voltage,
and temperature.
2. Includes diode to ground current.
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GA1085
V
Diode to GND␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣
I (mA)
Diode Stack to VDD
V
I (mA)
0.15
0.32
3.20
3.04
0
0.1
0.2
0.15
0.16
0.32
0.32
3.20
3.06
3.04
2.95
7.0
8.0
0
0
0.3
0.18
0.32
2.86
2.90
9.0
10.0
11.0
12.0
0
1
5
9
0.4
0.5
0.23
0.26
0.32
0.32
2.62
2.38
2.68
2.50
0.6
0.7
0.8
0.9
1.0
0.34
0.46
0.67
0.89
1.12
0.32
0.34
0.39
0.49
0.63
2.17
2.00
1.85
1.69
1.52
2.36
2.22
2.09
1.95
1.86
1.1
1.2
1.3
1.4
1.5
1.32
1.50
1.73
1.93
2.15
0.86
1.09
1.27
1.45
1.64
1.38
1.26
1.12
0.96
0.83
1.68
1.59
1.49
1.36
1.23
1.6
1.7
1.8
1.9
2.0
2.75
2.58
2.75
2.90
3.02
2.23
2.00
2.23
2.41
2.50
0.52
0.61
0.52
0.45
0.39
0.95
1.00
0.95
0.91
0.86
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.12
3.17
3.19
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
2.64
2.77
2.86
2.95
2.99
3.02
3.02
3.04
3.04
3.04
3.04
3.04
3.04
3.04
3.04
0.33
0.29
0.24
0.21
0.19
0.17
0.16
0.16
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.77
0.73
0.68
0.64
0.59
0.55
0.53
0.50
0.45
0.41
0.40
0.37
0.36
0.32
0.32
0
5.0
0
–0.4
0
6.0
–0.5
–0.6
0
–5
–0.7
–0.8
–0.9
–1.0
–2.0
–15
–35
–55
–75
–300
–2.5
–3.0
–350
–360
Note: TriQuint does not guarantee diode operation for purposes other
than ESD protection.
Figure 11. Output Model
L1
L2
OUTPUT
C1
C2
Table 7. Device and Bond-Wire Characteristics
(Estimates)
L1
C1
2 nH
10 pF
Table 8. 28-Pin MQuad Package Characteristics
L2
C2
1.85 nH
0.40 pF
Time (ns) TR min (V) TR max (V) TF min (V) TF max (V)
0.0
0.0
DIE
Table 9. Rise and Fall Times
(Into 0 pF, 50 Ohms to 1.5 V)
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SYSTEM TIMING
SYSTEM TIMING
PRODUCTS
Table 6. Characteristics Above VDD and Below Ground
9
GA1085
Ordering Information
To order, please specify as shown below:
GA1085-MC nnnn
11-Output Configurable Clock Buffer
Propagation delay skew: 1000 = –350 ps ± 1000 ps
Temperature range: Commercial (0 °C to 70 °C)
Package: MQuad
For latest specifications, additional product information,
worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Email: [email protected]
Tel: (503) 615-9000
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: [email protected]
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or
omissions. TriQuint assumes no responsibility for the use of this information, and all such information
shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved.
Revision 1.1.A
November 1997
10
For additional information and latest specifications, see our website: www.triquint.com