M61558FP Power driver IC for 30-W × 1-channel digital amplifiers REJ03F0060-0100Z Rev.1.0 Sep.19.2003 Description The M61558FP is a power driver IC for digital power amplifiers. The IC incorporates both pre-drivers and the outputstage n-channel power MOS FET, for a single chip implementation of a 30-W single-channel digital amplifier for audio applications. Features • • • • On-chip n-channel power MOS FET Fast PWM switching operation On-chip diode for boot strap Various on-chip protective circuits VDD under detection circuit Over-Temperature protection circuit Over-current protection circuit Recommended Operating Conditions Power-supply voltage for pre-drive stage: VDD = 12 V (pre-driver stage power-supply voltage) Output-stage power-supply voltage: VD = 21 V (typ.) < 16 V (min.) to 24 V (max.), RL = 4 (min.), 6 (typ.), 8 (max.) Ω Rev.1.0, Sep.19.2003, page 1 of 17 M61558FP System block diagram HBA MCU M61558FP INA+ PWM processor VDA Level shifter OUTA VSA Over-Temperature protection detector CH1 Over current protection HBB INB+ CH2 VDB Level shifter OUT B VSB Rev.1.0, Sep.19.2003, page 2 of 17 M61558FP Sample application circuit and pin assignments PWM processor MCU VDD = 12 V (from 10.8V to 13.2V) GND 0.1µF 10µF 100µF PROUT 21 22 GNDP 23 FILP5V PROUT VDDP 20 6.2K 24 DTCNTL EN INB + PRVD 18 26 INB + INA + 17 INA + FILA5V 16 10µF 0.1µ 28 GNDB 29 LSGOUTB 10µF 30 VDDB 31 HBB 32 SUB(G ND 2.7 33 HSGOUT 10 34 HSGINB 35 LSGINB 36 SUB(G ND 0.022uF 37 VDB 0.1µ GNDA 15 SUB(G ND 14 10uH Vz=33V VDDA 12 HBA 11 SUB(G ND 10 HSGOUT 9 2.7 10 HSGINA 8 LSGINA 7 VDA 6 VDA 5 39 OUTB OUTA 4 40 OUTB OUTA 3 41 VSB VSA 2 42 VSB VSA 1 0.022µF 0.1µF 47µF LPF 10uH 1u Vz=33V VD=21 (16 to 24)V (max. current: about 7.5 A) 10Ω 470µF 0.1µ 1000pF (for EMI) RL=4 to 8 Rev.1.0, Sep.19.2003, page 3 of 17 10µF LSGOUTA 13 38 VDB LPF 1u M61558FP 0.1µ 10nF 25 EN 27 FILB5V 10µF 47µF PRLPFVD 19 Damping circuit Rev.1.0, Sep.19.2003, page 4 of 17 16 17 12 20 21 25 24 23 22 30 26 27 28 VDDB INB FILB5 V GNDB Dead-time control Level shifter LSGOUT 13 PRVD VSA OUTA VDA OUTB VDB 19 VSB PRLPFVD 18 GNDP 1 FILP5 2 DTCNT VDD under voltage detector 3 Dead-time control circuit HSGOUT 9 Over-Temperatire protection circuit 4 Protector control logic 5 EN HBA 11 Over-current protection circuit 6 PROUT 15 VDDP 7 VDD A Level shifter LSGIN INA Dead-time control 8 FILA5 HSGIN GND A M61558FP Block diagram 42 41 40 39 38 37 34 HSGIN B 35 LSGINB 31 HBB 33 HSGOUT B 29 LSGOUTB M61558FP Pin Descriptions A-side power module A-side precontrol module A, B common protection module B-side precontrol module B-side power module Pin No. Pin Name Pin Description 1, 2 VSA Ground pin for the A-side power-output stage 3, 4 OUTA A-side power-output pin 5, 6 7 VDA LSGINA Power-supply pin for A-side power-output stage MOS FET input pin for A-side (L) 8 9 HSGINA HSGOUTA MOS FET input pin for A side (H) A side (H) pre-buffer output 10 11 NC HBA Connected to ground A pin for A side (H) boot strap.* 12 13 VDDA LSGOUTA A-side pre-driver power-supply pin A-side (L) pre-buffer output 14 15 NC GNDA Connected to ground A-side pre-driver ground pin 16 17 FILA5V INA+ Filter pin for A-side 5-V internal generation power-supply A-side PWM + input pin (CMOS input) 18 19 PRVD PRLPFVD Power-supply pin for over current protection. Connected to VD power supply. Filter pin for over-current protection circuit 20 21 VDDP PROUT Power-supply pin for protection circuit block Protection detector output pin. When protection condition is detected, low level (if pin is pulled up) is output (open drain output). 22 23 GNDP FILP5V Ground pin for protection circuit block Filter pin for generation of 5-V internal power-supply for protection circuits 24 25 DTCNTL EN For connection to a resistor for dead-time control Enable pin that release from the protection state 26 27 INB+ FILB5V B-side PWM + input pin (CMOS input) B-side 5-V internal generation power-supply filter pin 28 29 GNDB LSGOUTB B-side pre-driver ground pin B-side (L) pre-buffer output 30 31 VDDB HBB B pre-driver power-supply pin Apm for B-side (H) boot-strap capacitor circuit. 32 33 NC HSGOUTB Connected to ground B–side (H) pre-buffer output 34 HSGINB B side (H) MOS FET input pin 35 LSGINB B side (L) MOS FET input pin 36 NC Connected to ground 37, 38 VDB B-side power-output stage power-supply pin 39, 40 OUTB B-side power-output pin 41, 42 VSB B-side power-output stage ground pin Note: * Adjacent power-module pins that have the same names must be connected with the shortest possible wiring lengths. Rev.1.0, Sep.19.2003, page 5 of 17 M61558FP Absolute Maximum Ratings Parameter Symbol Ratings Unit Conditions HBA, HBB max. operating voltage HBA, HBB 39 V HBA, HBB pin voltage (operational setting) VDA, VDB max. operating voltage VDA, VDB 25 V VDA, VDB pin voltage (operational setting) Absolute max. voltage rating Voltage applied to input pins VDD Vin 15 −0.3 to 5.5 V V VDD power-supply voltage Allowable dissipation Pd 3.6 W Thermal derating Kθ 28.8 mW/°C Ta = 25°C (when mounted on the board specified by Renesas; see note 1) When mounted on the board specified by Renesas; see note 1) Junction temperature Operating temperature Tj Ta 150 −20 to +60 °C °C Storage temperature Tstg −40 to +125 °C Notes: 1. The specifications of the board specified by Renesas are given below for reference. 2. Maximum allowable power dissipation Pd = 11.4 W (ambient temperature Ta = 25°C) with an ideal heat sink. Power dissipation Pd (W) Thermal derating curve 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 *2 Infinite heat sink *1 0 25 50 75 100 125 Ambient temperature Ta (˚C) Rev.1.0, Sep.19.2003, page 6 of 17 150 M61558FP Layer 1 (surface) Layer 2 (rear) *1 Thermal derating characteristics measured for the board specified by Renesas (Board specifications) Material: Glass epoxy FR-4 Dimensions: 70 × 70 mm Thickness: t = 1.6 mm (Wiring specifications for layers 1 and 2) Material: Copper Thickness: t = 18 mm Precautions on Usage 1. This product radiates heat even during normal operation, and reaches high temperatures. There is a possibility that characteristics failure or breakdown, including in peripheral components and circuits, may cause this product or peripherals to reach abnormally high temperatures. Also, please take special care when using this product as the final stage, since it may then be susceptible to damage because of external factors. This product is designed for consumer applications. Accordingly, please use it within the specified thermal conditions. Usage of the product in more relaxed thermal conditions may lead to malfunctions or damage to the product. 2. This product incorporates an over-current protection circuit which terminates the PWM operation when the peak instantaneous current from the VDA or the VDB power supply exceeds 7.5 A (designed value). Please note that it is never required to supply more current than this. The maximum-current value is roughly below 3 A during operation with a standard 4-Ω load. In usage, care is required with regard to the stability of the power-supply voltage. 3. Detection of an abnormality (when the PROUT pin (pin 21) becomes low) indicates a possibility of over current, so eliminate the cause, such as shorting of the output pins, and release the IC from the protection state (input low level on the EN pin (pin 25)). 4. This product includes MOS FET and CMOS logic circuits. Accordingly, electrostatic break down or latch-up may be generated within these elements. Please take the same care in using this product as in any case where MOS FET and CMOS logic LSIs are in use. Rev.1.0, Sep.19.2003, page 7 of 17 M61558FP Recommended Operating Condition Limits Item Symbol Min. Typ. Max. Unit Condition VD power-supply voltage VD 16 21 24 V VDA (pins 5, 6), VDB (pins 37, 38) VDD power-supply voltage VDD 10.8 12.0 13.2 V PWM frequency fpwm 0.7 1.5 MHz VDDA (pin 12), VDDB (pin 30), VDDP (pin 20) INA+ (pin 17), INB+ (pin 26) Min. operating pulse width High input voltage Tpw MIN VinH 40 4.0 5.0 ns V INA+ (pin 17), INB+ (pin 26) INA+ (pin 17), INB+ (pin 26) Low input voltage VinL 0.0 0.8 V INA+ (pin 17), INB+ (pin 26), EN (pin 25) Notes: 1. PWM operation Do not input a signal shorter than the minimum pulse width, since this may lead to unstable operation or, in the worst case, damage to the product. Since boot-strap operation is performed, an input signal with aperiodical high and low levels may lead to abnormal operation. Ensure that the PWM signal has periodical high and low levels. The capacitance of the capacitor for boot-strapping in the sample application diagram is for the product in operation at 768 kHz. The thermal conditions, etc., become looser with operation at lower PWM frequencies. 2. Power-supply voltage The normal operating condition for this product is VDD voltage < VD voltage, so ensure that this is the state during normal operation. Setting a lower VDD voltage increases the margin against damage but carries the danger of the under voltage detection circuit malfunctioning, so please ensure that VDD is maintained at 9 V or more. 3. Mounting (board) The board layout must be capable of handling the same high frequencies and high levels of power as are handled by this IC. Furthermore, components must be selected in consideration of both audio-frequency and high-frequency characteristics. Please external note that large surges are generated by parasitic inductances during high-speed switching. This IC is designed specifically for bridge-tied load (BTL) operation, so the design focus was on symmetry of sides A and B. The pattern on the board must also be highly symmetrical for BTL configuration. Rev.1.0, Sep.19.2003, page 8 of 17 M61558FP Electrical characteristics (Unless otherwise noted, Ta = 25°C, VDDP, VDDA, B = 12 V, VDA, B = 21 V) Limits Item Symbol Min. Typ. Max. Unit Condition of measurement IDDQS 15 mA PWM-suspended state IDDQ 35 mA No signal (f = 768 kHz, duty cycle = 50%) 40 mA No signal (f = 768 kHz, duty cycle = 50%) 1.0 V V Pins INA+, INB+, EN Pins INA+, INB+, EN −130 10 −65 µA µA Pin EN Pin EN Current drawn by the circuit VDD current circuit (suspended) VDD current circuit VD current circuit Signal interfaces High input signal Low input signal VIH VIL 2.3 High level input current Low level input current IIH IIL −10 −260 Low output voltage VOL 0.4 V Pin PROUT: IOL = 1 mA High-output (leakage) current IOH 10 µA Pin PROUT: VOH = 5 V Protection detectors VDD under voltage detection level VDDR 5.0 7.0 9.0 V Between VDD and GND, dropdetected to normal Hysteresis in VDD-detection voltage Over Temperature protection start temperature VDDH 0.5 V Normal to under voltage Tsd+ 150 °C Normal to over-temperature protection state* Over Temperature protection end temperature Tsd− 130 °C Over-temperature to normal state* Diode characteristics for boot-strap Diode forward-direction VFL voltage Diode forward-direction voltage Diode dynamic resistance 0.75 V HB output current = 100 µA VFH 1.0 V HB output current = 100 mA RDON 0.7 Ω HB output current = 100 mA 0.5 −0.75 V V ILO = 100 mA IHO = −100 mA V V ILO = 100 mA IHO = −100 mA Gate driver for low-side power transistor: “on” voltage Low level output voltage High level output voltage VOL VOH Gate driver for high-side power transistor: “on” voltage Low level output voltage High level output voltage VOL VOH 0.5 −0.75 *: Note that Tsd+, Tsd− are designed values for the IC’s internal temperature. Rev.1.0, Sep.19.2003, page 9 of 17 M61558FP (Unless otherwise noted, Ta = 25°C, VDDP and VDDA/B = 12 V, VDA/B = 21 V) Limits Item Symbol Min. Typ. Max. Unit Condition of measurement Output-stage DMOS transistor ON resistance Breakdown voltage between drain and source ON resistance between drain and source BVds 35 V Ileak=1mA rDS(ON) 0.20 Ω ID=100mA 1/tpf 768 KHz Boot-strap C = 0.022 uF tpw 40 ns Period = 1.3 us (f = 768 kHz) VDTC 1.35 V Connected resistance: 6.2 kΩ Input/output timing Reference input operating frequency Min. input pulse width Dead-time setting Pin 24 output voltage (Data for reference) AC characteristics Note: The reference values when the evaluation board specified by Renesas is used. (Unless otherwise specified, Ta = 25°C, VDDP and VDDA/B = 12 V, VDA/B = 21 V) Rated value Reference board setting condition Item Symbol Min. Typ. Max. Unit Measurement condition Output power 1 Po1 30 W Sine, 1 kHz/0 dB, modulation depth = 90% THD+N=1%,RL=6Ω, VDA/B=24V LPF=20KHz, HPF=400Hz Output power 2 Po2 30 W Sine, 1 kHz/0 dB, modulation depth = 90% Total harmonic distortion THD+N 0.04 % Sine, 1 kHz/0 dB, modulation depth = 50% THD+N=1%,RL=4Ω, VDA/B=21V LPF=20KHz, HPF=400Hz RL=4Ω, LPF=20KHz, HPF=400Hz Noise voltage Power efficiency Vno 150 µVrms Eff 85 % The MUTE signal is inputed Sine, 1 kHz/0 dB, modulation depth = 90% A-Weighted filter/ LPF=20KHz Po=30W, RL=4Ω Note: In the heat-radiation state of attachment to the board specified by Renesas, the M61558FP can continuously output 10 W (refer to the thermal derating curve on page 5). When more than 10 W is continuously output, heatradiation design measures such as heat sinks are required. Description of additional functions Dead-time control The dead-time value given below sets a period between LSGOUTA(B) and HSGOUTA(B) at the gate-driver outputs. This prevents through-current-induced damage to the output-stage power transistor. The dead-time setting is adjusted by the value of the external resistor on DTCNTL (pin 24). Rev.1.0, Sep.19.2003, page 10 of 17 M61558FP Note : The given values are design values, and the actual dead time is affected by the operating conditions (gateresistor value, switching characteristics, etc.) of the power transistor. Timing of input and output operations INA(B) HSGOUT A(B) LSGOUT A(B) Dead time Dead time Input pulse width (high level) Dead time and resistance setting (reference values for the pre-driver module) Dead time DT (ns) 20 15 10 5 0 10 20 30 Set resistance RDT (kΩ) Rev.1.0, Sep.19.2003, page 11 of 17 40 50 M61558FP Internal protective circuits 1. VDD under voltage detection circuit When the VDD power-supply voltage falls by a certain amount, the VDD under voltage protective circuit operates to prevent malfunctions of the IC. When an abnormality is detected, the output transistor on the H side is switched off, the output transistor on the L side is switched on, and a low level is output from the output pin. For the sake of automatic resumption, a low level is not output from PROUT (pin 21). Of the protection states, this is only the case for abnormal voltage-drop detection. The VDD detection circuit is connected to the common VDD power-supply pin, VDDP (pin 20). Please set up IC-external wiring to connect the VDDA/B (pins 12, 30) to VDDP. 2. Over Temperature protection circuit The IC incorporates an over temperature protection circuit (thermal shutdown circuit) that protects the IC from thermal damage when the temperature of the IC (chip) rises because of an abnormality. The protection circuit is activated before the IC’s internal junctions, etc., reach the thermal-damage temperature, and remains so until the temperature falls to the hysteresis condition, regardless of the state of the EN pin (pin 25). In the excessivetemperature condition, all output transistors are turned off, the output pins are released (open), and a low level is output from PROUT to issue a notification about the abnormal state. 3. Over current protection circuit This IC incorporates an excessive current protection circuit which terminates the PWM operation when the peak instantaneous value of current supplied from the VDA or VDB power supply exceeds 7.5 A (designed value). In the protection mode, all output transistors are switched off, all output pins are released (open), and a low level is output from PROUT to notify the system of the abnormal state. Note: The abnormality is detected on the positive side of the power-stage power supply. The conditions for detecting a load short between output pin and VDD. VDD are not more strict short between both output pins or between output pin and ground. Note that when shorting between VDD occurs, detection is not possible until the abnormality affects the positive side of the power supply, so the protective operation may not be performed. Functions when an abnormality is detected When an abnormality is detected, the IC operates asynchronously with respect to the PWM inputs (INA+, INB+), controls the output-stage n-channel transistor (H or L side) and enters the protection state. The states of the PROUT and OUT outputs and the states of each output-stage transistor are given in the table below. After the low level has been placed on PROUT, the protection state is maintained until the EN signal is low. State of output stage during protection operation Protection VDD voltage-drop protection Over Temperature, over-current protection OUTA outputstage transistor OUTB outputstage transistor PROUT output in case of abnormality OUTA output pin OUTB output pin H side L side H side L side No change (high) Low Low Off On Off On Output low, held until low level is placed on EN Open Open Off Off Off Off Resuming from abnormality detection Resumption to signal output from the individual abnormal state varies with the corresponding protective circuit. After the conditions for resumption have been satisfied, resumption occurs on the rising edge of either INA+ or INB+, whichever is earlier. The conditions for resumption from each abnormal state are given in the table below. Rev.1.0, Sep.19.2003, page 12 of 17 M61558FP Conditions required for resumption from abnormal states Abnormal state Condition for resumption VDD under voltage After the voltage has returned to the normal level and this has been confirmed by the internal VDD detection circuit, the IC resumes normal operation on the next rising edge of either INA+ or INB+. Over Temperature, over current After the state has returned to normal, the condition for resumption is the falling edge of EN. The IC then returns to normal operation on the next rising edge of either INA+ or INB+. Timing chart for protector detection-output PROUT (pin 21) and enable input EN (pin 25) Detctiond Protect detected (Over Temperature or Over current) (End of protect evnaition) Recovery of PROUT (on the falling edge of EN) Protector detection-circuit output PROUT (pin 21) Enable input EN (pin 25) 1 to 10 µs or less INA+ or INB+ Power-output stage FET control On input of the low level to EN (pin 19), normal operation resumes on the next rising edge of input signal INA+ or INB+. Normal operation Normal operation Protect Operation Rev.1.0, Sep.19.2003, page 13 of 17 M61558FP LPF circuit The output LPF circuit must have characteristics in accord with the signal-frequency band and characteristic impedance value of the speaker that constitutes the load. The simplest example is a second-order Butterworth filter in an LC configuration. Damping circuit When the speaker is removed, the frequency characteristics of the low-pass filter may lead to problems of high-band characteristics such as peaking. Accordingly, a high-band damping circuit should be installed in parallel with the speaker. (Take the allowable power, etc., of the damping resistor into consideration.) Zener diode for surge protection Ringing, etc., occurs during the high-speed switching operation of this IC. During short-circuit, connection to ground or VDD of load, very large surge voltages are generated. When the surge voltage exceeds the voltage tolerance of the transistors (step-down voltage between source and drain, etc.), the IC may be damaged. We recommend that you prevent damage to this IC by connecting a Zener diode for surge protection to the output pins (select a Zener voltage slightly below 35 V). Precautions on wiring for the protective circuits PRVD (pin 18) is wired to the protective detection circuits. Use as short a wiring run as is possible to connect this pin to a point on the VD power-supply line near the VD pin. This point should not be readily affected by variation in voltages due to power supply and the operating conditions. Please take care because this may affect the characteristics of the protective circuits or damage the IC. Measures against EMI Please note the need to reduce the levels of unwanted radiation components produced by high-speed switching operation. For example, apply countermeasures such as raising the order of the output LPF circuit, or attaching a capacitor with a value of about 1000 pF to the speaker pin. Single-ended operation This IC is for bridge-tied load (BTL) operation, but single-ended operation for an independent half-bridge configuration is possible. In this case, note that performance changes (e.g. 30 W x 1 ch. becomes 7.5 W x 2 ch). Also, other parts of the IC are designed on the specific assumption of BTL operation, so sufficient evaluation and examination is required. Pop noise when turning the power supply on and off One simple countermeasure against pop noise is to ensure that VD (power-stage power-supply voltage ) is only turned on and off while VDD (power-supply voltage of the pre-driver stage) is applied. If this measure is ignored, pop noise may occur when the power supply is turned on or off. We also recommend operation under the condition VDD < VD. Consider turning the power supply on and off in the following sequence. Rev.1.0, Sep.19.2003, page 14 of 17 M61558FP V Actual usage range VD power-supply voltage (power-stage) VDD power-supply voltage (pre-driver stage) t Heat sink Unlike the molded resin surface, the metal side of the package for heat radiation is slightly concave.Take this structure into consideration when designing a heat sink for use with high output levels. Capacitor for boot-strapping This IC is designed for PWM operation at around 768 kHz (high-speed PWM operation in the hundreds of kHz order). Accordingly, the value of the capacitor for boot-strapping in the diagram of the example application circuit is for such operation. If a large change is to be made to the PWM frequency, a correspondingly change in the value of this capacitor is required. Note that such usage was not presupposed in the design of this IC. Rev.1.0, Sep.19.2003, page 15 of 17 M61558FP Muting operation by force The output is forcibly muted by using a resistor to pull the PRLPFVD pin (pin 19) down to ground (signal output is terminated and the output terminals enter the Hi-Z open state; refer to the figure below). To cancel muting, release pin 19 from the pulled-down state, and then input a cancellation pulse on the EN pin (pin 25) in the same way as is used to cancel the protection state. Please note the following points: • Muted operation is only possible during normal operation; that is, it is not possible in transient states, such as while turning the power supply on or off. • For actual usage, please thoroughly evaluate and examine the forcible mute operation. Mute circuit R = 4.2 kΩ (see note) M61558FP 19 Note: The above setting assures operation by ensuring the flow of a strong current. Decreasing the resistance below this level has no effect. Rev.1.0, Sep.19.2003, page 16 of 17 M61558FP Package Dimensions 42P9R-E Note : Please contact Renesas Technology Corporation for further details. Rev.1.0, Sep.19.2003, page 17 of 17 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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